amr.c revision 1.38
1 /* $NetBSD: amr.c,v 1.38 2006/08/27 23:31:15 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999,2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 66 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 67 */ 68 69 /* 70 * Driver for AMI RAID controllers. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.38 2006/08/27 23:31:15 christos Exp $"); 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 #include <sys/proc.h> 82 #include <sys/buf.h> 83 #include <sys/malloc.h> 84 #include <sys/conf.h> 85 #include <sys/kthread.h> 86 87 #include <uvm/uvm_extern.h> 88 89 #include <machine/endian.h> 90 #include <machine/bus.h> 91 92 #include <dev/pci/pcidevs.h> 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/amrreg.h> 95 #include <dev/pci/amrvar.h> 96 #include <dev/pci/amrio.h> 97 98 #include "locators.h" 99 100 static void amr_attach(struct device *, struct device *, void *); 101 static void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 102 static void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, 103 void *); 104 static int amr_init(struct amr_softc *, const char *, 105 struct pci_attach_args *pa); 106 static int amr_intr(void *); 107 static int amr_match(struct device *, struct cfdata *, void *); 108 static int amr_print(void *, const char *); 109 static void amr_shutdown(void *); 110 static void amr_teardown(struct amr_softc *); 111 static void amr_thread(void *); 112 static void amr_thread_create(void *); 113 114 static int amr_quartz_get_work(struct amr_softc *, 115 struct amr_mailbox_resp *); 116 static int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 117 static int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 118 static int amr_std_submit(struct amr_softc *, struct amr_ccb *); 119 120 static dev_type_open(amropen); 121 static dev_type_close(amrclose); 122 static dev_type_ioctl(amrioctl); 123 124 CFATTACH_DECL(amr, sizeof(struct amr_softc), 125 amr_match, amr_attach, NULL, NULL); 126 127 const struct cdevsw amr_cdevsw = { 128 amropen, amrclose, noread, nowrite, amrioctl, 129 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 130 }; 131 132 extern struct cfdriver amr_cd; 133 134 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 135 #define AT_SIG 0x02 /* Check for signature */ 136 137 static struct amr_pci_type { 138 u_short apt_vendor; 139 u_short apt_product; 140 u_short apt_flags; 141 } const amr_pci_type[] = { 142 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 143 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 144 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 145 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 149 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 150 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 151 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 152 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4ESI, AT_QUARTZ }, 153 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_PERC_4SC, AT_QUARTZ }, 154 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 155 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 156 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 157 }; 158 159 static struct amr_typestr { 160 const char *at_str; 161 int at_sig; 162 } const amr_typestr[] = { 163 { "Series 431", AMR_SIG_431 }, 164 { "Series 438", AMR_SIG_438 }, 165 { "Series 466", AMR_SIG_466 }, 166 { "Series 467", AMR_SIG_467 }, 167 { "Series 490", AMR_SIG_490 }, 168 { "Series 762", AMR_SIG_762 }, 169 { "HP NetRAID (T5)", AMR_SIG_T5 }, 170 { "HP NetRAID (T7)", AMR_SIG_T7 }, 171 }; 172 173 static struct { 174 const char *ds_descr; 175 int ds_happy; 176 } const amr_dstate[] = { 177 { "offline", 0 }, 178 { "degraded", 1 }, 179 { "optimal", 1 }, 180 { "online", 1 }, 181 { "failed", 0 }, 182 { "rebuilding", 1 }, 183 { "hotspare", 0 }, 184 }; 185 186 static void *amr_sdh; 187 188 static int amr_max_segs; 189 int amr_max_xfer; 190 191 static inline u_int8_t 192 amr_inb(struct amr_softc *amr, int off) 193 { 194 195 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 196 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 197 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 198 } 199 200 static inline u_int32_t 201 amr_inl(struct amr_softc *amr, int off) 202 { 203 204 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 205 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 206 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 207 } 208 209 static inline void 210 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 211 { 212 213 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 214 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 215 BUS_SPACE_BARRIER_WRITE); 216 } 217 218 static inline void 219 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 220 { 221 222 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 223 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 224 BUS_SPACE_BARRIER_WRITE); 225 } 226 227 /* 228 * Match a supported device. 229 */ 230 static int 231 amr_match(struct device *parent, struct cfdata *match, void *aux) 232 { 233 struct pci_attach_args *pa; 234 pcireg_t s; 235 int i; 236 237 pa = (struct pci_attach_args *)aux; 238 239 /* 240 * Don't match the device if it's operating in I2O mode. In this 241 * case it should be handled by the `iop' driver. 242 */ 243 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 244 return (0); 245 246 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 247 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 248 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 249 break; 250 251 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 252 return (0); 253 254 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 255 return (1); 256 257 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 258 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 259 } 260 261 /* 262 * Attach a supported device. 263 */ 264 static void 265 amr_attach(struct device *parent, struct device *self, void *aux) 266 { 267 struct pci_attach_args *pa; 268 struct amr_attach_args amra; 269 const struct amr_pci_type *apt; 270 struct amr_softc *amr; 271 pci_chipset_tag_t pc; 272 pci_intr_handle_t ih; 273 const char *intrstr; 274 pcireg_t reg; 275 int rseg, i, j, size, rv, memreg, ioreg; 276 struct amr_ccb *ac; 277 int locs[AMRCF_NLOCS]; 278 279 aprint_naive(": RAID controller\n"); 280 281 amr = (struct amr_softc *)self; 282 pa = (struct pci_attach_args *)aux; 283 pc = pa->pa_pc; 284 285 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 286 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 287 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 288 break; 289 apt = amr_pci_type + i; 290 291 memreg = ioreg = 0; 292 for (i = 0x10; i <= 0x14; i += 4) { 293 reg = pci_conf_read(pc, pa->pa_tag, i); 294 switch (PCI_MAPREG_TYPE(reg)) { 295 case PCI_MAPREG_TYPE_MEM: 296 if (PCI_MAPREG_MEM_SIZE(reg) != 0) 297 memreg = i; 298 break; 299 case PCI_MAPREG_TYPE_IO: 300 if (PCI_MAPREG_IO_SIZE(reg) != 0) 301 ioreg = i; 302 break; 303 304 } 305 } 306 307 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 308 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 309 ; 310 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 311 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 312 ; 313 else { 314 aprint_error("can't map control registers\n"); 315 amr_teardown(amr); 316 return; 317 } 318 319 amr->amr_flags |= AMRF_PCI_REGS; 320 amr->amr_dmat = pa->pa_dmat; 321 amr->amr_pc = pa->pa_pc; 322 323 /* Enable the device. */ 324 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 325 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 326 reg | PCI_COMMAND_MASTER_ENABLE); 327 328 /* Map and establish the interrupt. */ 329 if (pci_intr_map(pa, &ih)) { 330 aprint_error("can't map interrupt\n"); 331 amr_teardown(amr); 332 return; 333 } 334 intrstr = pci_intr_string(pc, ih); 335 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); 336 if (amr->amr_ih == NULL) { 337 aprint_error("can't establish interrupt"); 338 if (intrstr != NULL) 339 aprint_normal(" at %s", intrstr); 340 aprint_normal("\n"); 341 amr_teardown(amr); 342 return; 343 } 344 amr->amr_flags |= AMRF_PCI_INTR; 345 346 /* 347 * Allocate space for the mailbox and S/G lists. Some controllers 348 * don't like S/G lists to be located below 0x2000, so we allocate 349 * enough slop to enable us to compensate. 350 * 351 * The standard mailbox structure needs to be aligned on a 16-byte 352 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 353 * size, which preceeds the standard mailbox. 354 */ 355 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 356 amr->amr_dmasize = size; 357 358 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, 359 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 360 aprint_error("%s: unable to allocate buffer, rv = %d\n", 361 amr->amr_dv.dv_xname, rv); 362 amr_teardown(amr); 363 return; 364 } 365 amr->amr_flags |= AMRF_DMA_ALLOC; 366 367 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 368 (caddr_t *)&amr->amr_mbox, 369 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 370 aprint_error("%s: unable to map buffer, rv = %d\n", 371 amr->amr_dv.dv_xname, rv); 372 amr_teardown(amr); 373 return; 374 } 375 amr->amr_flags |= AMRF_DMA_MAP; 376 377 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 378 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 379 aprint_error("%s: unable to create buffer DMA map, rv = %d\n", 380 amr->amr_dv.dv_xname, rv); 381 amr_teardown(amr); 382 return; 383 } 384 amr->amr_flags |= AMRF_DMA_CREATE; 385 386 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 387 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 388 aprint_error("%s: unable to load buffer DMA map, rv = %d\n", 389 amr->amr_dv.dv_xname, rv); 390 amr_teardown(amr); 391 return; 392 } 393 amr->amr_flags |= AMRF_DMA_LOAD; 394 395 memset(amr->amr_mbox, 0, size); 396 397 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 398 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 399 amr->amr_sgls = (struct amr_sgentry *)((caddr_t)amr->amr_mbox + 400 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 401 402 /* 403 * Allocate and initalise the command control blocks. 404 */ 405 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); 406 amr->amr_ccbs = ac; 407 SLIST_INIT(&amr->amr_ccb_freelist); 408 TAILQ_INIT(&amr->amr_ccb_active); 409 amr->amr_flags |= AMRF_CCBS; 410 411 if (amr_max_xfer == 0) { 412 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); 413 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 414 } 415 416 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 417 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 418 amr_max_segs, amr_max_xfer, 0, 419 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 420 if (rv != 0) 421 break; 422 423 ac->ac_ident = i; 424 amr_ccb_free(amr, ac); 425 } 426 if (i != AMR_MAX_CMDS) { 427 aprint_error("%s: memory exhausted\n", amr->amr_dv.dv_xname); 428 amr_teardown(amr); 429 return; 430 } 431 432 /* 433 * Take care of model-specific tasks. 434 */ 435 if ((apt->apt_flags & AT_QUARTZ) != 0) { 436 amr->amr_submit = amr_quartz_submit; 437 amr->amr_get_work = amr_quartz_get_work; 438 } else { 439 amr->amr_submit = amr_std_submit; 440 amr->amr_get_work = amr_std_get_work; 441 442 /* Notify the controller of the mailbox location. */ 443 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 444 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 445 446 /* Clear outstanding interrupts and enable interrupts. */ 447 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 448 amr_outb(amr, AMR_SREG_TOGL, 449 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 450 } 451 452 /* 453 * Retrieve parameters, and tell the world about us. 454 */ 455 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); 456 amr->amr_flags |= AMRF_ENQBUF; 457 amr->amr_maxqueuecnt = i; 458 aprint_normal(": AMI RAID "); 459 if (amr_init(amr, intrstr, pa) != 0) { 460 amr_teardown(amr); 461 return; 462 } 463 464 /* 465 * Cap the maximum number of outstanding commands. AMI's Linux 466 * driver doesn't trust the controller's reported value, and lockups 467 * have been seen when we do. 468 */ 469 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 470 if (amr->amr_maxqueuecnt > i) 471 amr->amr_maxqueuecnt = i; 472 473 /* Set our `shutdownhook' before we start any device activity. */ 474 if (amr_sdh == NULL) 475 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 476 477 /* Attach sub-devices. */ 478 for (j = 0; j < amr->amr_numdrives; j++) { 479 if (amr->amr_drive[j].al_size == 0) 480 continue; 481 amra.amra_unit = j; 482 483 locs[AMRCF_UNIT] = j; 484 485 amr->amr_drive[j].al_dv = config_found_sm_loc(&amr->amr_dv, 486 "amr", locs, &amra, amr_print, config_stdsubmatch); 487 } 488 489 SIMPLEQ_INIT(&amr->amr_ccb_queue); 490 491 /* XXX This doesn't work for newer boards yet. */ 492 if ((apt->apt_flags & AT_QUARTZ) == 0) 493 kthread_create(amr_thread_create, amr); 494 } 495 496 /* 497 * Free up resources. 498 */ 499 static void 500 amr_teardown(struct amr_softc *amr) 501 { 502 struct amr_ccb *ac; 503 int fl; 504 505 fl = amr->amr_flags; 506 507 if ((fl & AMRF_THREAD) != 0) { 508 amr->amr_flags |= AMRF_THREAD_EXIT; 509 wakeup(amr_thread); 510 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) 511 tsleep(&amr->amr_flags, PWAIT, "amrexit", 0); 512 } 513 if ((fl & AMRF_CCBS) != 0) { 514 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 515 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 516 } 517 free(amr->amr_ccbs, M_DEVBUF); 518 } 519 if ((fl & AMRF_ENQBUF) != 0) 520 free(amr->amr_enqbuf, M_DEVBUF); 521 if ((fl & AMRF_DMA_LOAD) != 0) 522 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 523 if ((fl & AMRF_DMA_MAP) != 0) 524 bus_dmamem_unmap(amr->amr_dmat, (caddr_t)amr->amr_mbox, 525 amr->amr_dmasize); 526 if ((fl & AMRF_DMA_ALLOC) != 0) 527 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 528 if ((fl & AMRF_DMA_CREATE) != 0) 529 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 530 if ((fl & AMRF_PCI_INTR) != 0) 531 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 532 if ((fl & AMRF_PCI_REGS) != 0) 533 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 534 } 535 536 /* 537 * Print autoconfiguration message for a sub-device. 538 */ 539 static int 540 amr_print(void *aux, const char *pnp) 541 { 542 struct amr_attach_args *amra; 543 544 amra = (struct amr_attach_args *)aux; 545 546 if (pnp != NULL) 547 aprint_normal("block device at %s", pnp); 548 aprint_normal(" unit %d", amra->amra_unit); 549 return (UNCONF); 550 } 551 552 /* 553 * Retrieve operational parameters and describe the controller. 554 */ 555 static int 556 amr_init(struct amr_softc *amr, const char *intrstr, 557 struct pci_attach_args *pa) 558 { 559 struct amr_adapter_info *aa; 560 struct amr_prodinfo *ap; 561 struct amr_enquiry *ae; 562 struct amr_enquiry3 *aex; 563 const char *prodstr; 564 u_int i, sig, ishp; 565 char sbuf[64]; 566 567 /* 568 * Try to get 40LD product info, which tells us what the card is 569 * labelled as. 570 */ 571 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 572 amr->amr_enqbuf); 573 if (ap != NULL) { 574 aprint_normal("<%.80s>\n", ap->ap_product); 575 if (intrstr != NULL) 576 aprint_normal("%s: interrupting at %s\n", 577 amr->amr_dv.dv_xname, intrstr); 578 aprint_normal("%s: firmware %.16s, BIOS %.16s, %dMB RAM\n", 579 amr->amr_dv.dv_xname, ap->ap_firmware, ap->ap_bios, 580 le16toh(ap->ap_memsize)); 581 582 amr->amr_maxqueuecnt = ap->ap_maxio; 583 584 /* 585 * Fetch and record state of logical drives. 586 */ 587 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 588 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 589 if (aex == NULL) { 590 aprint_error("%s ENQUIRY3 failed\n", 591 amr->amr_dv.dv_xname); 592 return (-1); 593 } 594 595 if (aex->ae_numldrives > __arraycount(aex->ae_drivestate)) { 596 aprint_error("%s: Inquiry returned more drives (%d)" 597 " than the array can handle (%zu)\n", 598 amr->amr_dv.dv_xname, aex->ae_numldrives, 599 __arraycount(aex->ae_drivestate)); 600 aex->ae_numldrives = __arraycount(aex->ae_drivestate); 601 } 602 if (aex->ae_numldrives > AMR_MAX_UNITS) { 603 aprint_error( 604 "%s: adjust AMR_MAX_UNITS to %d (currently %d)" 605 "\n", amr->amr_dv.dv_xname, AMR_MAX_UNITS, 606 amr->amr_numdrives); 607 amr->amr_numdrives = AMR_MAX_UNITS; 608 } else 609 amr->amr_numdrives = aex->ae_numldrives; 610 611 for (i = 0; i < amr->amr_numdrives; i++) { 612 amr->amr_drive[i].al_size = 613 le32toh(aex->ae_drivesize[i]); 614 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 615 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 616 } 617 618 return (0); 619 } 620 621 /* 622 * Try 8LD extended ENQUIRY to get the controller signature. Once 623 * found, search for a product description. 624 */ 625 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 626 if (ae != NULL) { 627 i = 0; 628 sig = le32toh(ae->ae_signature); 629 630 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 631 if (amr_typestr[i].at_sig == sig) 632 break; 633 i++; 634 } 635 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 636 snprintf(sbuf, sizeof(sbuf), 637 "unknown ENQUIRY2 sig (0x%08x)", sig); 638 prodstr = sbuf; 639 } else 640 prodstr = amr_typestr[i].at_str; 641 } else { 642 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 643 if (ae == NULL) { 644 aprint_error("%s: unsupported controller\n", 645 amr->amr_dv.dv_xname); 646 return (-1); 647 } 648 649 switch (PCI_PRODUCT(pa->pa_id)) { 650 case PCI_PRODUCT_AMI_MEGARAID: 651 prodstr = "Series 428"; 652 break; 653 case PCI_PRODUCT_AMI_MEGARAID2: 654 prodstr = "Series 434"; 655 break; 656 default: 657 snprintf(sbuf, sizeof(sbuf), "unknown PCI dev (0x%04x)", 658 PCI_PRODUCT(pa->pa_id)); 659 prodstr = sbuf; 660 break; 661 } 662 } 663 664 /* 665 * HP NetRaid controllers have a special encoding of the firmware 666 * and BIOS versions. The AMI version seems to have it as strings 667 * whereas the HP version does it with a leading uppercase character 668 * and two binary numbers. 669 */ 670 aa = &ae->ae_adapter; 671 672 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 673 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 674 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 675 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 676 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 677 /* The AMI 438 is a NetRaid 3si in HP-land. */ 678 prodstr = "HP NetRaid 3si"; 679 } 680 ishp = 1; 681 } else 682 ishp = 0; 683 684 aprint_normal("<%s>\n", prodstr); 685 if (intrstr != NULL) 686 aprint_normal("%s: interrupting at %s\n", amr->amr_dv.dv_xname, 687 intrstr); 688 689 if (ishp) 690 aprint_normal("%s: firmware <%c.%02d.%02d>, BIOS <%c.%02d.%02d>" 691 ", %dMB RAM\n", amr->amr_dv.dv_xname, aa->aa_firmware[2], 692 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 693 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 694 else 695 aprint_normal("%s: firmware <%.4s>, BIOS <%.4s>, %dMB RAM\n", 696 amr->amr_dv.dv_xname, aa->aa_firmware, aa->aa_bios, 697 aa->aa_memorysize); 698 699 amr->amr_maxqueuecnt = aa->aa_maxio; 700 701 /* 702 * Record state of logical drives. 703 */ 704 if (ae->ae_ldrv.al_numdrives > __arraycount(ae->ae_ldrv.al_size)) { 705 aprint_error("%s: Inquiry returned more drives (%d)" 706 " than the array can handle (%zu)\n", 707 amr->amr_dv.dv_xname, ae->ae_ldrv.al_numdrives, 708 __arraycount(ae->ae_ldrv.al_size)); 709 ae->ae_ldrv.al_numdrives = __arraycount(ae->ae_ldrv.al_size); 710 } 711 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 712 aprint_error("%s: adjust AMR_MAX_UNITS to %d (currently %d)\n", 713 amr->amr_dv.dv_xname, ae->ae_ldrv.al_numdrives, 714 AMR_MAX_UNITS); 715 amr->amr_numdrives = AMR_MAX_UNITS; 716 } else 717 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 718 719 for (i = 0; i < amr->amr_numdrives; i++) { 720 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 721 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 722 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 723 } 724 725 return (0); 726 } 727 728 /* 729 * Flush the internal cache on each configured controller. Called at 730 * shutdown time. 731 */ 732 static void 733 amr_shutdown(void *cookie) 734 { 735 extern struct cfdriver amr_cd; 736 struct amr_softc *amr; 737 struct amr_ccb *ac; 738 int i, rv, s; 739 740 for (i = 0; i < amr_cd.cd_ndevs; i++) { 741 if ((amr = device_lookup(&amr_cd, i)) == NULL) 742 continue; 743 744 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 745 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 746 s = splbio(); 747 rv = amr_ccb_poll(amr, ac, 30000); 748 splx(s); 749 amr_ccb_free(amr, ac); 750 } 751 if (rv != 0) 752 printf("%s: unable to flush cache (%d)\n", 753 amr->amr_dv.dv_xname, rv); 754 } 755 } 756 757 /* 758 * Interrupt service routine. 759 */ 760 static int 761 amr_intr(void *cookie) 762 { 763 struct amr_softc *amr; 764 struct amr_ccb *ac; 765 struct amr_mailbox_resp mbox; 766 u_int i, forus, idx; 767 768 amr = cookie; 769 forus = 0; 770 771 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 772 /* Iterate over completed commands in this result. */ 773 for (i = 0; i < mbox.mb_nstatus; i++) { 774 idx = mbox.mb_completed[i] - 1; 775 ac = amr->amr_ccbs + idx; 776 777 if (idx >= amr->amr_maxqueuecnt) { 778 printf("%s: bad status (bogus ID: %u=%u)\n", 779 amr->amr_dv.dv_xname, i, idx); 780 continue; 781 } 782 783 if ((ac->ac_flags & AC_ACTIVE) == 0) { 784 printf("%s: bad status (not active; 0x04%x)\n", 785 amr->amr_dv.dv_xname, ac->ac_flags); 786 continue; 787 } 788 789 ac->ac_status = mbox.mb_status; 790 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 791 AC_COMPLETE; 792 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 793 794 if ((ac->ac_flags & AC_MOAN) != 0) 795 printf("%s: ccb %d completed\n", 796 amr->amr_dv.dv_xname, ac->ac_ident); 797 798 /* Pass notification to upper layers. */ 799 if (ac->ac_handler != NULL) 800 (*ac->ac_handler)(ac); 801 else 802 wakeup(ac); 803 } 804 forus = 1; 805 } 806 807 if (forus) 808 amr_ccb_enqueue(amr, NULL); 809 810 return (forus); 811 } 812 813 /* 814 * Create the watchdog thread. 815 */ 816 static void 817 amr_thread_create(void *cookie) 818 { 819 struct amr_softc *amr; 820 int rv; 821 822 amr = cookie; 823 824 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 825 amr->amr_flags ^= AMRF_THREAD_EXIT; 826 wakeup(&amr->amr_flags); 827 return; 828 } 829 830 rv = kthread_create1(amr_thread, amr, &amr->amr_thread, "%s", 831 amr->amr_dv.dv_xname); 832 if (rv != 0) 833 aprint_error("%s: unable to create thread (%d)", 834 amr->amr_dv.dv_xname, rv); 835 else 836 amr->amr_flags |= AMRF_THREAD; 837 } 838 839 /* 840 * Watchdog thread. 841 */ 842 static void 843 amr_thread(void *cookie) 844 { 845 struct amr_softc *amr; 846 struct amr_ccb *ac; 847 struct amr_logdrive *al; 848 struct amr_enquiry *ae; 849 int rv, i, s; 850 851 amr = cookie; 852 ae = amr->amr_enqbuf; 853 854 for (;;) { 855 tsleep(amr_thread, PWAIT, "amrwdog", AMR_WDOG_TICKS); 856 857 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 858 amr->amr_flags ^= AMRF_THREAD_EXIT; 859 wakeup(&amr->amr_flags); 860 kthread_exit(0); 861 } 862 863 s = splbio(); 864 amr_intr(cookie); 865 ac = TAILQ_FIRST(&amr->amr_ccb_active); 866 while (ac != NULL) { 867 if (ac->ac_start_time + AMR_TIMEOUT > time_uptime) 868 break; 869 if ((ac->ac_flags & AC_MOAN) == 0) { 870 printf("%s: ccb %d timed out; mailbox:\n", 871 amr->amr_dv.dv_xname, ac->ac_ident); 872 amr_ccb_dump(amr, ac); 873 ac->ac_flags |= AC_MOAN; 874 } 875 ac = TAILQ_NEXT(ac, ac_chain.tailq); 876 } 877 splx(s); 878 879 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 880 printf("%s: ccb_alloc failed (%d)\n", 881 amr->amr_dv.dv_xname, rv); 882 continue; 883 } 884 885 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 886 887 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 888 AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 889 if (rv != 0) { 890 printf("%s: ccb_map failed (%d)\n", 891 amr->amr_dv.dv_xname, rv); 892 amr_ccb_free(amr, ac); 893 continue; 894 } 895 896 rv = amr_ccb_wait(amr, ac); 897 amr_ccb_unmap(amr, ac); 898 if (rv != 0) { 899 printf("%s: enquiry failed (st=%d)\n", 900 amr->amr_dv.dv_xname, ac->ac_status); 901 continue; 902 } 903 amr_ccb_free(amr, ac); 904 905 al = amr->amr_drive; 906 for (i = 0; i < __arraycount(ae->ae_ldrv.al_state); i++, al++) { 907 if (al->al_dv == NULL) 908 continue; 909 if (al->al_state == ae->ae_ldrv.al_state[i]) 910 continue; 911 912 printf("%s: state changed: %s -> %s\n", 913 al->al_dv->dv_xname, 914 amr_drive_state(al->al_state, NULL), 915 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 916 917 al->al_state = ae->ae_ldrv.al_state[i]; 918 } 919 } 920 } 921 922 /* 923 * Return a text description of a logical drive's current state. 924 */ 925 const char * 926 amr_drive_state(int state, int *happy) 927 { 928 const char *str; 929 930 state = AMR_DRV_CURSTATE(state); 931 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 932 if (happy) 933 *happy = 1; 934 str = "status unknown"; 935 } else { 936 if (happy) 937 *happy = amr_dstate[state].ds_happy; 938 str = amr_dstate[state].ds_descr; 939 } 940 941 return (str); 942 } 943 944 /* 945 * Run a generic enquiry-style command. 946 */ 947 static void * 948 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 949 u_int8_t cmdqual, void *sbuf) 950 { 951 struct amr_ccb *ac; 952 u_int8_t *mb; 953 int rv; 954 955 if (amr_ccb_alloc(amr, &ac) != 0) 956 return (NULL); 957 958 /* Build the command proper. */ 959 mb = (u_int8_t *)&ac->ac_cmd; 960 mb[0] = cmd; 961 mb[2] = cmdsub; 962 mb[3] = cmdqual; 963 964 rv = amr_ccb_map(amr, ac, sbuf, AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 965 if (rv == 0) { 966 rv = amr_ccb_poll(amr, ac, 2000); 967 amr_ccb_unmap(amr, ac); 968 } 969 amr_ccb_free(amr, ac); 970 971 return (rv ? NULL : sbuf); 972 } 973 974 /* 975 * Allocate and initialise a CCB. 976 */ 977 int 978 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 979 { 980 int s; 981 982 s = splbio(); 983 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 984 splx(s); 985 return (EAGAIN); 986 } 987 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 988 splx(s); 989 990 return (0); 991 } 992 993 /* 994 * Free a CCB. 995 */ 996 void 997 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 998 { 999 int s; 1000 1001 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 1002 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 1003 ac->ac_cmd.mb_busy = 1; 1004 ac->ac_handler = NULL; 1005 ac->ac_flags = 0; 1006 1007 s = splbio(); 1008 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 1009 splx(s); 1010 } 1011 1012 /* 1013 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1014 * the order that they were enqueued and try to submit their command blocks 1015 * to the controller for execution. 1016 */ 1017 void 1018 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 1019 { 1020 int s; 1021 1022 s = splbio(); 1023 1024 if (ac != NULL) 1025 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 1026 1027 while ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1028 if ((*amr->amr_submit)(amr, ac) != 0) 1029 break; 1030 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, ac_chain.simpleq); 1031 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1032 } 1033 1034 splx(s); 1035 } 1036 1037 /* 1038 * Map the specified CCB's data buffer onto the bus, and fill the 1039 * scatter-gather list. 1040 */ 1041 int 1042 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1043 int tflag) 1044 { 1045 struct amr_sgentry *sge; 1046 struct amr_mailbox_cmd *mb; 1047 int nsegs, i, rv, sgloff; 1048 bus_dmamap_t xfer; 1049 int dmaflag = 0; 1050 1051 xfer = ac->ac_xfer_map; 1052 1053 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1054 BUS_DMA_NOWAIT); 1055 if (rv != 0) 1056 return (rv); 1057 1058 mb = &ac->ac_cmd; 1059 ac->ac_xfer_size = size; 1060 ac->ac_flags |= (tflag & (AC_XFER_OUT | AC_XFER_IN)); 1061 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1062 1063 if (tflag & AC_XFER_OUT) 1064 dmaflag |= BUS_DMASYNC_PREWRITE; 1065 if (tflag & AC_XFER_IN) 1066 dmaflag |= BUS_DMASYNC_PREREAD; 1067 1068 /* We don't need to use a scatter/gather list for just 1 segment. */ 1069 nsegs = xfer->dm_nsegs; 1070 if (nsegs == 1) { 1071 mb->mb_nsgelem = 0; 1072 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1073 ac->ac_flags |= AC_NOSGL; 1074 } else { 1075 mb->mb_nsgelem = nsegs; 1076 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1077 1078 sge = (struct amr_sgentry *)((caddr_t)amr->amr_sgls + sgloff); 1079 for (i = 0; i < nsegs; i++, sge++) { 1080 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1081 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1082 } 1083 } 1084 1085 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, dmaflag); 1086 1087 if ((ac->ac_flags & AC_NOSGL) == 0) 1088 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1089 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1090 1091 return (0); 1092 } 1093 1094 /* 1095 * Unmap the specified CCB's data buffer. 1096 */ 1097 void 1098 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1099 { 1100 int dmaflag = 0; 1101 1102 if (ac->ac_flags & AC_XFER_IN) 1103 dmaflag |= BUS_DMASYNC_POSTREAD; 1104 if (ac->ac_flags & AC_XFER_OUT) 1105 dmaflag |= BUS_DMASYNC_POSTWRITE; 1106 1107 if ((ac->ac_flags & AC_NOSGL) == 0) 1108 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1109 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1110 BUS_DMASYNC_POSTWRITE); 1111 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1112 dmaflag); 1113 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1114 } 1115 1116 /* 1117 * Submit a command to the controller and poll on completion. Return 1118 * non-zero on timeout or error. Must be called with interrupts blocked. 1119 */ 1120 int 1121 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1122 { 1123 int rv; 1124 1125 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) 1126 return (rv); 1127 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1128 1129 for (timo *= 10; timo != 0; timo--) { 1130 amr_intr(amr); 1131 if ((ac->ac_flags & AC_COMPLETE) != 0) 1132 break; 1133 DELAY(100); 1134 } 1135 1136 return (timo == 0 || ac->ac_status != 0 ? EIO : 0); 1137 } 1138 1139 /* 1140 * Submit a command to the controller and sleep on completion. Return 1141 * non-zero on error. 1142 */ 1143 int 1144 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1145 { 1146 int s; 1147 1148 s = splbio(); 1149 amr_ccb_enqueue(amr, ac); 1150 tsleep(ac, PRIBIO, "amrcmd", 0); 1151 splx(s); 1152 1153 return (ac->ac_status != 0 ? EIO : 0); 1154 } 1155 1156 #if 0 1157 /* 1158 * Wait for the mailbox to become available. 1159 */ 1160 static int 1161 amr_mbox_wait(struct amr_softc *amr) 1162 { 1163 int timo; 1164 1165 for (timo = 10000; timo != 0; timo--) { 1166 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1167 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1168 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1169 break; 1170 DELAY(100); 1171 } 1172 1173 if (timo == 0) 1174 printf("%s: controller wedged\n", amr->amr_dv.dv_xname); 1175 1176 return (timo != 0 ? 0 : EAGAIN); 1177 } 1178 #endif 1179 1180 /* 1181 * Tell the controller that the mailbox contains a valid command. Must be 1182 * called with interrupts blocked. 1183 */ 1184 static int 1185 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1186 { 1187 u_int32_t v; 1188 1189 amr->amr_mbox->mb_poll = 0; 1190 amr->amr_mbox->mb_ack = 0; 1191 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1192 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1193 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1194 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1195 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1196 return (EAGAIN); 1197 1198 v = amr_inl(amr, AMR_QREG_IDB); 1199 if ((v & AMR_QIDB_SUBMIT) != 0) { 1200 amr->amr_mbox->mb_cmd.mb_busy = 0; 1201 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1202 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1203 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1204 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1205 return (EAGAIN); 1206 } 1207 1208 amr->amr_mbox->mb_segment = 0; 1209 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1210 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1211 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1212 1213 ac->ac_start_time = time_uptime; 1214 ac->ac_flags |= AC_ACTIVE; 1215 amr_outl(amr, AMR_QREG_IDB, 1216 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1217 return (0); 1218 } 1219 1220 static int 1221 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1222 { 1223 1224 amr->amr_mbox->mb_poll = 0; 1225 amr->amr_mbox->mb_ack = 0; 1226 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1227 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1228 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1229 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1230 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1231 return (EAGAIN); 1232 1233 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1234 amr->amr_mbox->mb_cmd.mb_busy = 0; 1235 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1236 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1237 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1238 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1239 return (EAGAIN); 1240 } 1241 1242 amr->amr_mbox->mb_segment = 0; 1243 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1244 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1245 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1246 1247 ac->ac_start_time = time_uptime; 1248 ac->ac_flags |= AC_ACTIVE; 1249 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1250 return (0); 1251 } 1252 1253 /* 1254 * Claim any work that the controller has completed; acknowledge completion, 1255 * save details of the completion in (mbsave). Must be called with 1256 * interrupts blocked. 1257 */ 1258 static int 1259 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1260 { 1261 1262 /* Work waiting for us? */ 1263 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1264 return (-1); 1265 1266 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1267 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1268 1269 /* Save the mailbox, which contains a list of completed commands. */ 1270 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1271 1272 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1273 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1274 1275 /* Ack the interrupt and mailbox transfer. */ 1276 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1277 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1278 1279 /* 1280 * This waits for the controller to notice that we've taken the 1281 * command from it. It's very inefficient, and we shouldn't do it, 1282 * but if we remove this code, we stop completing commands under 1283 * load. 1284 * 1285 * Peter J says we shouldn't do this. The documentation says we 1286 * should. Who is right? 1287 */ 1288 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1289 DELAY(10); 1290 1291 return (0); 1292 } 1293 1294 static int 1295 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1296 { 1297 u_int8_t istat; 1298 1299 /* Check for valid interrupt status. */ 1300 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1301 return (-1); 1302 1303 /* Ack the interrupt. */ 1304 amr_outb(amr, AMR_SREG_INTR, istat); 1305 1306 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1307 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1308 1309 /* Save mailbox, which contains a list of completed commands. */ 1310 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1311 1312 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1313 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1314 1315 /* Ack mailbox transfer. */ 1316 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1317 1318 return (0); 1319 } 1320 1321 static void 1322 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1323 { 1324 int i; 1325 1326 printf("%s: ", amr->amr_dv.dv_xname); 1327 for (i = 0; i < 4; i++) 1328 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1329 printf("\n"); 1330 } 1331 1332 static int 1333 amropen(dev_t dev, int flag, int mode, struct lwp *l) 1334 { 1335 struct amr_softc *amr; 1336 1337 if ((amr = device_lookup(&amr_cd, minor(dev))) == NULL) 1338 return (ENXIO); 1339 if ((amr->amr_flags & AMRF_OPEN) != 0) 1340 return (EBUSY); 1341 1342 amr->amr_flags |= AMRF_OPEN; 1343 return (0); 1344 } 1345 1346 static int 1347 amrclose(dev_t dev, int flag, int mode, struct lwp *l) 1348 { 1349 struct amr_softc *amr; 1350 1351 amr = device_lookup(&amr_cd, minor(dev)); 1352 amr->amr_flags &= ~AMRF_OPEN; 1353 return (0); 1354 } 1355 1356 static int 1357 amrioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct lwp *l) 1358 { 1359 struct amr_softc *amr; 1360 struct amr_user_ioctl *au; 1361 struct amr_ccb *ac; 1362 struct amr_mailbox_ioctl *mbi; 1363 unsigned long au_length; 1364 uint8_t *au_cmd; 1365 int error; 1366 void *dp = NULL, *au_buffer; 1367 1368 amr = device_lookup(&amr_cd, minor(dev)); 1369 1370 /* This should be compatible with the FreeBSD interface */ 1371 1372 switch (cmd) { 1373 case AMR_IO_VERSION: 1374 *(int *)data = AMR_IO_VERSION_NUMBER; 1375 return 0; 1376 case AMR_IO_COMMAND: 1377 if (securelevel >= 2) 1378 return (EPERM); 1379 1380 au = (struct amr_user_ioctl *)data; 1381 au_cmd = au->au_cmd; 1382 au_buffer = au->au_buffer; 1383 au_length = au->au_length; 1384 break; 1385 default: 1386 return ENOTTY; 1387 } 1388 1389 if (au_cmd[0] == AMR_CMD_PASS) { 1390 /* not yet */ 1391 return EOPNOTSUPP; 1392 } 1393 1394 if (au_length <= 0 || au_length > MAXPHYS || au_cmd[0] == 0x06) 1395 return (EINVAL); 1396 1397 /* 1398 * allocate kernel memory for data, doing I/O directly to user 1399 * buffer isn't that easy. 1400 */ 1401 dp = malloc(au_length, M_DEVBUF, M_WAITOK|M_ZERO); 1402 if (dp == NULL) 1403 return ENOMEM; 1404 if ((error = copyin(au_buffer, dp, au_length)) != 0) 1405 goto out; 1406 1407 /* direct command to controller */ 1408 while (amr_ccb_alloc(amr, &ac) != 0) { 1409 error = tsleep(NULL, PRIBIO | PCATCH, "armmbx", hz); 1410 if (error == EINTR) 1411 goto out; 1412 } 1413 1414 mbi = (struct amr_mailbox_ioctl *)&ac->ac_cmd; 1415 mbi->mb_command = au_cmd[0]; 1416 mbi->mb_channel = au_cmd[1]; 1417 mbi->mb_param = au_cmd[2]; 1418 mbi->mb_pad[0] = au_cmd[3]; 1419 mbi->mb_drive = au_cmd[4]; 1420 error = amr_ccb_map(amr, ac, dp, (int)au_length, 1421 AC_XFER_IN | AC_XFER_OUT); 1422 if (error == 0) { 1423 error = amr_ccb_wait(amr, ac); 1424 amr_ccb_unmap(amr, ac); 1425 if (error == 0) 1426 error = copyout(dp, au_buffer, au_length); 1427 1428 } 1429 amr_ccb_free(amr, ac); 1430 out: 1431 free(dp, M_DEVBUF); 1432 return (error); 1433 } 1434
Indexes created Thu Sep 25 06:09:39 GMT 2025