amr.c revision 1.44.2.2
1 /* $NetBSD: amr.c,v 1.44.2.2 2007/04/10 12:07:11 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999,2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 66 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 67 */ 68 69 /* 70 * Driver for AMI RAID controllers. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.44.2.2 2007/04/10 12:07:11 ad Exp $"); 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 #include <sys/proc.h> 82 #include <sys/buf.h> 83 #include <sys/malloc.h> 84 #include <sys/conf.h> 85 #include <sys/kthread.h> 86 #include <sys/kauth.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #include <machine/endian.h> 91 #include <machine/bus.h> 92 93 #include <dev/pci/pcidevs.h> 94 #include <dev/pci/pcivar.h> 95 #include <dev/pci/amrreg.h> 96 #include <dev/pci/amrvar.h> 97 #include <dev/pci/amrio.h> 98 99 #include "locators.h" 100 101 static void amr_attach(struct device *, struct device *, void *); 102 static void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 103 static void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, 104 void *); 105 static int amr_init(struct amr_softc *, const char *, 106 struct pci_attach_args *pa); 107 static int amr_intr(void *); 108 static int amr_match(struct device *, struct cfdata *, void *); 109 static int amr_print(void *, const char *); 110 static void amr_shutdown(void *); 111 static void amr_teardown(struct amr_softc *); 112 static void amr_thread(void *); 113 114 static int amr_quartz_get_work(struct amr_softc *, 115 struct amr_mailbox_resp *); 116 static int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 117 static int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 118 static int amr_std_submit(struct amr_softc *, struct amr_ccb *); 119 120 static dev_type_open(amropen); 121 static dev_type_close(amrclose); 122 static dev_type_ioctl(amrioctl); 123 124 CFATTACH_DECL(amr, sizeof(struct amr_softc), 125 amr_match, amr_attach, NULL, NULL); 126 127 const struct cdevsw amr_cdevsw = { 128 amropen, amrclose, noread, nowrite, amrioctl, 129 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 130 }; 131 132 extern struct cfdriver amr_cd; 133 134 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 135 #define AT_SIG 0x02 /* Check for signature */ 136 137 static struct amr_pci_type { 138 u_short apt_vendor; 139 u_short apt_product; 140 u_short apt_flags; 141 } const amr_pci_type[] = { 142 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 143 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 144 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 145 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 149 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 150 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 151 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 152 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4ESI, AT_QUARTZ }, 153 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_PERC_4SC, AT_QUARTZ }, 154 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 155 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 156 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 157 }; 158 159 static struct amr_typestr { 160 const char *at_str; 161 int at_sig; 162 } const amr_typestr[] = { 163 { "Series 431", AMR_SIG_431 }, 164 { "Series 438", AMR_SIG_438 }, 165 { "Series 466", AMR_SIG_466 }, 166 { "Series 467", AMR_SIG_467 }, 167 { "Series 490", AMR_SIG_490 }, 168 { "Series 762", AMR_SIG_762 }, 169 { "HP NetRAID (T5)", AMR_SIG_T5 }, 170 { "HP NetRAID (T7)", AMR_SIG_T7 }, 171 }; 172 173 static struct { 174 const char *ds_descr; 175 int ds_happy; 176 } const amr_dstate[] = { 177 { "offline", 0 }, 178 { "degraded", 1 }, 179 { "optimal", 1 }, 180 { "online", 1 }, 181 { "failed", 0 }, 182 { "rebuilding", 1 }, 183 { "hotspare", 0 }, 184 }; 185 186 static void *amr_sdh; 187 188 static int amr_max_segs; 189 int amr_max_xfer; 190 191 static inline u_int8_t 192 amr_inb(struct amr_softc *amr, int off) 193 { 194 195 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 196 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 197 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 198 } 199 200 static inline u_int32_t 201 amr_inl(struct amr_softc *amr, int off) 202 { 203 204 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 205 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 206 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 207 } 208 209 static inline void 210 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 211 { 212 213 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 214 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 215 BUS_SPACE_BARRIER_WRITE); 216 } 217 218 static inline void 219 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 220 { 221 222 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 223 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 224 BUS_SPACE_BARRIER_WRITE); 225 } 226 227 /* 228 * Match a supported device. 229 */ 230 static int 231 amr_match(struct device *parent, struct cfdata *match, 232 void *aux) 233 { 234 struct pci_attach_args *pa; 235 pcireg_t s; 236 int i; 237 238 pa = (struct pci_attach_args *)aux; 239 240 /* 241 * Don't match the device if it's operating in I2O mode. In this 242 * case it should be handled by the `iop' driver. 243 */ 244 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 245 return (0); 246 247 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 248 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 249 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 250 break; 251 252 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 253 return (0); 254 255 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 256 return (1); 257 258 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 259 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 260 } 261 262 /* 263 * Attach a supported device. 264 */ 265 static void 266 amr_attach(struct device *parent, struct device *self, void *aux) 267 { 268 struct pci_attach_args *pa; 269 struct amr_attach_args amra; 270 const struct amr_pci_type *apt; 271 struct amr_softc *amr; 272 pci_chipset_tag_t pc; 273 pci_intr_handle_t ih; 274 const char *intrstr; 275 pcireg_t reg; 276 int rseg, i, j, size, rv, memreg, ioreg; 277 struct amr_ccb *ac; 278 int locs[AMRCF_NLOCS]; 279 280 aprint_naive(": RAID controller\n"); 281 282 amr = (struct amr_softc *)self; 283 pa = (struct pci_attach_args *)aux; 284 pc = pa->pa_pc; 285 286 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 287 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 288 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 289 break; 290 apt = amr_pci_type + i; 291 292 memreg = ioreg = 0; 293 for (i = 0x10; i <= 0x14; i += 4) { 294 reg = pci_conf_read(pc, pa->pa_tag, i); 295 switch (PCI_MAPREG_TYPE(reg)) { 296 case PCI_MAPREG_TYPE_MEM: 297 if (PCI_MAPREG_MEM_SIZE(reg) != 0) 298 memreg = i; 299 break; 300 case PCI_MAPREG_TYPE_IO: 301 if (PCI_MAPREG_IO_SIZE(reg) != 0) 302 ioreg = i; 303 break; 304 305 } 306 } 307 308 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 309 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 310 ; 311 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 312 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 313 ; 314 else { 315 aprint_error("can't map control registers\n"); 316 amr_teardown(amr); 317 return; 318 } 319 320 amr->amr_flags |= AMRF_PCI_REGS; 321 amr->amr_dmat = pa->pa_dmat; 322 amr->amr_pc = pa->pa_pc; 323 324 /* Enable the device. */ 325 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 326 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 327 reg | PCI_COMMAND_MASTER_ENABLE); 328 329 /* Map and establish the interrupt. */ 330 if (pci_intr_map(pa, &ih)) { 331 aprint_error("can't map interrupt\n"); 332 amr_teardown(amr); 333 return; 334 } 335 intrstr = pci_intr_string(pc, ih); 336 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); 337 if (amr->amr_ih == NULL) { 338 aprint_error("can't establish interrupt"); 339 if (intrstr != NULL) 340 aprint_normal(" at %s", intrstr); 341 aprint_normal("\n"); 342 amr_teardown(amr); 343 return; 344 } 345 amr->amr_flags |= AMRF_PCI_INTR; 346 347 /* 348 * Allocate space for the mailbox and S/G lists. Some controllers 349 * don't like S/G lists to be located below 0x2000, so we allocate 350 * enough slop to enable us to compensate. 351 * 352 * The standard mailbox structure needs to be aligned on a 16-byte 353 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 354 * size, which precedes the standard mailbox. 355 */ 356 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 357 amr->amr_dmasize = size; 358 359 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, 360 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 361 aprint_error("%s: unable to allocate buffer, rv = %d\n", 362 amr->amr_dv.dv_xname, rv); 363 amr_teardown(amr); 364 return; 365 } 366 amr->amr_flags |= AMRF_DMA_ALLOC; 367 368 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 369 (void **)&amr->amr_mbox, 370 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 371 aprint_error("%s: unable to map buffer, rv = %d\n", 372 amr->amr_dv.dv_xname, rv); 373 amr_teardown(amr); 374 return; 375 } 376 amr->amr_flags |= AMRF_DMA_MAP; 377 378 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 379 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 380 aprint_error("%s: unable to create buffer DMA map, rv = %d\n", 381 amr->amr_dv.dv_xname, rv); 382 amr_teardown(amr); 383 return; 384 } 385 amr->amr_flags |= AMRF_DMA_CREATE; 386 387 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 388 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 389 aprint_error("%s: unable to load buffer DMA map, rv = %d\n", 390 amr->amr_dv.dv_xname, rv); 391 amr_teardown(amr); 392 return; 393 } 394 amr->amr_flags |= AMRF_DMA_LOAD; 395 396 memset(amr->amr_mbox, 0, size); 397 398 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 399 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 400 amr->amr_sgls = (struct amr_sgentry *)((char *)amr->amr_mbox + 401 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 402 403 /* 404 * Allocate and initalise the command control blocks. 405 */ 406 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); 407 amr->amr_ccbs = ac; 408 SLIST_INIT(&amr->amr_ccb_freelist); 409 TAILQ_INIT(&amr->amr_ccb_active); 410 amr->amr_flags |= AMRF_CCBS; 411 412 if (amr_max_xfer == 0) { 413 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); 414 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 415 } 416 417 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 418 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 419 amr_max_segs, amr_max_xfer, 0, 420 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 421 if (rv != 0) 422 break; 423 424 ac->ac_ident = i; 425 amr_ccb_free(amr, ac); 426 } 427 if (i != AMR_MAX_CMDS) { 428 aprint_error("%s: memory exhausted\n", amr->amr_dv.dv_xname); 429 amr_teardown(amr); 430 return; 431 } 432 433 /* 434 * Take care of model-specific tasks. 435 */ 436 if ((apt->apt_flags & AT_QUARTZ) != 0) { 437 amr->amr_submit = amr_quartz_submit; 438 amr->amr_get_work = amr_quartz_get_work; 439 } else { 440 amr->amr_submit = amr_std_submit; 441 amr->amr_get_work = amr_std_get_work; 442 443 /* Notify the controller of the mailbox location. */ 444 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 445 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 446 447 /* Clear outstanding interrupts and enable interrupts. */ 448 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 449 amr_outb(amr, AMR_SREG_TOGL, 450 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 451 } 452 453 /* 454 * Retrieve parameters, and tell the world about us. 455 */ 456 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); 457 amr->amr_flags |= AMRF_ENQBUF; 458 amr->amr_maxqueuecnt = i; 459 aprint_normal(": AMI RAID "); 460 if (amr_init(amr, intrstr, pa) != 0) { 461 amr_teardown(amr); 462 return; 463 } 464 465 /* 466 * Cap the maximum number of outstanding commands. AMI's Linux 467 * driver doesn't trust the controller's reported value, and lockups 468 * have been seen when we do. 469 */ 470 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 471 if (amr->amr_maxqueuecnt > i) 472 amr->amr_maxqueuecnt = i; 473 474 /* Set our `shutdownhook' before we start any device activity. */ 475 if (amr_sdh == NULL) 476 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 477 478 /* Attach sub-devices. */ 479 for (j = 0; j < amr->amr_numdrives; j++) { 480 if (amr->amr_drive[j].al_size == 0) 481 continue; 482 amra.amra_unit = j; 483 484 locs[AMRCF_UNIT] = j; 485 486 amr->amr_drive[j].al_dv = config_found_sm_loc(&amr->amr_dv, 487 "amr", locs, &amra, amr_print, config_stdsubmatch); 488 } 489 490 SIMPLEQ_INIT(&amr->amr_ccb_queue); 491 492 /* XXX This doesn't work for newer boards yet. */ 493 if ((apt->apt_flags & AT_QUARTZ) == 0) { 494 rv = kthread_create(PRI_NONE, false, amr_thread, amr, 495 &amr->amr_thread, "%s", amr->amr_dv.dv_xname); 496 if (rv != 0) 497 aprint_error("%s: unable to create thread (%d)", 498 amr->amr_dv.dv_xname, rv); 499 else 500 amr->amr_flags |= AMRF_THREAD; 501 } 502 } 503 504 /* 505 * Free up resources. 506 */ 507 static void 508 amr_teardown(struct amr_softc *amr) 509 { 510 struct amr_ccb *ac; 511 int fl; 512 513 fl = amr->amr_flags; 514 515 if ((fl & AMRF_THREAD) != 0) { 516 amr->amr_flags |= AMRF_THREAD_EXIT; 517 wakeup(amr_thread); 518 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) 519 tsleep(&amr->amr_flags, PWAIT, "amrexit", 0); 520 } 521 if ((fl & AMRF_CCBS) != 0) { 522 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 523 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 524 } 525 free(amr->amr_ccbs, M_DEVBUF); 526 } 527 if ((fl & AMRF_ENQBUF) != 0) 528 free(amr->amr_enqbuf, M_DEVBUF); 529 if ((fl & AMRF_DMA_LOAD) != 0) 530 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 531 if ((fl & AMRF_DMA_MAP) != 0) 532 bus_dmamem_unmap(amr->amr_dmat, (void *)amr->amr_mbox, 533 amr->amr_dmasize); 534 if ((fl & AMRF_DMA_ALLOC) != 0) 535 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 536 if ((fl & AMRF_DMA_CREATE) != 0) 537 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 538 if ((fl & AMRF_PCI_INTR) != 0) 539 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 540 if ((fl & AMRF_PCI_REGS) != 0) 541 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 542 } 543 544 /* 545 * Print autoconfiguration message for a sub-device. 546 */ 547 static int 548 amr_print(void *aux, const char *pnp) 549 { 550 struct amr_attach_args *amra; 551 552 amra = (struct amr_attach_args *)aux; 553 554 if (pnp != NULL) 555 aprint_normal("block device at %s", pnp); 556 aprint_normal(" unit %d", amra->amra_unit); 557 return (UNCONF); 558 } 559 560 /* 561 * Retrieve operational parameters and describe the controller. 562 */ 563 static int 564 amr_init(struct amr_softc *amr, const char *intrstr, 565 struct pci_attach_args *pa) 566 { 567 struct amr_adapter_info *aa; 568 struct amr_prodinfo *ap; 569 struct amr_enquiry *ae; 570 struct amr_enquiry3 *aex; 571 const char *prodstr; 572 u_int i, sig, ishp; 573 char sbuf[64]; 574 575 /* 576 * Try to get 40LD product info, which tells us what the card is 577 * labelled as. 578 */ 579 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 580 amr->amr_enqbuf); 581 if (ap != NULL) { 582 aprint_normal("<%.80s>\n", ap->ap_product); 583 if (intrstr != NULL) 584 aprint_normal("%s: interrupting at %s\n", 585 amr->amr_dv.dv_xname, intrstr); 586 aprint_normal("%s: firmware %.16s, BIOS %.16s, %dMB RAM\n", 587 amr->amr_dv.dv_xname, ap->ap_firmware, ap->ap_bios, 588 le16toh(ap->ap_memsize)); 589 590 amr->amr_maxqueuecnt = ap->ap_maxio; 591 592 /* 593 * Fetch and record state of logical drives. 594 */ 595 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 596 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 597 if (aex == NULL) { 598 aprint_error("%s ENQUIRY3 failed\n", 599 amr->amr_dv.dv_xname); 600 return (-1); 601 } 602 603 if (aex->ae_numldrives > __arraycount(aex->ae_drivestate)) { 604 aprint_error("%s: Inquiry returned more drives (%d)" 605 " than the array can handle (%zu)\n", 606 amr->amr_dv.dv_xname, aex->ae_numldrives, 607 __arraycount(aex->ae_drivestate)); 608 aex->ae_numldrives = __arraycount(aex->ae_drivestate); 609 } 610 if (aex->ae_numldrives > AMR_MAX_UNITS) { 611 aprint_error( 612 "%s: adjust AMR_MAX_UNITS to %d (currently %d)" 613 "\n", amr->amr_dv.dv_xname, AMR_MAX_UNITS, 614 amr->amr_numdrives); 615 amr->amr_numdrives = AMR_MAX_UNITS; 616 } else 617 amr->amr_numdrives = aex->ae_numldrives; 618 619 for (i = 0; i < amr->amr_numdrives; i++) { 620 amr->amr_drive[i].al_size = 621 le32toh(aex->ae_drivesize[i]); 622 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 623 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 624 } 625 626 return (0); 627 } 628 629 /* 630 * Try 8LD extended ENQUIRY to get the controller signature. Once 631 * found, search for a product description. 632 */ 633 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 634 if (ae != NULL) { 635 i = 0; 636 sig = le32toh(ae->ae_signature); 637 638 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 639 if (amr_typestr[i].at_sig == sig) 640 break; 641 i++; 642 } 643 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 644 snprintf(sbuf, sizeof(sbuf), 645 "unknown ENQUIRY2 sig (0x%08x)", sig); 646 prodstr = sbuf; 647 } else 648 prodstr = amr_typestr[i].at_str; 649 } else { 650 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 651 if (ae == NULL) { 652 aprint_error("%s: unsupported controller\n", 653 amr->amr_dv.dv_xname); 654 return (-1); 655 } 656 657 switch (PCI_PRODUCT(pa->pa_id)) { 658 case PCI_PRODUCT_AMI_MEGARAID: 659 prodstr = "Series 428"; 660 break; 661 case PCI_PRODUCT_AMI_MEGARAID2: 662 prodstr = "Series 434"; 663 break; 664 default: 665 snprintf(sbuf, sizeof(sbuf), "unknown PCI dev (0x%04x)", 666 PCI_PRODUCT(pa->pa_id)); 667 prodstr = sbuf; 668 break; 669 } 670 } 671 672 /* 673 * HP NetRaid controllers have a special encoding of the firmware 674 * and BIOS versions. The AMI version seems to have it as strings 675 * whereas the HP version does it with a leading uppercase character 676 * and two binary numbers. 677 */ 678 aa = &ae->ae_adapter; 679 680 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 681 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 682 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 683 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 684 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 685 /* The AMI 438 is a NetRaid 3si in HP-land. */ 686 prodstr = "HP NetRaid 3si"; 687 } 688 ishp = 1; 689 } else 690 ishp = 0; 691 692 aprint_normal("<%s>\n", prodstr); 693 if (intrstr != NULL) 694 aprint_normal("%s: interrupting at %s\n", amr->amr_dv.dv_xname, 695 intrstr); 696 697 if (ishp) 698 aprint_normal("%s: firmware <%c.%02d.%02d>, BIOS <%c.%02d.%02d>" 699 ", %dMB RAM\n", amr->amr_dv.dv_xname, aa->aa_firmware[2], 700 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 701 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 702 else 703 aprint_normal("%s: firmware <%.4s>, BIOS <%.4s>, %dMB RAM\n", 704 amr->amr_dv.dv_xname, aa->aa_firmware, aa->aa_bios, 705 aa->aa_memorysize); 706 707 amr->amr_maxqueuecnt = aa->aa_maxio; 708 709 /* 710 * Record state of logical drives. 711 */ 712 if (ae->ae_ldrv.al_numdrives > __arraycount(ae->ae_ldrv.al_size)) { 713 aprint_error("%s: Inquiry returned more drives (%d)" 714 " than the array can handle (%zu)\n", 715 amr->amr_dv.dv_xname, ae->ae_ldrv.al_numdrives, 716 __arraycount(ae->ae_ldrv.al_size)); 717 ae->ae_ldrv.al_numdrives = __arraycount(ae->ae_ldrv.al_size); 718 } 719 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 720 aprint_error("%s: adjust AMR_MAX_UNITS to %d (currently %d)\n", 721 amr->amr_dv.dv_xname, ae->ae_ldrv.al_numdrives, 722 AMR_MAX_UNITS); 723 amr->amr_numdrives = AMR_MAX_UNITS; 724 } else 725 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 726 727 for (i = 0; i < amr->amr_numdrives; i++) { 728 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 729 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 730 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 731 } 732 733 return (0); 734 } 735 736 /* 737 * Flush the internal cache on each configured controller. Called at 738 * shutdown time. 739 */ 740 static void 741 amr_shutdown(void *cookie) 742 { 743 extern struct cfdriver amr_cd; 744 struct amr_softc *amr; 745 struct amr_ccb *ac; 746 int i, rv, s; 747 748 for (i = 0; i < amr_cd.cd_ndevs; i++) { 749 if ((amr = device_lookup(&amr_cd, i)) == NULL) 750 continue; 751 752 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 753 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 754 s = splbio(); 755 rv = amr_ccb_poll(amr, ac, 30000); 756 splx(s); 757 amr_ccb_free(amr, ac); 758 } 759 if (rv != 0) 760 printf("%s: unable to flush cache (%d)\n", 761 amr->amr_dv.dv_xname, rv); 762 } 763 } 764 765 /* 766 * Interrupt service routine. 767 */ 768 static int 769 amr_intr(void *cookie) 770 { 771 struct amr_softc *amr; 772 struct amr_ccb *ac; 773 struct amr_mailbox_resp mbox; 774 u_int i, forus, idx; 775 776 amr = cookie; 777 forus = 0; 778 779 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 780 /* Iterate over completed commands in this result. */ 781 for (i = 0; i < mbox.mb_nstatus; i++) { 782 idx = mbox.mb_completed[i] - 1; 783 ac = amr->amr_ccbs + idx; 784 785 if (idx >= amr->amr_maxqueuecnt) { 786 printf("%s: bad status (bogus ID: %u=%u)\n", 787 amr->amr_dv.dv_xname, i, idx); 788 continue; 789 } 790 791 if ((ac->ac_flags & AC_ACTIVE) == 0) { 792 printf("%s: bad status (not active; 0x04%x)\n", 793 amr->amr_dv.dv_xname, ac->ac_flags); 794 continue; 795 } 796 797 ac->ac_status = mbox.mb_status; 798 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 799 AC_COMPLETE; 800 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 801 802 if ((ac->ac_flags & AC_MOAN) != 0) 803 printf("%s: ccb %d completed\n", 804 amr->amr_dv.dv_xname, ac->ac_ident); 805 806 /* Pass notification to upper layers. */ 807 if (ac->ac_handler != NULL) 808 (*ac->ac_handler)(ac); 809 else 810 wakeup(ac); 811 } 812 forus = 1; 813 } 814 815 if (forus) 816 amr_ccb_enqueue(amr, NULL); 817 818 return (forus); 819 } 820 821 /* 822 * Watchdog thread. 823 */ 824 static void 825 amr_thread(void *cookie) 826 { 827 struct amr_softc *amr; 828 struct amr_ccb *ac; 829 struct amr_logdrive *al; 830 struct amr_enquiry *ae; 831 int rv, i, s; 832 833 amr = cookie; 834 ae = amr->amr_enqbuf; 835 836 for (;;) { 837 tsleep(amr_thread, PWAIT, "amrwdog", AMR_WDOG_TICKS); 838 839 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 840 amr->amr_flags ^= AMRF_THREAD_EXIT; 841 wakeup(&amr->amr_flags); 842 kthread_exit(0); 843 } 844 845 s = splbio(); 846 amr_intr(cookie); 847 ac = TAILQ_FIRST(&amr->amr_ccb_active); 848 while (ac != NULL) { 849 if (ac->ac_start_time + AMR_TIMEOUT > time_uptime) 850 break; 851 if ((ac->ac_flags & AC_MOAN) == 0) { 852 printf("%s: ccb %d timed out; mailbox:\n", 853 amr->amr_dv.dv_xname, ac->ac_ident); 854 amr_ccb_dump(amr, ac); 855 ac->ac_flags |= AC_MOAN; 856 } 857 ac = TAILQ_NEXT(ac, ac_chain.tailq); 858 } 859 splx(s); 860 861 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 862 printf("%s: ccb_alloc failed (%d)\n", 863 amr->amr_dv.dv_xname, rv); 864 continue; 865 } 866 867 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 868 869 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 870 AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 871 if (rv != 0) { 872 printf("%s: ccb_map failed (%d)\n", 873 amr->amr_dv.dv_xname, rv); 874 amr_ccb_free(amr, ac); 875 continue; 876 } 877 878 rv = amr_ccb_wait(amr, ac); 879 amr_ccb_unmap(amr, ac); 880 if (rv != 0) { 881 printf("%s: enquiry failed (st=%d)\n", 882 amr->amr_dv.dv_xname, ac->ac_status); 883 continue; 884 } 885 amr_ccb_free(amr, ac); 886 887 al = amr->amr_drive; 888 for (i = 0; i < __arraycount(ae->ae_ldrv.al_state); i++, al++) { 889 if (al->al_dv == NULL) 890 continue; 891 if (al->al_state == ae->ae_ldrv.al_state[i]) 892 continue; 893 894 printf("%s: state changed: %s -> %s\n", 895 al->al_dv->dv_xname, 896 amr_drive_state(al->al_state, NULL), 897 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 898 899 al->al_state = ae->ae_ldrv.al_state[i]; 900 } 901 } 902 } 903 904 /* 905 * Return a text description of a logical drive's current state. 906 */ 907 const char * 908 amr_drive_state(int state, int *happy) 909 { 910 const char *str; 911 912 state = AMR_DRV_CURSTATE(state); 913 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 914 if (happy) 915 *happy = 1; 916 str = "status unknown"; 917 } else { 918 if (happy) 919 *happy = amr_dstate[state].ds_happy; 920 str = amr_dstate[state].ds_descr; 921 } 922 923 return (str); 924 } 925 926 /* 927 * Run a generic enquiry-style command. 928 */ 929 static void * 930 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 931 u_int8_t cmdqual, void *sbuf) 932 { 933 struct amr_ccb *ac; 934 u_int8_t *mb; 935 int rv; 936 937 if (amr_ccb_alloc(amr, &ac) != 0) 938 return (NULL); 939 940 /* Build the command proper. */ 941 mb = (u_int8_t *)&ac->ac_cmd; 942 mb[0] = cmd; 943 mb[2] = cmdsub; 944 mb[3] = cmdqual; 945 946 rv = amr_ccb_map(amr, ac, sbuf, AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 947 if (rv == 0) { 948 rv = amr_ccb_poll(amr, ac, 2000); 949 amr_ccb_unmap(amr, ac); 950 } 951 amr_ccb_free(amr, ac); 952 953 return (rv ? NULL : sbuf); 954 } 955 956 /* 957 * Allocate and initialise a CCB. 958 */ 959 int 960 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 961 { 962 int s; 963 964 s = splbio(); 965 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 966 splx(s); 967 return (EAGAIN); 968 } 969 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 970 splx(s); 971 972 return (0); 973 } 974 975 /* 976 * Free a CCB. 977 */ 978 void 979 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 980 { 981 int s; 982 983 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 984 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 985 ac->ac_cmd.mb_busy = 1; 986 ac->ac_handler = NULL; 987 ac->ac_flags = 0; 988 989 s = splbio(); 990 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 991 splx(s); 992 } 993 994 /* 995 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 996 * the order that they were enqueued and try to submit their command blocks 997 * to the controller for execution. 998 */ 999 void 1000 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 1001 { 1002 int s; 1003 1004 s = splbio(); 1005 1006 if (ac != NULL) 1007 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 1008 1009 while ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1010 if ((*amr->amr_submit)(amr, ac) != 0) 1011 break; 1012 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, ac_chain.simpleq); 1013 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1014 } 1015 1016 splx(s); 1017 } 1018 1019 /* 1020 * Map the specified CCB's data buffer onto the bus, and fill the 1021 * scatter-gather list. 1022 */ 1023 int 1024 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1025 int tflag) 1026 { 1027 struct amr_sgentry *sge; 1028 struct amr_mailbox_cmd *mb; 1029 int nsegs, i, rv, sgloff; 1030 bus_dmamap_t xfer; 1031 int dmaflag = 0; 1032 1033 xfer = ac->ac_xfer_map; 1034 1035 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1036 BUS_DMA_NOWAIT); 1037 if (rv != 0) 1038 return (rv); 1039 1040 mb = &ac->ac_cmd; 1041 ac->ac_xfer_size = size; 1042 ac->ac_flags |= (tflag & (AC_XFER_OUT | AC_XFER_IN)); 1043 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1044 1045 if (tflag & AC_XFER_OUT) 1046 dmaflag |= BUS_DMASYNC_PREWRITE; 1047 if (tflag & AC_XFER_IN) 1048 dmaflag |= BUS_DMASYNC_PREREAD; 1049 1050 /* We don't need to use a scatter/gather list for just 1 segment. */ 1051 nsegs = xfer->dm_nsegs; 1052 if (nsegs == 1) { 1053 mb->mb_nsgelem = 0; 1054 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1055 ac->ac_flags |= AC_NOSGL; 1056 } else { 1057 mb->mb_nsgelem = nsegs; 1058 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1059 1060 sge = (struct amr_sgentry *)((char *)amr->amr_sgls + sgloff); 1061 for (i = 0; i < nsegs; i++, sge++) { 1062 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1063 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1064 } 1065 } 1066 1067 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, dmaflag); 1068 1069 if ((ac->ac_flags & AC_NOSGL) == 0) 1070 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1071 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1072 1073 return (0); 1074 } 1075 1076 /* 1077 * Unmap the specified CCB's data buffer. 1078 */ 1079 void 1080 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1081 { 1082 int dmaflag = 0; 1083 1084 if (ac->ac_flags & AC_XFER_IN) 1085 dmaflag |= BUS_DMASYNC_POSTREAD; 1086 if (ac->ac_flags & AC_XFER_OUT) 1087 dmaflag |= BUS_DMASYNC_POSTWRITE; 1088 1089 if ((ac->ac_flags & AC_NOSGL) == 0) 1090 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1091 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1092 BUS_DMASYNC_POSTWRITE); 1093 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1094 dmaflag); 1095 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1096 } 1097 1098 /* 1099 * Submit a command to the controller and poll on completion. Return 1100 * non-zero on timeout or error. Must be called with interrupts blocked. 1101 */ 1102 int 1103 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1104 { 1105 int rv; 1106 1107 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) 1108 return (rv); 1109 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1110 1111 for (timo *= 10; timo != 0; timo--) { 1112 amr_intr(amr); 1113 if ((ac->ac_flags & AC_COMPLETE) != 0) 1114 break; 1115 DELAY(100); 1116 } 1117 1118 return (timo == 0 || ac->ac_status != 0 ? EIO : 0); 1119 } 1120 1121 /* 1122 * Submit a command to the controller and sleep on completion. Return 1123 * non-zero on error. 1124 */ 1125 int 1126 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1127 { 1128 int s; 1129 1130 s = splbio(); 1131 amr_ccb_enqueue(amr, ac); 1132 tsleep(ac, PRIBIO, "amrcmd", 0); 1133 splx(s); 1134 1135 return (ac->ac_status != 0 ? EIO : 0); 1136 } 1137 1138 #if 0 1139 /* 1140 * Wait for the mailbox to become available. 1141 */ 1142 static int 1143 amr_mbox_wait(struct amr_softc *amr) 1144 { 1145 int timo; 1146 1147 for (timo = 10000; timo != 0; timo--) { 1148 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1149 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1150 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1151 break; 1152 DELAY(100); 1153 } 1154 1155 if (timo == 0) 1156 printf("%s: controller wedged\n", amr->amr_dv.dv_xname); 1157 1158 return (timo != 0 ? 0 : EAGAIN); 1159 } 1160 #endif 1161 1162 /* 1163 * Tell the controller that the mailbox contains a valid command. Must be 1164 * called with interrupts blocked. 1165 */ 1166 static int 1167 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1168 { 1169 u_int32_t v; 1170 1171 amr->amr_mbox->mb_poll = 0; 1172 amr->amr_mbox->mb_ack = 0; 1173 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1174 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1175 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1176 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1177 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1178 return (EAGAIN); 1179 1180 v = amr_inl(amr, AMR_QREG_IDB); 1181 if ((v & AMR_QIDB_SUBMIT) != 0) { 1182 amr->amr_mbox->mb_cmd.mb_busy = 0; 1183 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1184 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1185 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1186 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1187 return (EAGAIN); 1188 } 1189 1190 amr->amr_mbox->mb_segment = 0; 1191 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1192 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1193 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1194 1195 ac->ac_start_time = time_uptime; 1196 ac->ac_flags |= AC_ACTIVE; 1197 amr_outl(amr, AMR_QREG_IDB, 1198 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1199 return (0); 1200 } 1201 1202 static int 1203 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1204 { 1205 1206 amr->amr_mbox->mb_poll = 0; 1207 amr->amr_mbox->mb_ack = 0; 1208 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1209 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1210 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1211 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1212 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1213 return (EAGAIN); 1214 1215 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1216 amr->amr_mbox->mb_cmd.mb_busy = 0; 1217 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1218 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1219 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1220 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1221 return (EAGAIN); 1222 } 1223 1224 amr->amr_mbox->mb_segment = 0; 1225 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1226 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1227 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1228 1229 ac->ac_start_time = time_uptime; 1230 ac->ac_flags |= AC_ACTIVE; 1231 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1232 return (0); 1233 } 1234 1235 /* 1236 * Claim any work that the controller has completed; acknowledge completion, 1237 * save details of the completion in (mbsave). Must be called with 1238 * interrupts blocked. 1239 */ 1240 static int 1241 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1242 { 1243 1244 /* Work waiting for us? */ 1245 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1246 return (-1); 1247 1248 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1249 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1250 1251 /* Save the mailbox, which contains a list of completed commands. */ 1252 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1253 1254 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1255 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1256 1257 /* Ack the interrupt and mailbox transfer. */ 1258 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1259 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1260 1261 /* 1262 * This waits for the controller to notice that we've taken the 1263 * command from it. It's very inefficient, and we shouldn't do it, 1264 * but if we remove this code, we stop completing commands under 1265 * load. 1266 * 1267 * Peter J says we shouldn't do this. The documentation says we 1268 * should. Who is right? 1269 */ 1270 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1271 DELAY(10); 1272 1273 return (0); 1274 } 1275 1276 static int 1277 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1278 { 1279 u_int8_t istat; 1280 1281 /* Check for valid interrupt status. */ 1282 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1283 return (-1); 1284 1285 /* Ack the interrupt. */ 1286 amr_outb(amr, AMR_SREG_INTR, istat); 1287 1288 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1289 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1290 1291 /* Save mailbox, which contains a list of completed commands. */ 1292 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1293 1294 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1295 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1296 1297 /* Ack mailbox transfer. */ 1298 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1299 1300 return (0); 1301 } 1302 1303 static void 1304 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1305 { 1306 int i; 1307 1308 printf("%s: ", amr->amr_dv.dv_xname); 1309 for (i = 0; i < 4; i++) 1310 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1311 printf("\n"); 1312 } 1313 1314 static int 1315 amropen(dev_t dev, int flag, int mode, struct lwp *l) 1316 { 1317 struct amr_softc *amr; 1318 1319 if ((amr = device_lookup(&amr_cd, minor(dev))) == NULL) 1320 return (ENXIO); 1321 if ((amr->amr_flags & AMRF_OPEN) != 0) 1322 return (EBUSY); 1323 1324 amr->amr_flags |= AMRF_OPEN; 1325 return (0); 1326 } 1327 1328 static int 1329 amrclose(dev_t dev, int flag, int mode, struct lwp *l) 1330 { 1331 struct amr_softc *amr; 1332 1333 amr = device_lookup(&amr_cd, minor(dev)); 1334 amr->amr_flags &= ~AMRF_OPEN; 1335 return (0); 1336 } 1337 1338 static int 1339 amrioctl(dev_t dev, u_long cmd, void *data, int flag, 1340 struct lwp *l) 1341 { 1342 struct amr_softc *amr; 1343 struct amr_user_ioctl *au; 1344 struct amr_ccb *ac; 1345 struct amr_mailbox_ioctl *mbi; 1346 unsigned long au_length; 1347 uint8_t *au_cmd; 1348 int error; 1349 void *dp = NULL, *au_buffer; 1350 1351 amr = device_lookup(&amr_cd, minor(dev)); 1352 1353 /* This should be compatible with the FreeBSD interface */ 1354 1355 switch (cmd) { 1356 case AMR_IO_VERSION: 1357 *(int *)data = AMR_IO_VERSION_NUMBER; 1358 return 0; 1359 case AMR_IO_COMMAND: 1360 error = kauth_authorize_device_passthru(l->l_cred, dev, 1361 KAUTH_REQ_DEVICE_RAWIO_PASSTHRU_ALL, data); 1362 if (error) 1363 return (error); 1364 1365 au = (struct amr_user_ioctl *)data; 1366 au_cmd = au->au_cmd; 1367 au_buffer = au->au_buffer; 1368 au_length = au->au_length; 1369 break; 1370 default: 1371 return ENOTTY; 1372 } 1373 1374 if (au_cmd[0] == AMR_CMD_PASS) { 1375 /* not yet */ 1376 return EOPNOTSUPP; 1377 } 1378 1379 if (au_length <= 0 || au_length > MAXPHYS || au_cmd[0] == 0x06) 1380 return (EINVAL); 1381 1382 /* 1383 * allocate kernel memory for data, doing I/O directly to user 1384 * buffer isn't that easy. 1385 */ 1386 dp = malloc(au_length, M_DEVBUF, M_WAITOK|M_ZERO); 1387 if (dp == NULL) 1388 return ENOMEM; 1389 if ((error = copyin(au_buffer, dp, au_length)) != 0) 1390 goto out; 1391 1392 /* direct command to controller */ 1393 while (amr_ccb_alloc(amr, &ac) != 0) { 1394 error = tsleep(NULL, PRIBIO | PCATCH, "armmbx", hz); 1395 if (error == EINTR) 1396 goto out; 1397 } 1398 1399 mbi = (struct amr_mailbox_ioctl *)&ac->ac_cmd; 1400 mbi->mb_command = au_cmd[0]; 1401 mbi->mb_channel = au_cmd[1]; 1402 mbi->mb_param = au_cmd[2]; 1403 mbi->mb_pad[0] = au_cmd[3]; 1404 mbi->mb_drive = au_cmd[4]; 1405 error = amr_ccb_map(amr, ac, dp, (int)au_length, 1406 AC_XFER_IN | AC_XFER_OUT); 1407 if (error == 0) { 1408 error = amr_ccb_wait(amr, ac); 1409 amr_ccb_unmap(amr, ac); 1410 if (error == 0) 1411 error = copyout(dp, au_buffer, au_length); 1412 1413 } 1414 amr_ccb_free(amr, ac); 1415 out: 1416 free(dp, M_DEVBUF); 1417 return (error); 1418 } 1419
Indexes created Thu Oct 02 14:10:14 GMT 2025