amr.c revision 1.46.16.1
1 /* $NetBSD: amr.c,v 1.46.16.1 2008/04/05 23:33:22 mjf Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999,2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 66 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 67 */ 68 69 /* 70 * Driver for AMI RAID controllers. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.46.16.1 2008/04/05 23:33:22 mjf Exp $"); 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 #include <sys/proc.h> 82 #include <sys/buf.h> 83 #include <sys/malloc.h> 84 #include <sys/conf.h> 85 #include <sys/kthread.h> 86 #include <sys/kauth.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #include <machine/endian.h> 91 #include <sys/bus.h> 92 93 #include <dev/pci/pcidevs.h> 94 #include <dev/pci/pcivar.h> 95 #include <dev/pci/amrreg.h> 96 #include <dev/pci/amrvar.h> 97 #include <dev/pci/amrio.h> 98 99 #include "locators.h" 100 101 static void amr_attach(struct device *, struct device *, void *); 102 static void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 103 static void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, 104 void *); 105 static int amr_init(struct amr_softc *, const char *, 106 struct pci_attach_args *pa); 107 static int amr_intr(void *); 108 static int amr_match(struct device *, struct cfdata *, void *); 109 static int amr_print(void *, const char *); 110 static void amr_shutdown(void *); 111 static void amr_teardown(struct amr_softc *); 112 static void amr_thread(void *); 113 114 static int amr_quartz_get_work(struct amr_softc *, 115 struct amr_mailbox_resp *); 116 static int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 117 static int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 118 static int amr_std_submit(struct amr_softc *, struct amr_ccb *); 119 120 static dev_type_open(amropen); 121 static dev_type_close(amrclose); 122 static dev_type_ioctl(amrioctl); 123 124 CFATTACH_DECL(amr, sizeof(struct amr_softc), 125 amr_match, amr_attach, NULL, NULL); 126 127 const struct cdevsw amr_cdevsw = { 128 amropen, amrclose, noread, nowrite, amrioctl, 129 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 130 }; 131 132 extern struct cfdriver amr_cd; 133 134 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 135 #define AT_SIG 0x02 /* Check for signature */ 136 137 static struct amr_pci_type { 138 u_short apt_vendor; 139 u_short apt_product; 140 u_short apt_flags; 141 } const amr_pci_type[] = { 142 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 143 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 144 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 145 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 149 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 150 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 151 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 152 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4ESI, AT_QUARTZ }, 153 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_PERC_4SC, AT_QUARTZ }, 154 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 155 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 156 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 157 }; 158 159 static struct amr_typestr { 160 const char *at_str; 161 int at_sig; 162 } const amr_typestr[] = { 163 { "Series 431", AMR_SIG_431 }, 164 { "Series 438", AMR_SIG_438 }, 165 { "Series 466", AMR_SIG_466 }, 166 { "Series 467", AMR_SIG_467 }, 167 { "Series 490", AMR_SIG_490 }, 168 { "Series 762", AMR_SIG_762 }, 169 { "HP NetRAID (T5)", AMR_SIG_T5 }, 170 { "HP NetRAID (T7)", AMR_SIG_T7 }, 171 }; 172 173 static struct { 174 const char *ds_descr; 175 int ds_happy; 176 } const amr_dstate[] = { 177 { "offline", 0 }, 178 { "degraded", 1 }, 179 { "optimal", 1 }, 180 { "online", 1 }, 181 { "failed", 0 }, 182 { "rebuilding", 1 }, 183 { "hotspare", 0 }, 184 }; 185 186 static void *amr_sdh; 187 188 static int amr_max_segs; 189 int amr_max_xfer; 190 191 static inline u_int8_t 192 amr_inb(struct amr_softc *amr, int off) 193 { 194 195 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 196 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 197 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 198 } 199 200 static inline u_int32_t 201 amr_inl(struct amr_softc *amr, int off) 202 { 203 204 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 205 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 206 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 207 } 208 209 static inline void 210 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 211 { 212 213 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 214 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 215 BUS_SPACE_BARRIER_WRITE); 216 } 217 218 static inline void 219 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 220 { 221 222 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 223 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 224 BUS_SPACE_BARRIER_WRITE); 225 } 226 227 /* 228 * Match a supported device. 229 */ 230 static int 231 amr_match(struct device *parent, struct cfdata *match, 232 void *aux) 233 { 234 struct pci_attach_args *pa; 235 pcireg_t s; 236 int i; 237 238 pa = (struct pci_attach_args *)aux; 239 240 /* 241 * Don't match the device if it's operating in I2O mode. In this 242 * case it should be handled by the `iop' driver. 243 */ 244 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 245 return (0); 246 247 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 248 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 249 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 250 break; 251 252 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 253 return (0); 254 255 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 256 return (1); 257 258 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 259 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 260 } 261 262 /* 263 * Attach a supported device. 264 */ 265 static void 266 amr_attach(struct device *parent, struct device *self, void *aux) 267 { 268 struct pci_attach_args *pa; 269 struct amr_attach_args amra; 270 const struct amr_pci_type *apt; 271 struct amr_softc *amr; 272 pci_chipset_tag_t pc; 273 pci_intr_handle_t ih; 274 const char *intrstr; 275 pcireg_t reg; 276 int rseg, i, j, size, rv, memreg, ioreg; 277 struct amr_ccb *ac; 278 int locs[AMRCF_NLOCS]; 279 int unit, major; 280 281 aprint_naive(": RAID controller\n"); 282 283 amr = (struct amr_softc *)self; 284 pa = (struct pci_attach_args *)aux; 285 pc = pa->pa_pc; 286 287 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 288 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 289 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 290 break; 291 apt = amr_pci_type + i; 292 293 memreg = ioreg = 0; 294 for (i = 0x10; i <= 0x14; i += 4) { 295 reg = pci_conf_read(pc, pa->pa_tag, i); 296 switch (PCI_MAPREG_TYPE(reg)) { 297 case PCI_MAPREG_TYPE_MEM: 298 if (PCI_MAPREG_MEM_SIZE(reg) != 0) 299 memreg = i; 300 break; 301 case PCI_MAPREG_TYPE_IO: 302 if (PCI_MAPREG_IO_SIZE(reg) != 0) 303 ioreg = i; 304 break; 305 306 } 307 } 308 309 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 310 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 311 ; 312 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 313 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 314 ; 315 else { 316 aprint_error("can't map control registers\n"); 317 amr_teardown(amr); 318 return; 319 } 320 321 amr->amr_flags |= AMRF_PCI_REGS; 322 amr->amr_dmat = pa->pa_dmat; 323 amr->amr_pc = pa->pa_pc; 324 325 /* Enable the device. */ 326 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 327 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 328 reg | PCI_COMMAND_MASTER_ENABLE); 329 330 /* Map and establish the interrupt. */ 331 if (pci_intr_map(pa, &ih)) { 332 aprint_error("can't map interrupt\n"); 333 amr_teardown(amr); 334 return; 335 } 336 intrstr = pci_intr_string(pc, ih); 337 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); 338 if (amr->amr_ih == NULL) { 339 aprint_error("can't establish interrupt"); 340 if (intrstr != NULL) 341 aprint_normal(" at %s", intrstr); 342 aprint_normal("\n"); 343 amr_teardown(amr); 344 return; 345 } 346 amr->amr_flags |= AMRF_PCI_INTR; 347 348 /* 349 * Allocate space for the mailbox and S/G lists. Some controllers 350 * don't like S/G lists to be located below 0x2000, so we allocate 351 * enough slop to enable us to compensate. 352 * 353 * The standard mailbox structure needs to be aligned on a 16-byte 354 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 355 * size, which precedes the standard mailbox. 356 */ 357 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 358 amr->amr_dmasize = size; 359 360 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, 361 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 362 aprint_error("%s: unable to allocate buffer, rv = %d\n", 363 amr->amr_dv.dv_xname, rv); 364 amr_teardown(amr); 365 return; 366 } 367 amr->amr_flags |= AMRF_DMA_ALLOC; 368 369 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 370 (void **)&amr->amr_mbox, 371 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 372 aprint_error("%s: unable to map buffer, rv = %d\n", 373 amr->amr_dv.dv_xname, rv); 374 amr_teardown(amr); 375 return; 376 } 377 amr->amr_flags |= AMRF_DMA_MAP; 378 379 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 380 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 381 aprint_error("%s: unable to create buffer DMA map, rv = %d\n", 382 amr->amr_dv.dv_xname, rv); 383 amr_teardown(amr); 384 return; 385 } 386 amr->amr_flags |= AMRF_DMA_CREATE; 387 388 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 389 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 390 aprint_error("%s: unable to load buffer DMA map, rv = %d\n", 391 amr->amr_dv.dv_xname, rv); 392 amr_teardown(amr); 393 return; 394 } 395 amr->amr_flags |= AMRF_DMA_LOAD; 396 397 memset(amr->amr_mbox, 0, size); 398 399 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 400 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 401 amr->amr_sgls = (struct amr_sgentry *)((char *)amr->amr_mbox + 402 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 403 404 /* 405 * Allocate and initalise the command control blocks. 406 */ 407 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); 408 amr->amr_ccbs = ac; 409 SLIST_INIT(&amr->amr_ccb_freelist); 410 TAILQ_INIT(&amr->amr_ccb_active); 411 amr->amr_flags |= AMRF_CCBS; 412 413 if (amr_max_xfer == 0) { 414 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); 415 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 416 } 417 418 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 419 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 420 amr_max_segs, amr_max_xfer, 0, 421 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 422 if (rv != 0) 423 break; 424 425 ac->ac_ident = i; 426 amr_ccb_free(amr, ac); 427 } 428 if (i != AMR_MAX_CMDS) { 429 aprint_error("%s: memory exhausted\n", amr->amr_dv.dv_xname); 430 amr_teardown(amr); 431 return; 432 } 433 434 /* 435 * Take care of model-specific tasks. 436 */ 437 if ((apt->apt_flags & AT_QUARTZ) != 0) { 438 amr->amr_submit = amr_quartz_submit; 439 amr->amr_get_work = amr_quartz_get_work; 440 } else { 441 amr->amr_submit = amr_std_submit; 442 amr->amr_get_work = amr_std_get_work; 443 444 /* Notify the controller of the mailbox location. */ 445 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 446 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 447 448 /* Clear outstanding interrupts and enable interrupts. */ 449 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 450 amr_outb(amr, AMR_SREG_TOGL, 451 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 452 } 453 454 /* 455 * Retrieve parameters, and tell the world about us. 456 */ 457 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); 458 amr->amr_flags |= AMRF_ENQBUF; 459 amr->amr_maxqueuecnt = i; 460 aprint_normal(": AMI RAID "); 461 if (amr_init(amr, intrstr, pa) != 0) { 462 amr_teardown(amr); 463 return; 464 } 465 466 /* 467 * Cap the maximum number of outstanding commands. AMI's Linux 468 * driver doesn't trust the controller's reported value, and lockups 469 * have been seen when we do. 470 */ 471 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 472 if (amr->amr_maxqueuecnt > i) 473 amr->amr_maxqueuecnt = i; 474 475 /* Set our `shutdownhook' before we start any device activity. */ 476 if (amr_sdh == NULL) 477 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 478 479 /* Attach sub-devices. */ 480 for (j = 0; j < amr->amr_numdrives; j++) { 481 if (amr->amr_drive[j].al_size == 0) 482 continue; 483 amra.amra_unit = j; 484 485 locs[AMRCF_UNIT] = j; 486 487 amr->amr_drive[j].al_dv = config_found_sm_loc(&amr->amr_dv, 488 "amr", locs, &amra, amr_print, config_stdsubmatch); 489 } 490 491 SIMPLEQ_INIT(&amr->amr_ccb_queue); 492 493 /* XXX This doesn't work for newer boards yet. */ 494 if ((apt->apt_flags & AT_QUARTZ) == 0) { 495 rv = kthread_create(PRI_NONE, 0, NULL, amr_thread, amr, 496 &amr->amr_thread, "%s", amr->amr_dv.dv_xname); 497 if (rv != 0) 498 aprint_error("%s: unable to create thread (%d)", 499 amr->amr_dv.dv_xname, rv); 500 else 501 amr->amr_flags |= AMRF_THREAD; 502 } 503 504 major = cdevsw_lookup_major(&amr_cdevsw); 505 unit = device_unit(self); 506 device_register_name(makedev(major, unit), self, true, 507 DEV_DISK, device_xname(self)); 508 } 509 510 /* 511 * Free up resources. 512 */ 513 static void 514 amr_teardown(struct amr_softc *amr) 515 { 516 struct amr_ccb *ac; 517 int fl; 518 519 fl = amr->amr_flags; 520 521 if ((fl & AMRF_THREAD) != 0) { 522 amr->amr_flags |= AMRF_THREAD_EXIT; 523 wakeup(amr_thread); 524 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) 525 tsleep(&amr->amr_flags, PWAIT, "amrexit", 0); 526 } 527 if ((fl & AMRF_CCBS) != 0) { 528 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 529 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 530 } 531 free(amr->amr_ccbs, M_DEVBUF); 532 } 533 if ((fl & AMRF_ENQBUF) != 0) 534 free(amr->amr_enqbuf, M_DEVBUF); 535 if ((fl & AMRF_DMA_LOAD) != 0) 536 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 537 if ((fl & AMRF_DMA_MAP) != 0) 538 bus_dmamem_unmap(amr->amr_dmat, (void *)amr->amr_mbox, 539 amr->amr_dmasize); 540 if ((fl & AMRF_DMA_ALLOC) != 0) 541 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 542 if ((fl & AMRF_DMA_CREATE) != 0) 543 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 544 if ((fl & AMRF_PCI_INTR) != 0) 545 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 546 if ((fl & AMRF_PCI_REGS) != 0) 547 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 548 } 549 550 /* 551 * Print autoconfiguration message for a sub-device. 552 */ 553 static int 554 amr_print(void *aux, const char *pnp) 555 { 556 struct amr_attach_args *amra; 557 558 amra = (struct amr_attach_args *)aux; 559 560 if (pnp != NULL) 561 aprint_normal("block device at %s", pnp); 562 aprint_normal(" unit %d", amra->amra_unit); 563 return (UNCONF); 564 } 565 566 /* 567 * Retrieve operational parameters and describe the controller. 568 */ 569 static int 570 amr_init(struct amr_softc *amr, const char *intrstr, 571 struct pci_attach_args *pa) 572 { 573 struct amr_adapter_info *aa; 574 struct amr_prodinfo *ap; 575 struct amr_enquiry *ae; 576 struct amr_enquiry3 *aex; 577 const char *prodstr; 578 u_int i, sig, ishp; 579 char sbuf[64]; 580 581 /* 582 * Try to get 40LD product info, which tells us what the card is 583 * labelled as. 584 */ 585 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 586 amr->amr_enqbuf); 587 if (ap != NULL) { 588 aprint_normal("<%.80s>\n", ap->ap_product); 589 if (intrstr != NULL) 590 aprint_normal("%s: interrupting at %s\n", 591 amr->amr_dv.dv_xname, intrstr); 592 aprint_normal("%s: firmware %.16s, BIOS %.16s, %dMB RAM\n", 593 amr->amr_dv.dv_xname, ap->ap_firmware, ap->ap_bios, 594 le16toh(ap->ap_memsize)); 595 596 amr->amr_maxqueuecnt = ap->ap_maxio; 597 598 /* 599 * Fetch and record state of logical drives. 600 */ 601 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 602 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 603 if (aex == NULL) { 604 aprint_error("%s ENQUIRY3 failed\n", 605 amr->amr_dv.dv_xname); 606 return (-1); 607 } 608 609 if (aex->ae_numldrives > __arraycount(aex->ae_drivestate)) { 610 aprint_error("%s: Inquiry returned more drives (%d)" 611 " than the array can handle (%zu)\n", 612 amr->amr_dv.dv_xname, aex->ae_numldrives, 613 __arraycount(aex->ae_drivestate)); 614 aex->ae_numldrives = __arraycount(aex->ae_drivestate); 615 } 616 if (aex->ae_numldrives > AMR_MAX_UNITS) { 617 aprint_error( 618 "%s: adjust AMR_MAX_UNITS to %d (currently %d)" 619 "\n", amr->amr_dv.dv_xname, AMR_MAX_UNITS, 620 amr->amr_numdrives); 621 amr->amr_numdrives = AMR_MAX_UNITS; 622 } else 623 amr->amr_numdrives = aex->ae_numldrives; 624 625 for (i = 0; i < amr->amr_numdrives; i++) { 626 amr->amr_drive[i].al_size = 627 le32toh(aex->ae_drivesize[i]); 628 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 629 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 630 } 631 632 return (0); 633 } 634 635 /* 636 * Try 8LD extended ENQUIRY to get the controller signature. Once 637 * found, search for a product description. 638 */ 639 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 640 if (ae != NULL) { 641 i = 0; 642 sig = le32toh(ae->ae_signature); 643 644 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 645 if (amr_typestr[i].at_sig == sig) 646 break; 647 i++; 648 } 649 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 650 snprintf(sbuf, sizeof(sbuf), 651 "unknown ENQUIRY2 sig (0x%08x)", sig); 652 prodstr = sbuf; 653 } else 654 prodstr = amr_typestr[i].at_str; 655 } else { 656 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 657 if (ae == NULL) { 658 aprint_error("%s: unsupported controller\n", 659 amr->amr_dv.dv_xname); 660 return (-1); 661 } 662 663 switch (PCI_PRODUCT(pa->pa_id)) { 664 case PCI_PRODUCT_AMI_MEGARAID: 665 prodstr = "Series 428"; 666 break; 667 case PCI_PRODUCT_AMI_MEGARAID2: 668 prodstr = "Series 434"; 669 break; 670 default: 671 snprintf(sbuf, sizeof(sbuf), "unknown PCI dev (0x%04x)", 672 PCI_PRODUCT(pa->pa_id)); 673 prodstr = sbuf; 674 break; 675 } 676 } 677 678 /* 679 * HP NetRaid controllers have a special encoding of the firmware 680 * and BIOS versions. The AMI version seems to have it as strings 681 * whereas the HP version does it with a leading uppercase character 682 * and two binary numbers. 683 */ 684 aa = &ae->ae_adapter; 685 686 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 687 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 688 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 689 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 690 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 691 /* The AMI 438 is a NetRaid 3si in HP-land. */ 692 prodstr = "HP NetRaid 3si"; 693 } 694 ishp = 1; 695 } else 696 ishp = 0; 697 698 aprint_normal("<%s>\n", prodstr); 699 if (intrstr != NULL) 700 aprint_normal("%s: interrupting at %s\n", amr->amr_dv.dv_xname, 701 intrstr); 702 703 if (ishp) 704 aprint_normal("%s: firmware <%c.%02d.%02d>, BIOS <%c.%02d.%02d>" 705 ", %dMB RAM\n", amr->amr_dv.dv_xname, aa->aa_firmware[2], 706 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 707 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 708 else 709 aprint_normal("%s: firmware <%.4s>, BIOS <%.4s>, %dMB RAM\n", 710 amr->amr_dv.dv_xname, aa->aa_firmware, aa->aa_bios, 711 aa->aa_memorysize); 712 713 amr->amr_maxqueuecnt = aa->aa_maxio; 714 715 /* 716 * Record state of logical drives. 717 */ 718 if (ae->ae_ldrv.al_numdrives > __arraycount(ae->ae_ldrv.al_size)) { 719 aprint_error("%s: Inquiry returned more drives (%d)" 720 " than the array can handle (%zu)\n", 721 amr->amr_dv.dv_xname, ae->ae_ldrv.al_numdrives, 722 __arraycount(ae->ae_ldrv.al_size)); 723 ae->ae_ldrv.al_numdrives = __arraycount(ae->ae_ldrv.al_size); 724 } 725 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 726 aprint_error("%s: adjust AMR_MAX_UNITS to %d (currently %d)\n", 727 amr->amr_dv.dv_xname, ae->ae_ldrv.al_numdrives, 728 AMR_MAX_UNITS); 729 amr->amr_numdrives = AMR_MAX_UNITS; 730 } else 731 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 732 733 for (i = 0; i < amr->amr_numdrives; i++) { 734 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 735 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 736 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 737 } 738 739 return (0); 740 } 741 742 /* 743 * Flush the internal cache on each configured controller. Called at 744 * shutdown time. 745 */ 746 static void 747 amr_shutdown(void *cookie) 748 { 749 extern struct cfdriver amr_cd; 750 struct amr_softc *amr; 751 struct amr_ccb *ac; 752 int i, rv, s; 753 754 for (i = 0; i < amr_cd.cd_ndevs; i++) { 755 if ((amr = device_lookup(&amr_cd, i)) == NULL) 756 continue; 757 758 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 759 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 760 s = splbio(); 761 rv = amr_ccb_poll(amr, ac, 30000); 762 splx(s); 763 amr_ccb_free(amr, ac); 764 } 765 if (rv != 0) 766 printf("%s: unable to flush cache (%d)\n", 767 amr->amr_dv.dv_xname, rv); 768 } 769 } 770 771 /* 772 * Interrupt service routine. 773 */ 774 static int 775 amr_intr(void *cookie) 776 { 777 struct amr_softc *amr; 778 struct amr_ccb *ac; 779 struct amr_mailbox_resp mbox; 780 u_int i, forus, idx; 781 782 amr = cookie; 783 forus = 0; 784 785 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 786 /* Iterate over completed commands in this result. */ 787 for (i = 0; i < mbox.mb_nstatus; i++) { 788 idx = mbox.mb_completed[i] - 1; 789 ac = amr->amr_ccbs + idx; 790 791 if (idx >= amr->amr_maxqueuecnt) { 792 printf("%s: bad status (bogus ID: %u=%u)\n", 793 amr->amr_dv.dv_xname, i, idx); 794 continue; 795 } 796 797 if ((ac->ac_flags & AC_ACTIVE) == 0) { 798 printf("%s: bad status (not active; 0x04%x)\n", 799 amr->amr_dv.dv_xname, ac->ac_flags); 800 continue; 801 } 802 803 ac->ac_status = mbox.mb_status; 804 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 805 AC_COMPLETE; 806 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 807 808 if ((ac->ac_flags & AC_MOAN) != 0) 809 printf("%s: ccb %d completed\n", 810 amr->amr_dv.dv_xname, ac->ac_ident); 811 812 /* Pass notification to upper layers. */ 813 if (ac->ac_handler != NULL) 814 (*ac->ac_handler)(ac); 815 else 816 wakeup(ac); 817 } 818 forus = 1; 819 } 820 821 if (forus) 822 amr_ccb_enqueue(amr, NULL); 823 824 return (forus); 825 } 826 827 /* 828 * Watchdog thread. 829 */ 830 static void 831 amr_thread(void *cookie) 832 { 833 struct amr_softc *amr; 834 struct amr_ccb *ac; 835 struct amr_logdrive *al; 836 struct amr_enquiry *ae; 837 int rv, i, s; 838 839 amr = cookie; 840 ae = amr->amr_enqbuf; 841 842 for (;;) { 843 tsleep(amr_thread, PWAIT, "amrwdog", AMR_WDOG_TICKS); 844 845 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 846 amr->amr_flags ^= AMRF_THREAD_EXIT; 847 wakeup(&amr->amr_flags); 848 kthread_exit(0); 849 } 850 851 s = splbio(); 852 amr_intr(cookie); 853 ac = TAILQ_FIRST(&amr->amr_ccb_active); 854 while (ac != NULL) { 855 if (ac->ac_start_time + AMR_TIMEOUT > time_uptime) 856 break; 857 if ((ac->ac_flags & AC_MOAN) == 0) { 858 printf("%s: ccb %d timed out; mailbox:\n", 859 amr->amr_dv.dv_xname, ac->ac_ident); 860 amr_ccb_dump(amr, ac); 861 ac->ac_flags |= AC_MOAN; 862 } 863 ac = TAILQ_NEXT(ac, ac_chain.tailq); 864 } 865 splx(s); 866 867 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 868 printf("%s: ccb_alloc failed (%d)\n", 869 amr->amr_dv.dv_xname, rv); 870 continue; 871 } 872 873 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 874 875 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 876 AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 877 if (rv != 0) { 878 printf("%s: ccb_map failed (%d)\n", 879 amr->amr_dv.dv_xname, rv); 880 amr_ccb_free(amr, ac); 881 continue; 882 } 883 884 rv = amr_ccb_wait(amr, ac); 885 amr_ccb_unmap(amr, ac); 886 if (rv != 0) { 887 printf("%s: enquiry failed (st=%d)\n", 888 amr->amr_dv.dv_xname, ac->ac_status); 889 continue; 890 } 891 amr_ccb_free(amr, ac); 892 893 al = amr->amr_drive; 894 for (i = 0; i < __arraycount(ae->ae_ldrv.al_state); i++, al++) { 895 if (al->al_dv == NULL) 896 continue; 897 if (al->al_state == ae->ae_ldrv.al_state[i]) 898 continue; 899 900 printf("%s: state changed: %s -> %s\n", 901 al->al_dv->dv_xname, 902 amr_drive_state(al->al_state, NULL), 903 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 904 905 al->al_state = ae->ae_ldrv.al_state[i]; 906 } 907 } 908 } 909 910 /* 911 * Return a text description of a logical drive's current state. 912 */ 913 const char * 914 amr_drive_state(int state, int *happy) 915 { 916 const char *str; 917 918 state = AMR_DRV_CURSTATE(state); 919 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 920 if (happy) 921 *happy = 1; 922 str = "status unknown"; 923 } else { 924 if (happy) 925 *happy = amr_dstate[state].ds_happy; 926 str = amr_dstate[state].ds_descr; 927 } 928 929 return (str); 930 } 931 932 /* 933 * Run a generic enquiry-style command. 934 */ 935 static void * 936 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 937 u_int8_t cmdqual, void *sbuf) 938 { 939 struct amr_ccb *ac; 940 u_int8_t *mb; 941 int rv; 942 943 if (amr_ccb_alloc(amr, &ac) != 0) 944 return (NULL); 945 946 /* Build the command proper. */ 947 mb = (u_int8_t *)&ac->ac_cmd; 948 mb[0] = cmd; 949 mb[2] = cmdsub; 950 mb[3] = cmdqual; 951 952 rv = amr_ccb_map(amr, ac, sbuf, AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 953 if (rv == 0) { 954 rv = amr_ccb_poll(amr, ac, 2000); 955 amr_ccb_unmap(amr, ac); 956 } 957 amr_ccb_free(amr, ac); 958 959 return (rv ? NULL : sbuf); 960 } 961 962 /* 963 * Allocate and initialise a CCB. 964 */ 965 int 966 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 967 { 968 int s; 969 970 s = splbio(); 971 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 972 splx(s); 973 return (EAGAIN); 974 } 975 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 976 splx(s); 977 978 return (0); 979 } 980 981 /* 982 * Free a CCB. 983 */ 984 void 985 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 986 { 987 int s; 988 989 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 990 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 991 ac->ac_cmd.mb_busy = 1; 992 ac->ac_handler = NULL; 993 ac->ac_flags = 0; 994 995 s = splbio(); 996 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 997 splx(s); 998 } 999 1000 /* 1001 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1002 * the order that they were enqueued and try to submit their command blocks 1003 * to the controller for execution. 1004 */ 1005 void 1006 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 1007 { 1008 int s; 1009 1010 s = splbio(); 1011 1012 if (ac != NULL) 1013 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 1014 1015 while ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1016 if ((*amr->amr_submit)(amr, ac) != 0) 1017 break; 1018 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, ac_chain.simpleq); 1019 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1020 } 1021 1022 splx(s); 1023 } 1024 1025 /* 1026 * Map the specified CCB's data buffer onto the bus, and fill the 1027 * scatter-gather list. 1028 */ 1029 int 1030 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1031 int tflag) 1032 { 1033 struct amr_sgentry *sge; 1034 struct amr_mailbox_cmd *mb; 1035 int nsegs, i, rv, sgloff; 1036 bus_dmamap_t xfer; 1037 int dmaflag = 0; 1038 1039 xfer = ac->ac_xfer_map; 1040 1041 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1042 BUS_DMA_NOWAIT); 1043 if (rv != 0) 1044 return (rv); 1045 1046 mb = &ac->ac_cmd; 1047 ac->ac_xfer_size = size; 1048 ac->ac_flags |= (tflag & (AC_XFER_OUT | AC_XFER_IN)); 1049 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1050 1051 if (tflag & AC_XFER_OUT) 1052 dmaflag |= BUS_DMASYNC_PREWRITE; 1053 if (tflag & AC_XFER_IN) 1054 dmaflag |= BUS_DMASYNC_PREREAD; 1055 1056 /* We don't need to use a scatter/gather list for just 1 segment. */ 1057 nsegs = xfer->dm_nsegs; 1058 if (nsegs == 1) { 1059 mb->mb_nsgelem = 0; 1060 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1061 ac->ac_flags |= AC_NOSGL; 1062 } else { 1063 mb->mb_nsgelem = nsegs; 1064 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1065 1066 sge = (struct amr_sgentry *)((char *)amr->amr_sgls + sgloff); 1067 for (i = 0; i < nsegs; i++, sge++) { 1068 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1069 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1070 } 1071 } 1072 1073 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, dmaflag); 1074 1075 if ((ac->ac_flags & AC_NOSGL) == 0) 1076 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1077 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1078 1079 return (0); 1080 } 1081 1082 /* 1083 * Unmap the specified CCB's data buffer. 1084 */ 1085 void 1086 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1087 { 1088 int dmaflag = 0; 1089 1090 if (ac->ac_flags & AC_XFER_IN) 1091 dmaflag |= BUS_DMASYNC_POSTREAD; 1092 if (ac->ac_flags & AC_XFER_OUT) 1093 dmaflag |= BUS_DMASYNC_POSTWRITE; 1094 1095 if ((ac->ac_flags & AC_NOSGL) == 0) 1096 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1097 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1098 BUS_DMASYNC_POSTWRITE); 1099 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1100 dmaflag); 1101 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1102 } 1103 1104 /* 1105 * Submit a command to the controller and poll on completion. Return 1106 * non-zero on timeout or error. Must be called with interrupts blocked. 1107 */ 1108 int 1109 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1110 { 1111 int rv; 1112 1113 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) 1114 return (rv); 1115 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1116 1117 for (timo *= 10; timo != 0; timo--) { 1118 amr_intr(amr); 1119 if ((ac->ac_flags & AC_COMPLETE) != 0) 1120 break; 1121 DELAY(100); 1122 } 1123 1124 return (timo == 0 || ac->ac_status != 0 ? EIO : 0); 1125 } 1126 1127 /* 1128 * Submit a command to the controller and sleep on completion. Return 1129 * non-zero on error. 1130 */ 1131 int 1132 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1133 { 1134 int s; 1135 1136 s = splbio(); 1137 amr_ccb_enqueue(amr, ac); 1138 tsleep(ac, PRIBIO, "amrcmd", 0); 1139 splx(s); 1140 1141 return (ac->ac_status != 0 ? EIO : 0); 1142 } 1143 1144 #if 0 1145 /* 1146 * Wait for the mailbox to become available. 1147 */ 1148 static int 1149 amr_mbox_wait(struct amr_softc *amr) 1150 { 1151 int timo; 1152 1153 for (timo = 10000; timo != 0; timo--) { 1154 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1155 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1156 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1157 break; 1158 DELAY(100); 1159 } 1160 1161 if (timo == 0) 1162 printf("%s: controller wedged\n", amr->amr_dv.dv_xname); 1163 1164 return (timo != 0 ? 0 : EAGAIN); 1165 } 1166 #endif 1167 1168 /* 1169 * Tell the controller that the mailbox contains a valid command. Must be 1170 * called with interrupts blocked. 1171 */ 1172 static int 1173 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1174 { 1175 u_int32_t v; 1176 1177 amr->amr_mbox->mb_poll = 0; 1178 amr->amr_mbox->mb_ack = 0; 1179 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1180 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1181 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1182 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1183 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1184 return (EAGAIN); 1185 1186 v = amr_inl(amr, AMR_QREG_IDB); 1187 if ((v & AMR_QIDB_SUBMIT) != 0) { 1188 amr->amr_mbox->mb_cmd.mb_busy = 0; 1189 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1190 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1191 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1192 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1193 return (EAGAIN); 1194 } 1195 1196 amr->amr_mbox->mb_segment = 0; 1197 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1198 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1199 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1200 1201 ac->ac_start_time = time_uptime; 1202 ac->ac_flags |= AC_ACTIVE; 1203 amr_outl(amr, AMR_QREG_IDB, 1204 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1205 return (0); 1206 } 1207 1208 static int 1209 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1210 { 1211 1212 amr->amr_mbox->mb_poll = 0; 1213 amr->amr_mbox->mb_ack = 0; 1214 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1215 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1216 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1217 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1218 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1219 return (EAGAIN); 1220 1221 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1222 amr->amr_mbox->mb_cmd.mb_busy = 0; 1223 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1224 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1225 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1226 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1227 return (EAGAIN); 1228 } 1229 1230 amr->amr_mbox->mb_segment = 0; 1231 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1232 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1233 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1234 1235 ac->ac_start_time = time_uptime; 1236 ac->ac_flags |= AC_ACTIVE; 1237 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1238 return (0); 1239 } 1240 1241 /* 1242 * Claim any work that the controller has completed; acknowledge completion, 1243 * save details of the completion in (mbsave). Must be called with 1244 * interrupts blocked. 1245 */ 1246 static int 1247 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1248 { 1249 1250 /* Work waiting for us? */ 1251 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1252 return (-1); 1253 1254 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1255 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1256 1257 /* Save the mailbox, which contains a list of completed commands. */ 1258 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1259 1260 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1261 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1262 1263 /* Ack the interrupt and mailbox transfer. */ 1264 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1265 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1266 1267 /* 1268 * This waits for the controller to notice that we've taken the 1269 * command from it. It's very inefficient, and we shouldn't do it, 1270 * but if we remove this code, we stop completing commands under 1271 * load. 1272 * 1273 * Peter J says we shouldn't do this. The documentation says we 1274 * should. Who is right? 1275 */ 1276 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1277 DELAY(10); 1278 1279 return (0); 1280 } 1281 1282 static int 1283 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1284 { 1285 u_int8_t istat; 1286 1287 /* Check for valid interrupt status. */ 1288 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1289 return (-1); 1290 1291 /* Ack the interrupt. */ 1292 amr_outb(amr, AMR_SREG_INTR, istat); 1293 1294 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1295 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1296 1297 /* Save mailbox, which contains a list of completed commands. */ 1298 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1299 1300 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1301 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1302 1303 /* Ack mailbox transfer. */ 1304 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1305 1306 return (0); 1307 } 1308 1309 static void 1310 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1311 { 1312 int i; 1313 1314 printf("%s: ", amr->amr_dv.dv_xname); 1315 for (i = 0; i < 4; i++) 1316 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1317 printf("\n"); 1318 } 1319 1320 static int 1321 amropen(dev_t dev, int flag, int mode, struct lwp *l) 1322 { 1323 struct amr_softc *amr; 1324 1325 if ((amr = device_lookup(&amr_cd, minor(dev))) == NULL) 1326 return (ENXIO); 1327 if ((amr->amr_flags & AMRF_OPEN) != 0) 1328 return (EBUSY); 1329 1330 amr->amr_flags |= AMRF_OPEN; 1331 return (0); 1332 } 1333 1334 static int 1335 amrclose(dev_t dev, int flag, int mode, struct lwp *l) 1336 { 1337 struct amr_softc *amr; 1338 1339 amr = device_lookup(&amr_cd, minor(dev)); 1340 amr->amr_flags &= ~AMRF_OPEN; 1341 return (0); 1342 } 1343 1344 static int 1345 amrioctl(dev_t dev, u_long cmd, void *data, int flag, 1346 struct lwp *l) 1347 { 1348 struct amr_softc *amr; 1349 struct amr_user_ioctl *au; 1350 struct amr_ccb *ac; 1351 struct amr_mailbox_ioctl *mbi; 1352 unsigned long au_length; 1353 uint8_t *au_cmd; 1354 int error; 1355 void *dp = NULL, *au_buffer; 1356 1357 amr = device_lookup(&amr_cd, minor(dev)); 1358 1359 /* This should be compatible with the FreeBSD interface */ 1360 1361 switch (cmd) { 1362 case AMR_IO_VERSION: 1363 *(int *)data = AMR_IO_VERSION_NUMBER; 1364 return 0; 1365 case AMR_IO_COMMAND: 1366 error = kauth_authorize_device_passthru(l->l_cred, dev, 1367 KAUTH_REQ_DEVICE_RAWIO_PASSTHRU_ALL, data); 1368 if (error) 1369 return (error); 1370 1371 au = (struct amr_user_ioctl *)data; 1372 au_cmd = au->au_cmd; 1373 au_buffer = au->au_buffer; 1374 au_length = au->au_length; 1375 break; 1376 default: 1377 return ENOTTY; 1378 } 1379 1380 if (au_cmd[0] == AMR_CMD_PASS) { 1381 /* not yet */ 1382 return EOPNOTSUPP; 1383 } 1384 1385 if (au_length <= 0 || au_length > MAXPHYS || au_cmd[0] == 0x06) 1386 return (EINVAL); 1387 1388 /* 1389 * allocate kernel memory for data, doing I/O directly to user 1390 * buffer isn't that easy. 1391 */ 1392 dp = malloc(au_length, M_DEVBUF, M_WAITOK|M_ZERO); 1393 if (dp == NULL) 1394 return ENOMEM; 1395 if ((error = copyin(au_buffer, dp, au_length)) != 0) 1396 goto out; 1397 1398 /* direct command to controller */ 1399 while (amr_ccb_alloc(amr, &ac) != 0) { 1400 error = tsleep(NULL, PRIBIO | PCATCH, "armmbx", hz); 1401 if (error == EINTR) 1402 goto out; 1403 } 1404 1405 mbi = (struct amr_mailbox_ioctl *)&ac->ac_cmd; 1406 mbi->mb_command = au_cmd[0]; 1407 mbi->mb_channel = au_cmd[1]; 1408 mbi->mb_param = au_cmd[2]; 1409 mbi->mb_pad[0] = au_cmd[3]; 1410 mbi->mb_drive = au_cmd[4]; 1411 error = amr_ccb_map(amr, ac, dp, (int)au_length, 1412 AC_XFER_IN | AC_XFER_OUT); 1413 if (error == 0) { 1414 error = amr_ccb_wait(amr, ac); 1415 amr_ccb_unmap(amr, ac); 1416 if (error == 0) 1417 error = copyout(dp, au_buffer, au_length); 1418 1419 } 1420 amr_ccb_free(amr, ac); 1421 out: 1422 free(dp, M_DEVBUF); 1423 return (error); 1424 } 1425
Indexes created Thu Oct 02 14:10:14 GMT 2025