amr.c revision 1.49
1 /* $NetBSD: amr.c,v 1.49 2008/06/08 12:43:52 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999,2000 Michael Smith 34 * Copyright (c) 2000 BSDi 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 * 58 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 59 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 60 */ 61 62 /* 63 * Driver for AMI RAID controllers. 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.49 2008/06/08 12:43:52 tsutsui Exp $"); 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/kernel.h> 72 #include <sys/device.h> 73 #include <sys/queue.h> 74 #include <sys/proc.h> 75 #include <sys/buf.h> 76 #include <sys/malloc.h> 77 #include <sys/conf.h> 78 #include <sys/kthread.h> 79 #include <sys/kauth.h> 80 81 #include <uvm/uvm_extern.h> 82 83 #include <machine/endian.h> 84 #include <sys/bus.h> 85 86 #include <dev/pci/pcidevs.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/amrreg.h> 89 #include <dev/pci/amrvar.h> 90 #include <dev/pci/amrio.h> 91 92 #include "locators.h" 93 94 static void amr_attach(struct device *, struct device *, void *); 95 static void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 96 static void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, 97 void *); 98 static int amr_init(struct amr_softc *, const char *, 99 struct pci_attach_args *pa); 100 static int amr_intr(void *); 101 static int amr_match(struct device *, struct cfdata *, void *); 102 static int amr_print(void *, const char *); 103 static void amr_shutdown(void *); 104 static void amr_teardown(struct amr_softc *); 105 static void amr_thread(void *); 106 107 static int amr_quartz_get_work(struct amr_softc *, 108 struct amr_mailbox_resp *); 109 static int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 110 static int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 111 static int amr_std_submit(struct amr_softc *, struct amr_ccb *); 112 113 static dev_type_open(amropen); 114 static dev_type_close(amrclose); 115 static dev_type_ioctl(amrioctl); 116 117 CFATTACH_DECL(amr, sizeof(struct amr_softc), 118 amr_match, amr_attach, NULL, NULL); 119 120 const struct cdevsw amr_cdevsw = { 121 amropen, amrclose, noread, nowrite, amrioctl, 122 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 123 }; 124 125 extern struct cfdriver amr_cd; 126 127 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 128 #define AT_SIG 0x02 /* Check for signature */ 129 130 static struct amr_pci_type { 131 u_short apt_vendor; 132 u_short apt_product; 133 u_short apt_flags; 134 } const amr_pci_type[] = { 135 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 136 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 137 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 138 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 142 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 143 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 144 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 145 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4ESI, AT_QUARTZ }, 146 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_PERC_4SC, AT_QUARTZ }, 147 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 148 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 149 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 150 }; 151 152 static struct amr_typestr { 153 const char *at_str; 154 int at_sig; 155 } const amr_typestr[] = { 156 { "Series 431", AMR_SIG_431 }, 157 { "Series 438", AMR_SIG_438 }, 158 { "Series 466", AMR_SIG_466 }, 159 { "Series 467", AMR_SIG_467 }, 160 { "Series 490", AMR_SIG_490 }, 161 { "Series 762", AMR_SIG_762 }, 162 { "HP NetRAID (T5)", AMR_SIG_T5 }, 163 { "HP NetRAID (T7)", AMR_SIG_T7 }, 164 }; 165 166 static struct { 167 const char *ds_descr; 168 int ds_happy; 169 } const amr_dstate[] = { 170 { "offline", 0 }, 171 { "degraded", 1 }, 172 { "optimal", 1 }, 173 { "online", 1 }, 174 { "failed", 0 }, 175 { "rebuilding", 1 }, 176 { "hotspare", 0 }, 177 }; 178 179 static void *amr_sdh; 180 181 static int amr_max_segs; 182 int amr_max_xfer; 183 184 static inline u_int8_t 185 amr_inb(struct amr_softc *amr, int off) 186 { 187 188 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 189 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 190 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 191 } 192 193 static inline u_int32_t 194 amr_inl(struct amr_softc *amr, int off) 195 { 196 197 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 198 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 199 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 200 } 201 202 static inline void 203 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 204 { 205 206 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 207 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 208 BUS_SPACE_BARRIER_WRITE); 209 } 210 211 static inline void 212 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 213 { 214 215 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 216 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 217 BUS_SPACE_BARRIER_WRITE); 218 } 219 220 /* 221 * Match a supported device. 222 */ 223 static int 224 amr_match(struct device *parent, struct cfdata *match, 225 void *aux) 226 { 227 struct pci_attach_args *pa; 228 pcireg_t s; 229 int i; 230 231 pa = (struct pci_attach_args *)aux; 232 233 /* 234 * Don't match the device if it's operating in I2O mode. In this 235 * case it should be handled by the `iop' driver. 236 */ 237 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 238 return (0); 239 240 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 241 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 242 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 243 break; 244 245 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 246 return (0); 247 248 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 249 return (1); 250 251 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 252 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 253 } 254 255 /* 256 * Attach a supported device. 257 */ 258 static void 259 amr_attach(struct device *parent, struct device *self, void *aux) 260 { 261 struct pci_attach_args *pa; 262 struct amr_attach_args amra; 263 const struct amr_pci_type *apt; 264 struct amr_softc *amr; 265 pci_chipset_tag_t pc; 266 pci_intr_handle_t ih; 267 const char *intrstr; 268 pcireg_t reg; 269 int rseg, i, j, size, rv, memreg, ioreg; 270 struct amr_ccb *ac; 271 int locs[AMRCF_NLOCS]; 272 273 aprint_naive(": RAID controller\n"); 274 275 amr = (struct amr_softc *)self; 276 pa = (struct pci_attach_args *)aux; 277 pc = pa->pa_pc; 278 279 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 280 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 281 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 282 break; 283 apt = amr_pci_type + i; 284 285 memreg = ioreg = 0; 286 for (i = 0x10; i <= 0x14; i += 4) { 287 reg = pci_conf_read(pc, pa->pa_tag, i); 288 switch (PCI_MAPREG_TYPE(reg)) { 289 case PCI_MAPREG_TYPE_MEM: 290 if (PCI_MAPREG_MEM_SIZE(reg) != 0) 291 memreg = i; 292 break; 293 case PCI_MAPREG_TYPE_IO: 294 if (PCI_MAPREG_IO_SIZE(reg) != 0) 295 ioreg = i; 296 break; 297 298 } 299 } 300 301 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 302 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 303 ; 304 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 305 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 306 ; 307 else { 308 aprint_error("can't map control registers\n"); 309 amr_teardown(amr); 310 return; 311 } 312 313 amr->amr_flags |= AMRF_PCI_REGS; 314 amr->amr_dmat = pa->pa_dmat; 315 amr->amr_pc = pa->pa_pc; 316 317 /* Enable the device. */ 318 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 319 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 320 reg | PCI_COMMAND_MASTER_ENABLE); 321 322 /* Map and establish the interrupt. */ 323 if (pci_intr_map(pa, &ih)) { 324 aprint_error("can't map interrupt\n"); 325 amr_teardown(amr); 326 return; 327 } 328 intrstr = pci_intr_string(pc, ih); 329 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); 330 if (amr->amr_ih == NULL) { 331 aprint_error("can't establish interrupt"); 332 if (intrstr != NULL) 333 aprint_normal(" at %s", intrstr); 334 aprint_normal("\n"); 335 amr_teardown(amr); 336 return; 337 } 338 amr->amr_flags |= AMRF_PCI_INTR; 339 340 /* 341 * Allocate space for the mailbox and S/G lists. Some controllers 342 * don't like S/G lists to be located below 0x2000, so we allocate 343 * enough slop to enable us to compensate. 344 * 345 * The standard mailbox structure needs to be aligned on a 16-byte 346 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 347 * size, which precedes the standard mailbox. 348 */ 349 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 350 amr->amr_dmasize = size; 351 352 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, 353 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 354 aprint_error_dev(&amr->amr_dv, "unable to allocate buffer, rv = %d\n", 355 rv); 356 amr_teardown(amr); 357 return; 358 } 359 amr->amr_flags |= AMRF_DMA_ALLOC; 360 361 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 362 (void **)&amr->amr_mbox, 363 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 364 aprint_error_dev(&amr->amr_dv, "unable to map buffer, rv = %d\n", 365 rv); 366 amr_teardown(amr); 367 return; 368 } 369 amr->amr_flags |= AMRF_DMA_MAP; 370 371 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 372 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 373 aprint_error_dev(&amr->amr_dv, "unable to create buffer DMA map, rv = %d\n", 374 rv); 375 amr_teardown(amr); 376 return; 377 } 378 amr->amr_flags |= AMRF_DMA_CREATE; 379 380 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 381 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 382 aprint_error_dev(&amr->amr_dv, "unable to load buffer DMA map, rv = %d\n", 383 rv); 384 amr_teardown(amr); 385 return; 386 } 387 amr->amr_flags |= AMRF_DMA_LOAD; 388 389 memset(amr->amr_mbox, 0, size); 390 391 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 392 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 393 amr->amr_sgls = (struct amr_sgentry *)((char *)amr->amr_mbox + 394 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 395 396 /* 397 * Allocate and initalise the command control blocks. 398 */ 399 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); 400 amr->amr_ccbs = ac; 401 SLIST_INIT(&amr->amr_ccb_freelist); 402 TAILQ_INIT(&amr->amr_ccb_active); 403 amr->amr_flags |= AMRF_CCBS; 404 405 if (amr_max_xfer == 0) { 406 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); 407 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 408 } 409 410 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 411 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 412 amr_max_segs, amr_max_xfer, 0, 413 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 414 if (rv != 0) 415 break; 416 417 ac->ac_ident = i; 418 amr_ccb_free(amr, ac); 419 } 420 if (i != AMR_MAX_CMDS) { 421 aprint_error_dev(&amr->amr_dv, "memory exhausted\n"); 422 amr_teardown(amr); 423 return; 424 } 425 426 /* 427 * Take care of model-specific tasks. 428 */ 429 if ((apt->apt_flags & AT_QUARTZ) != 0) { 430 amr->amr_submit = amr_quartz_submit; 431 amr->amr_get_work = amr_quartz_get_work; 432 } else { 433 amr->amr_submit = amr_std_submit; 434 amr->amr_get_work = amr_std_get_work; 435 436 /* Notify the controller of the mailbox location. */ 437 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 438 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 439 440 /* Clear outstanding interrupts and enable interrupts. */ 441 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 442 amr_outb(amr, AMR_SREG_TOGL, 443 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 444 } 445 446 /* 447 * Retrieve parameters, and tell the world about us. 448 */ 449 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); 450 amr->amr_flags |= AMRF_ENQBUF; 451 amr->amr_maxqueuecnt = i; 452 aprint_normal(": AMI RAID "); 453 if (amr_init(amr, intrstr, pa) != 0) { 454 amr_teardown(amr); 455 return; 456 } 457 458 /* 459 * Cap the maximum number of outstanding commands. AMI's Linux 460 * driver doesn't trust the controller's reported value, and lockups 461 * have been seen when we do. 462 */ 463 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 464 if (amr->amr_maxqueuecnt > i) 465 amr->amr_maxqueuecnt = i; 466 467 /* Set our `shutdownhook' before we start any device activity. */ 468 if (amr_sdh == NULL) 469 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 470 471 /* Attach sub-devices. */ 472 for (j = 0; j < amr->amr_numdrives; j++) { 473 if (amr->amr_drive[j].al_size == 0) 474 continue; 475 amra.amra_unit = j; 476 477 locs[AMRCF_UNIT] = j; 478 479 amr->amr_drive[j].al_dv = config_found_sm_loc(&amr->amr_dv, 480 "amr", locs, &amra, amr_print, config_stdsubmatch); 481 } 482 483 SIMPLEQ_INIT(&amr->amr_ccb_queue); 484 485 /* XXX This doesn't work for newer boards yet. */ 486 if ((apt->apt_flags & AT_QUARTZ) == 0) { 487 rv = kthread_create(PRI_NONE, 0, NULL, amr_thread, amr, 488 &amr->amr_thread, "%s", device_xname(&amr->amr_dv)); 489 if (rv != 0) 490 aprint_error_dev(&amr->amr_dv, "unable to create thread (%d)", 491 rv); 492 else 493 amr->amr_flags |= AMRF_THREAD; 494 } 495 } 496 497 /* 498 * Free up resources. 499 */ 500 static void 501 amr_teardown(struct amr_softc *amr) 502 { 503 struct amr_ccb *ac; 504 int fl; 505 506 fl = amr->amr_flags; 507 508 if ((fl & AMRF_THREAD) != 0) { 509 amr->amr_flags |= AMRF_THREAD_EXIT; 510 wakeup(amr_thread); 511 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) 512 tsleep(&amr->amr_flags, PWAIT, "amrexit", 0); 513 } 514 if ((fl & AMRF_CCBS) != 0) { 515 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 516 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 517 } 518 free(amr->amr_ccbs, M_DEVBUF); 519 } 520 if ((fl & AMRF_ENQBUF) != 0) 521 free(amr->amr_enqbuf, M_DEVBUF); 522 if ((fl & AMRF_DMA_LOAD) != 0) 523 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 524 if ((fl & AMRF_DMA_MAP) != 0) 525 bus_dmamem_unmap(amr->amr_dmat, (void *)amr->amr_mbox, 526 amr->amr_dmasize); 527 if ((fl & AMRF_DMA_ALLOC) != 0) 528 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 529 if ((fl & AMRF_DMA_CREATE) != 0) 530 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 531 if ((fl & AMRF_PCI_INTR) != 0) 532 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 533 if ((fl & AMRF_PCI_REGS) != 0) 534 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 535 } 536 537 /* 538 * Print autoconfiguration message for a sub-device. 539 */ 540 static int 541 amr_print(void *aux, const char *pnp) 542 { 543 struct amr_attach_args *amra; 544 545 amra = (struct amr_attach_args *)aux; 546 547 if (pnp != NULL) 548 aprint_normal("block device at %s", pnp); 549 aprint_normal(" unit %d", amra->amra_unit); 550 return (UNCONF); 551 } 552 553 /* 554 * Retrieve operational parameters and describe the controller. 555 */ 556 static int 557 amr_init(struct amr_softc *amr, const char *intrstr, 558 struct pci_attach_args *pa) 559 { 560 struct amr_adapter_info *aa; 561 struct amr_prodinfo *ap; 562 struct amr_enquiry *ae; 563 struct amr_enquiry3 *aex; 564 const char *prodstr; 565 u_int i, sig, ishp; 566 char sbuf[64]; 567 568 /* 569 * Try to get 40LD product info, which tells us what the card is 570 * labelled as. 571 */ 572 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 573 amr->amr_enqbuf); 574 if (ap != NULL) { 575 aprint_normal("<%.80s>\n", ap->ap_product); 576 if (intrstr != NULL) 577 aprint_normal_dev(&amr->amr_dv, "interrupting at %s\n", 578 intrstr); 579 aprint_normal_dev(&amr->amr_dv, "firmware %.16s, BIOS %.16s, %dMB RAM\n", 580 ap->ap_firmware, ap->ap_bios, 581 le16toh(ap->ap_memsize)); 582 583 amr->amr_maxqueuecnt = ap->ap_maxio; 584 585 /* 586 * Fetch and record state of logical drives. 587 */ 588 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 589 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 590 if (aex == NULL) { 591 aprint_error_dev(&amr->amr_dv, "ENQUIRY3 failed\n"); 592 return (-1); 593 } 594 595 if (aex->ae_numldrives > __arraycount(aex->ae_drivestate)) { 596 aprint_error_dev(&amr->amr_dv, "Inquiry returned more drives (%d)" 597 " than the array can handle (%zu)\n", 598 aex->ae_numldrives, 599 __arraycount(aex->ae_drivestate)); 600 aex->ae_numldrives = __arraycount(aex->ae_drivestate); 601 } 602 if (aex->ae_numldrives > AMR_MAX_UNITS) { 603 aprint_error_dev(&amr->amr_dv, 604 "adjust AMR_MAX_UNITS to %d (currently %d)" 605 "\n", AMR_MAX_UNITS, 606 amr->amr_numdrives); 607 amr->amr_numdrives = AMR_MAX_UNITS; 608 } else 609 amr->amr_numdrives = aex->ae_numldrives; 610 611 for (i = 0; i < amr->amr_numdrives; i++) { 612 amr->amr_drive[i].al_size = 613 le32toh(aex->ae_drivesize[i]); 614 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 615 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 616 } 617 618 return (0); 619 } 620 621 /* 622 * Try 8LD extended ENQUIRY to get the controller signature. Once 623 * found, search for a product description. 624 */ 625 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 626 if (ae != NULL) { 627 i = 0; 628 sig = le32toh(ae->ae_signature); 629 630 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 631 if (amr_typestr[i].at_sig == sig) 632 break; 633 i++; 634 } 635 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 636 snprintf(sbuf, sizeof(sbuf), 637 "unknown ENQUIRY2 sig (0x%08x)", sig); 638 prodstr = sbuf; 639 } else 640 prodstr = amr_typestr[i].at_str; 641 } else { 642 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 643 if (ae == NULL) { 644 aprint_error_dev(&amr->amr_dv, "unsupported controller\n"); 645 return (-1); 646 } 647 648 switch (PCI_PRODUCT(pa->pa_id)) { 649 case PCI_PRODUCT_AMI_MEGARAID: 650 prodstr = "Series 428"; 651 break; 652 case PCI_PRODUCT_AMI_MEGARAID2: 653 prodstr = "Series 434"; 654 break; 655 default: 656 snprintf(sbuf, sizeof(sbuf), "unknown PCI dev (0x%04x)", 657 PCI_PRODUCT(pa->pa_id)); 658 prodstr = sbuf; 659 break; 660 } 661 } 662 663 /* 664 * HP NetRaid controllers have a special encoding of the firmware 665 * and BIOS versions. The AMI version seems to have it as strings 666 * whereas the HP version does it with a leading uppercase character 667 * and two binary numbers. 668 */ 669 aa = &ae->ae_adapter; 670 671 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 672 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 673 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 674 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 675 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 676 /* The AMI 438 is a NetRaid 3si in HP-land. */ 677 prodstr = "HP NetRaid 3si"; 678 } 679 ishp = 1; 680 } else 681 ishp = 0; 682 683 aprint_normal("<%s>\n", prodstr); 684 if (intrstr != NULL) 685 aprint_normal_dev(&amr->amr_dv, "interrupting at %s\n", 686 intrstr); 687 688 if (ishp) 689 aprint_normal_dev(&amr->amr_dv, "firmware <%c.%02d.%02d>, BIOS <%c.%02d.%02d>" 690 ", %dMB RAM\n", aa->aa_firmware[2], 691 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 692 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 693 else 694 aprint_normal_dev(&amr->amr_dv, "firmware <%.4s>, BIOS <%.4s>, %dMB RAM\n", 695 aa->aa_firmware, aa->aa_bios, 696 aa->aa_memorysize); 697 698 amr->amr_maxqueuecnt = aa->aa_maxio; 699 700 /* 701 * Record state of logical drives. 702 */ 703 if (ae->ae_ldrv.al_numdrives > __arraycount(ae->ae_ldrv.al_size)) { 704 aprint_error_dev(&amr->amr_dv, "Inquiry returned more drives (%d)" 705 " than the array can handle (%zu)\n", 706 ae->ae_ldrv.al_numdrives, 707 __arraycount(ae->ae_ldrv.al_size)); 708 ae->ae_ldrv.al_numdrives = __arraycount(ae->ae_ldrv.al_size); 709 } 710 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 711 aprint_error_dev(&amr->amr_dv, "adjust AMR_MAX_UNITS to %d (currently %d)\n", 712 ae->ae_ldrv.al_numdrives, 713 AMR_MAX_UNITS); 714 amr->amr_numdrives = AMR_MAX_UNITS; 715 } else 716 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 717 718 for (i = 0; i < amr->amr_numdrives; i++) { 719 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 720 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 721 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 722 } 723 724 return (0); 725 } 726 727 /* 728 * Flush the internal cache on each configured controller. Called at 729 * shutdown time. 730 */ 731 static void 732 amr_shutdown(void *cookie) 733 { 734 extern struct cfdriver amr_cd; 735 struct amr_softc *amr; 736 struct amr_ccb *ac; 737 int i, rv, s; 738 739 for (i = 0; i < amr_cd.cd_ndevs; i++) { 740 if ((amr = device_lookup_private(&amr_cd, i)) == NULL) 741 continue; 742 743 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 744 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 745 s = splbio(); 746 rv = amr_ccb_poll(amr, ac, 30000); 747 splx(s); 748 amr_ccb_free(amr, ac); 749 } 750 if (rv != 0) 751 aprint_error_dev(&amr->amr_dv, "unable to flush cache (%d)\n", rv); 752 } 753 } 754 755 /* 756 * Interrupt service routine. 757 */ 758 static int 759 amr_intr(void *cookie) 760 { 761 struct amr_softc *amr; 762 struct amr_ccb *ac; 763 struct amr_mailbox_resp mbox; 764 u_int i, forus, idx; 765 766 amr = cookie; 767 forus = 0; 768 769 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 770 /* Iterate over completed commands in this result. */ 771 for (i = 0; i < mbox.mb_nstatus; i++) { 772 idx = mbox.mb_completed[i] - 1; 773 ac = amr->amr_ccbs + idx; 774 775 if (idx >= amr->amr_maxqueuecnt) { 776 printf("%s: bad status (bogus ID: %u=%u)\n", 777 device_xname(&amr->amr_dv), i, idx); 778 continue; 779 } 780 781 if ((ac->ac_flags & AC_ACTIVE) == 0) { 782 printf("%s: bad status (not active; 0x04%x)\n", 783 device_xname(&amr->amr_dv), ac->ac_flags); 784 continue; 785 } 786 787 ac->ac_status = mbox.mb_status; 788 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 789 AC_COMPLETE; 790 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 791 792 if ((ac->ac_flags & AC_MOAN) != 0) 793 printf("%s: ccb %d completed\n", 794 device_xname(&amr->amr_dv), ac->ac_ident); 795 796 /* Pass notification to upper layers. */ 797 if (ac->ac_handler != NULL) 798 (*ac->ac_handler)(ac); 799 else 800 wakeup(ac); 801 } 802 forus = 1; 803 } 804 805 if (forus) 806 amr_ccb_enqueue(amr, NULL); 807 808 return (forus); 809 } 810 811 /* 812 * Watchdog thread. 813 */ 814 static void 815 amr_thread(void *cookie) 816 { 817 struct amr_softc *amr; 818 struct amr_ccb *ac; 819 struct amr_logdrive *al; 820 struct amr_enquiry *ae; 821 int rv, i, s; 822 823 amr = cookie; 824 ae = amr->amr_enqbuf; 825 826 for (;;) { 827 tsleep(amr_thread, PWAIT, "amrwdog", AMR_WDOG_TICKS); 828 829 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 830 amr->amr_flags ^= AMRF_THREAD_EXIT; 831 wakeup(&amr->amr_flags); 832 kthread_exit(0); 833 } 834 835 s = splbio(); 836 amr_intr(cookie); 837 ac = TAILQ_FIRST(&amr->amr_ccb_active); 838 while (ac != NULL) { 839 if (ac->ac_start_time + AMR_TIMEOUT > time_uptime) 840 break; 841 if ((ac->ac_flags & AC_MOAN) == 0) { 842 printf("%s: ccb %d timed out; mailbox:\n", 843 device_xname(&amr->amr_dv), ac->ac_ident); 844 amr_ccb_dump(amr, ac); 845 ac->ac_flags |= AC_MOAN; 846 } 847 ac = TAILQ_NEXT(ac, ac_chain.tailq); 848 } 849 splx(s); 850 851 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 852 printf("%s: ccb_alloc failed (%d)\n", 853 device_xname(&amr->amr_dv), rv); 854 continue; 855 } 856 857 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 858 859 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 860 AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 861 if (rv != 0) { 862 aprint_error_dev(&amr->amr_dv, "ccb_map failed (%d)\n", 863 rv); 864 amr_ccb_free(amr, ac); 865 continue; 866 } 867 868 rv = amr_ccb_wait(amr, ac); 869 amr_ccb_unmap(amr, ac); 870 if (rv != 0) { 871 aprint_error_dev(&amr->amr_dv, "enquiry failed (st=%d)\n", 872 ac->ac_status); 873 continue; 874 } 875 amr_ccb_free(amr, ac); 876 877 al = amr->amr_drive; 878 for (i = 0; i < __arraycount(ae->ae_ldrv.al_state); i++, al++) { 879 if (al->al_dv == NULL) 880 continue; 881 if (al->al_state == ae->ae_ldrv.al_state[i]) 882 continue; 883 884 printf("%s: state changed: %s -> %s\n", 885 device_xname(al->al_dv), 886 amr_drive_state(al->al_state, NULL), 887 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 888 889 al->al_state = ae->ae_ldrv.al_state[i]; 890 } 891 } 892 } 893 894 /* 895 * Return a text description of a logical drive's current state. 896 */ 897 const char * 898 amr_drive_state(int state, int *happy) 899 { 900 const char *str; 901 902 state = AMR_DRV_CURSTATE(state); 903 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 904 if (happy) 905 *happy = 1; 906 str = "status unknown"; 907 } else { 908 if (happy) 909 *happy = amr_dstate[state].ds_happy; 910 str = amr_dstate[state].ds_descr; 911 } 912 913 return (str); 914 } 915 916 /* 917 * Run a generic enquiry-style command. 918 */ 919 static void * 920 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 921 u_int8_t cmdqual, void *sbuf) 922 { 923 struct amr_ccb *ac; 924 u_int8_t *mb; 925 int rv; 926 927 if (amr_ccb_alloc(amr, &ac) != 0) 928 return (NULL); 929 930 /* Build the command proper. */ 931 mb = (u_int8_t *)&ac->ac_cmd; 932 mb[0] = cmd; 933 mb[2] = cmdsub; 934 mb[3] = cmdqual; 935 936 rv = amr_ccb_map(amr, ac, sbuf, AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 937 if (rv == 0) { 938 rv = amr_ccb_poll(amr, ac, 2000); 939 amr_ccb_unmap(amr, ac); 940 } 941 amr_ccb_free(amr, ac); 942 943 return (rv ? NULL : sbuf); 944 } 945 946 /* 947 * Allocate and initialise a CCB. 948 */ 949 int 950 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 951 { 952 int s; 953 954 s = splbio(); 955 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 956 splx(s); 957 return (EAGAIN); 958 } 959 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 960 splx(s); 961 962 return (0); 963 } 964 965 /* 966 * Free a CCB. 967 */ 968 void 969 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 970 { 971 int s; 972 973 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 974 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 975 ac->ac_cmd.mb_busy = 1; 976 ac->ac_handler = NULL; 977 ac->ac_flags = 0; 978 979 s = splbio(); 980 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 981 splx(s); 982 } 983 984 /* 985 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 986 * the order that they were enqueued and try to submit their command blocks 987 * to the controller for execution. 988 */ 989 void 990 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 991 { 992 int s; 993 994 s = splbio(); 995 996 if (ac != NULL) 997 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 998 999 while ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1000 if ((*amr->amr_submit)(amr, ac) != 0) 1001 break; 1002 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, ac_chain.simpleq); 1003 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1004 } 1005 1006 splx(s); 1007 } 1008 1009 /* 1010 * Map the specified CCB's data buffer onto the bus, and fill the 1011 * scatter-gather list. 1012 */ 1013 int 1014 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1015 int tflag) 1016 { 1017 struct amr_sgentry *sge; 1018 struct amr_mailbox_cmd *mb; 1019 int nsegs, i, rv, sgloff; 1020 bus_dmamap_t xfer; 1021 int dmaflag = 0; 1022 1023 xfer = ac->ac_xfer_map; 1024 1025 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1026 BUS_DMA_NOWAIT); 1027 if (rv != 0) 1028 return (rv); 1029 1030 mb = &ac->ac_cmd; 1031 ac->ac_xfer_size = size; 1032 ac->ac_flags |= (tflag & (AC_XFER_OUT | AC_XFER_IN)); 1033 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1034 1035 if (tflag & AC_XFER_OUT) 1036 dmaflag |= BUS_DMASYNC_PREWRITE; 1037 if (tflag & AC_XFER_IN) 1038 dmaflag |= BUS_DMASYNC_PREREAD; 1039 1040 /* We don't need to use a scatter/gather list for just 1 segment. */ 1041 nsegs = xfer->dm_nsegs; 1042 if (nsegs == 1) { 1043 mb->mb_nsgelem = 0; 1044 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1045 ac->ac_flags |= AC_NOSGL; 1046 } else { 1047 mb->mb_nsgelem = nsegs; 1048 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1049 1050 sge = (struct amr_sgentry *)((char *)amr->amr_sgls + sgloff); 1051 for (i = 0; i < nsegs; i++, sge++) { 1052 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1053 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1054 } 1055 } 1056 1057 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, dmaflag); 1058 1059 if ((ac->ac_flags & AC_NOSGL) == 0) 1060 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1061 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1062 1063 return (0); 1064 } 1065 1066 /* 1067 * Unmap the specified CCB's data buffer. 1068 */ 1069 void 1070 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1071 { 1072 int dmaflag = 0; 1073 1074 if (ac->ac_flags & AC_XFER_IN) 1075 dmaflag |= BUS_DMASYNC_POSTREAD; 1076 if (ac->ac_flags & AC_XFER_OUT) 1077 dmaflag |= BUS_DMASYNC_POSTWRITE; 1078 1079 if ((ac->ac_flags & AC_NOSGL) == 0) 1080 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1081 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1082 BUS_DMASYNC_POSTWRITE); 1083 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1084 dmaflag); 1085 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1086 } 1087 1088 /* 1089 * Submit a command to the controller and poll on completion. Return 1090 * non-zero on timeout or error. Must be called with interrupts blocked. 1091 */ 1092 int 1093 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1094 { 1095 int rv; 1096 1097 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) 1098 return (rv); 1099 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1100 1101 for (timo *= 10; timo != 0; timo--) { 1102 amr_intr(amr); 1103 if ((ac->ac_flags & AC_COMPLETE) != 0) 1104 break; 1105 DELAY(100); 1106 } 1107 1108 return (timo == 0 || ac->ac_status != 0 ? EIO : 0); 1109 } 1110 1111 /* 1112 * Submit a command to the controller and sleep on completion. Return 1113 * non-zero on error. 1114 */ 1115 int 1116 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1117 { 1118 int s; 1119 1120 s = splbio(); 1121 amr_ccb_enqueue(amr, ac); 1122 tsleep(ac, PRIBIO, "amrcmd", 0); 1123 splx(s); 1124 1125 return (ac->ac_status != 0 ? EIO : 0); 1126 } 1127 1128 #if 0 1129 /* 1130 * Wait for the mailbox to become available. 1131 */ 1132 static int 1133 amr_mbox_wait(struct amr_softc *amr) 1134 { 1135 int timo; 1136 1137 for (timo = 10000; timo != 0; timo--) { 1138 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1139 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1140 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1141 break; 1142 DELAY(100); 1143 } 1144 1145 if (timo == 0) 1146 printf("%s: controller wedged\n", device_xname(&amr->amr_dv)); 1147 1148 return (timo != 0 ? 0 : EAGAIN); 1149 } 1150 #endif 1151 1152 /* 1153 * Tell the controller that the mailbox contains a valid command. Must be 1154 * called with interrupts blocked. 1155 */ 1156 static int 1157 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1158 { 1159 u_int32_t v; 1160 1161 amr->amr_mbox->mb_poll = 0; 1162 amr->amr_mbox->mb_ack = 0; 1163 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1164 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1165 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1166 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1167 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1168 return (EAGAIN); 1169 1170 v = amr_inl(amr, AMR_QREG_IDB); 1171 if ((v & AMR_QIDB_SUBMIT) != 0) { 1172 amr->amr_mbox->mb_cmd.mb_busy = 0; 1173 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1174 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1175 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1176 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1177 return (EAGAIN); 1178 } 1179 1180 amr->amr_mbox->mb_segment = 0; 1181 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1182 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1183 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1184 1185 ac->ac_start_time = time_uptime; 1186 ac->ac_flags |= AC_ACTIVE; 1187 amr_outl(amr, AMR_QREG_IDB, 1188 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1189 return (0); 1190 } 1191 1192 static int 1193 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1194 { 1195 1196 amr->amr_mbox->mb_poll = 0; 1197 amr->amr_mbox->mb_ack = 0; 1198 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1199 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1200 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1201 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1202 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1203 return (EAGAIN); 1204 1205 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1206 amr->amr_mbox->mb_cmd.mb_busy = 0; 1207 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1208 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1209 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1210 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1211 return (EAGAIN); 1212 } 1213 1214 amr->amr_mbox->mb_segment = 0; 1215 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1216 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1217 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1218 1219 ac->ac_start_time = time_uptime; 1220 ac->ac_flags |= AC_ACTIVE; 1221 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1222 return (0); 1223 } 1224 1225 /* 1226 * Claim any work that the controller has completed; acknowledge completion, 1227 * save details of the completion in (mbsave). Must be called with 1228 * interrupts blocked. 1229 */ 1230 static int 1231 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1232 { 1233 1234 /* Work waiting for us? */ 1235 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1236 return (-1); 1237 1238 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1239 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1240 1241 /* Save the mailbox, which contains a list of completed commands. */ 1242 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1243 1244 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1245 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1246 1247 /* Ack the interrupt and mailbox transfer. */ 1248 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1249 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1250 1251 /* 1252 * This waits for the controller to notice that we've taken the 1253 * command from it. It's very inefficient, and we shouldn't do it, 1254 * but if we remove this code, we stop completing commands under 1255 * load. 1256 * 1257 * Peter J says we shouldn't do this. The documentation says we 1258 * should. Who is right? 1259 */ 1260 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1261 DELAY(10); 1262 1263 return (0); 1264 } 1265 1266 static int 1267 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1268 { 1269 u_int8_t istat; 1270 1271 /* Check for valid interrupt status. */ 1272 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1273 return (-1); 1274 1275 /* Ack the interrupt. */ 1276 amr_outb(amr, AMR_SREG_INTR, istat); 1277 1278 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1279 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1280 1281 /* Save mailbox, which contains a list of completed commands. */ 1282 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1283 1284 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1285 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1286 1287 /* Ack mailbox transfer. */ 1288 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1289 1290 return (0); 1291 } 1292 1293 static void 1294 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1295 { 1296 int i; 1297 1298 printf("%s: ", device_xname(&amr->amr_dv)); 1299 for (i = 0; i < 4; i++) 1300 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1301 printf("\n"); 1302 } 1303 1304 static int 1305 amropen(dev_t dev, int flag, int mode, struct lwp *l) 1306 { 1307 struct amr_softc *amr; 1308 1309 if ((amr = device_lookup_private(&amr_cd, minor(dev))) == NULL) 1310 return (ENXIO); 1311 if ((amr->amr_flags & AMRF_OPEN) != 0) 1312 return (EBUSY); 1313 1314 amr->amr_flags |= AMRF_OPEN; 1315 return (0); 1316 } 1317 1318 static int 1319 amrclose(dev_t dev, int flag, int mode, struct lwp *l) 1320 { 1321 struct amr_softc *amr; 1322 1323 amr = device_lookup_private(&amr_cd, minor(dev)); 1324 amr->amr_flags &= ~AMRF_OPEN; 1325 return (0); 1326 } 1327 1328 static int 1329 amrioctl(dev_t dev, u_long cmd, void *data, int flag, 1330 struct lwp *l) 1331 { 1332 struct amr_softc *amr; 1333 struct amr_user_ioctl *au; 1334 struct amr_ccb *ac; 1335 struct amr_mailbox_ioctl *mbi; 1336 unsigned long au_length; 1337 uint8_t *au_cmd; 1338 int error; 1339 void *dp = NULL, *au_buffer; 1340 1341 amr = device_lookup_private(&amr_cd, minor(dev)); 1342 1343 /* This should be compatible with the FreeBSD interface */ 1344 1345 switch (cmd) { 1346 case AMR_IO_VERSION: 1347 *(int *)data = AMR_IO_VERSION_NUMBER; 1348 return 0; 1349 case AMR_IO_COMMAND: 1350 error = kauth_authorize_device_passthru(l->l_cred, dev, 1351 KAUTH_REQ_DEVICE_RAWIO_PASSTHRU_ALL, data); 1352 if (error) 1353 return (error); 1354 1355 au = (struct amr_user_ioctl *)data; 1356 au_cmd = au->au_cmd; 1357 au_buffer = au->au_buffer; 1358 au_length = au->au_length; 1359 break; 1360 default: 1361 return ENOTTY; 1362 } 1363 1364 if (au_cmd[0] == AMR_CMD_PASS) { 1365 /* not yet */ 1366 return EOPNOTSUPP; 1367 } 1368 1369 if (au_length <= 0 || au_length > MAXPHYS || au_cmd[0] == 0x06) 1370 return (EINVAL); 1371 1372 /* 1373 * allocate kernel memory for data, doing I/O directly to user 1374 * buffer isn't that easy. 1375 */ 1376 dp = malloc(au_length, M_DEVBUF, M_WAITOK|M_ZERO); 1377 if (dp == NULL) 1378 return ENOMEM; 1379 if ((error = copyin(au_buffer, dp, au_length)) != 0) 1380 goto out; 1381 1382 /* direct command to controller */ 1383 while (amr_ccb_alloc(amr, &ac) != 0) { 1384 error = tsleep(NULL, PRIBIO | PCATCH, "armmbx", hz); 1385 if (error == EINTR) 1386 goto out; 1387 } 1388 1389 mbi = (struct amr_mailbox_ioctl *)&ac->ac_cmd; 1390 mbi->mb_command = au_cmd[0]; 1391 mbi->mb_channel = au_cmd[1]; 1392 mbi->mb_param = au_cmd[2]; 1393 mbi->mb_pad[0] = au_cmd[3]; 1394 mbi->mb_drive = au_cmd[4]; 1395 error = amr_ccb_map(amr, ac, dp, (int)au_length, 1396 AC_XFER_IN | AC_XFER_OUT); 1397 if (error == 0) { 1398 error = amr_ccb_wait(amr, ac); 1399 amr_ccb_unmap(amr, ac); 1400 if (error == 0) 1401 error = copyout(dp, au_buffer, au_length); 1402 1403 } 1404 amr_ccb_free(amr, ac); 1405 out: 1406 free(dp, M_DEVBUF); 1407 return (error); 1408 } 1409
Indexes created Sun Sep 21 20:09:37 GMT 2025