amr.c revision 1.54
1 /* $NetBSD: amr.c,v 1.54 2010/11/13 13:52:05 uebayasi Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999,2000 Michael Smith 34 * Copyright (c) 2000 BSDi 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 * 58 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 59 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 60 */ 61 62 /* 63 * Driver for AMI RAID controllers. 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.54 2010/11/13 13:52:05 uebayasi Exp $"); 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/kernel.h> 72 #include <sys/device.h> 73 #include <sys/queue.h> 74 #include <sys/proc.h> 75 #include <sys/buf.h> 76 #include <sys/malloc.h> 77 #include <sys/conf.h> 78 #include <sys/kthread.h> 79 #include <sys/kauth.h> 80 81 #include <machine/endian.h> 82 #include <sys/bus.h> 83 84 #include <dev/pci/pcidevs.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/amrreg.h> 87 #include <dev/pci/amrvar.h> 88 #include <dev/pci/amrio.h> 89 90 #include "locators.h" 91 92 static void amr_attach(device_t, device_t, void *); 93 static void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 94 static void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, 95 void *); 96 static int amr_init(struct amr_softc *, const char *, 97 struct pci_attach_args *pa); 98 static int amr_intr(void *); 99 static int amr_match(device_t, cfdata_t, void *); 100 static int amr_print(void *, const char *); 101 static void amr_shutdown(void *); 102 static void amr_teardown(struct amr_softc *); 103 static void amr_thread(void *); 104 105 static int amr_quartz_get_work(struct amr_softc *, 106 struct amr_mailbox_resp *); 107 static int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 108 static int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 109 static int amr_std_submit(struct amr_softc *, struct amr_ccb *); 110 111 static dev_type_open(amropen); 112 static dev_type_close(amrclose); 113 static dev_type_ioctl(amrioctl); 114 115 CFATTACH_DECL(amr, sizeof(struct amr_softc), 116 amr_match, amr_attach, NULL, NULL); 117 118 const struct cdevsw amr_cdevsw = { 119 amropen, amrclose, noread, nowrite, amrioctl, 120 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 121 }; 122 123 extern struct cfdriver amr_cd; 124 125 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 126 #define AT_SIG 0x02 /* Check for signature */ 127 128 static struct amr_pci_type { 129 u_short apt_vendor; 130 u_short apt_product; 131 u_short apt_flags; 132 } const amr_pci_type[] = { 133 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 134 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 135 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 136 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 140 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 141 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 142 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 143 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4ESI, AT_QUARTZ }, 144 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_PERC_4SC, AT_QUARTZ }, 145 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 146 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 147 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 148 }; 149 150 static struct amr_typestr { 151 const char *at_str; 152 int at_sig; 153 } const amr_typestr[] = { 154 { "Series 431", AMR_SIG_431 }, 155 { "Series 438", AMR_SIG_438 }, 156 { "Series 466", AMR_SIG_466 }, 157 { "Series 467", AMR_SIG_467 }, 158 { "Series 490", AMR_SIG_490 }, 159 { "Series 762", AMR_SIG_762 }, 160 { "HP NetRAID (T5)", AMR_SIG_T5 }, 161 { "HP NetRAID (T7)", AMR_SIG_T7 }, 162 }; 163 164 static struct { 165 const char *ds_descr; 166 int ds_happy; 167 } const amr_dstate[] = { 168 { "offline", 0 }, 169 { "degraded", 1 }, 170 { "optimal", 1 }, 171 { "online", 1 }, 172 { "failed", 0 }, 173 { "rebuilding", 1 }, 174 { "hotspare", 0 }, 175 }; 176 177 static void *amr_sdh; 178 179 static int amr_max_segs; 180 int amr_max_xfer; 181 182 static inline u_int8_t 183 amr_inb(struct amr_softc *amr, int off) 184 { 185 186 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 187 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 188 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 189 } 190 191 static inline u_int32_t 192 amr_inl(struct amr_softc *amr, int off) 193 { 194 195 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 196 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 197 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 198 } 199 200 static inline void 201 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 202 { 203 204 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 205 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 206 BUS_SPACE_BARRIER_WRITE); 207 } 208 209 static inline void 210 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 211 { 212 213 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 214 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 215 BUS_SPACE_BARRIER_WRITE); 216 } 217 218 /* 219 * Match a supported device. 220 */ 221 static int 222 amr_match(device_t parent, cfdata_t match, void *aux) 223 { 224 struct pci_attach_args *pa; 225 pcireg_t s; 226 int i; 227 228 pa = (struct pci_attach_args *)aux; 229 230 /* 231 * Don't match the device if it's operating in I2O mode. In this 232 * case it should be handled by the `iop' driver. 233 */ 234 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 235 return (0); 236 237 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 238 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 239 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 240 break; 241 242 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 243 return (0); 244 245 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 246 return (1); 247 248 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 249 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 250 } 251 252 /* 253 * Attach a supported device. 254 */ 255 static void 256 amr_attach(device_t parent, device_t self, void *aux) 257 { 258 struct pci_attach_args *pa; 259 struct amr_attach_args amra; 260 const struct amr_pci_type *apt; 261 struct amr_softc *amr; 262 pci_chipset_tag_t pc; 263 pci_intr_handle_t ih; 264 const char *intrstr; 265 pcireg_t reg; 266 int rseg, i, j, size, rv, memreg, ioreg; 267 struct amr_ccb *ac; 268 int locs[AMRCF_NLOCS]; 269 270 aprint_naive(": RAID controller\n"); 271 272 amr = device_private(self); 273 pa = (struct pci_attach_args *)aux; 274 pc = pa->pa_pc; 275 276 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 277 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 278 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 279 break; 280 apt = amr_pci_type + i; 281 282 memreg = ioreg = 0; 283 for (i = 0x10; i <= 0x14; i += 4) { 284 reg = pci_conf_read(pc, pa->pa_tag, i); 285 switch (PCI_MAPREG_TYPE(reg)) { 286 case PCI_MAPREG_TYPE_MEM: 287 if (PCI_MAPREG_MEM_SIZE(reg) != 0) 288 memreg = i; 289 break; 290 case PCI_MAPREG_TYPE_IO: 291 if (PCI_MAPREG_IO_SIZE(reg) != 0) 292 ioreg = i; 293 break; 294 295 } 296 } 297 298 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 299 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 300 ; 301 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 302 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 303 ; 304 else { 305 aprint_error("can't map control registers\n"); 306 amr_teardown(amr); 307 return; 308 } 309 310 amr->amr_flags |= AMRF_PCI_REGS; 311 amr->amr_dmat = pa->pa_dmat; 312 amr->amr_pc = pa->pa_pc; 313 314 /* Enable the device. */ 315 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 316 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 317 reg | PCI_COMMAND_MASTER_ENABLE); 318 319 /* Map and establish the interrupt. */ 320 if (pci_intr_map(pa, &ih)) { 321 aprint_error("can't map interrupt\n"); 322 amr_teardown(amr); 323 return; 324 } 325 intrstr = pci_intr_string(pc, ih); 326 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); 327 if (amr->amr_ih == NULL) { 328 aprint_error("can't establish interrupt"); 329 if (intrstr != NULL) 330 aprint_error(" at %s", intrstr); 331 aprint_error("\n"); 332 amr_teardown(amr); 333 return; 334 } 335 amr->amr_flags |= AMRF_PCI_INTR; 336 337 /* 338 * Allocate space for the mailbox and S/G lists. Some controllers 339 * don't like S/G lists to be located below 0x2000, so we allocate 340 * enough slop to enable us to compensate. 341 * 342 * The standard mailbox structure needs to be aligned on a 16-byte 343 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 344 * size, which precedes the standard mailbox. 345 */ 346 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 347 amr->amr_dmasize = size; 348 349 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, 350 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 351 aprint_error_dev(&amr->amr_dv, "unable to allocate buffer, rv = %d\n", 352 rv); 353 amr_teardown(amr); 354 return; 355 } 356 amr->amr_flags |= AMRF_DMA_ALLOC; 357 358 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 359 (void **)&amr->amr_mbox, 360 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 361 aprint_error_dev(&amr->amr_dv, "unable to map buffer, rv = %d\n", 362 rv); 363 amr_teardown(amr); 364 return; 365 } 366 amr->amr_flags |= AMRF_DMA_MAP; 367 368 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 369 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 370 aprint_error_dev(&amr->amr_dv, "unable to create buffer DMA map, rv = %d\n", 371 rv); 372 amr_teardown(amr); 373 return; 374 } 375 amr->amr_flags |= AMRF_DMA_CREATE; 376 377 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 378 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 379 aprint_error_dev(&amr->amr_dv, "unable to load buffer DMA map, rv = %d\n", 380 rv); 381 amr_teardown(amr); 382 return; 383 } 384 amr->amr_flags |= AMRF_DMA_LOAD; 385 386 memset(amr->amr_mbox, 0, size); 387 388 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 389 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 390 amr->amr_sgls = (struct amr_sgentry *)((char *)amr->amr_mbox + 391 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 392 393 /* 394 * Allocate and initalise the command control blocks. 395 */ 396 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); 397 amr->amr_ccbs = ac; 398 SLIST_INIT(&amr->amr_ccb_freelist); 399 TAILQ_INIT(&amr->amr_ccb_active); 400 amr->amr_flags |= AMRF_CCBS; 401 402 if (amr_max_xfer == 0) { 403 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); 404 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 405 } 406 407 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 408 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 409 amr_max_segs, amr_max_xfer, 0, 410 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 411 if (rv != 0) 412 break; 413 414 ac->ac_ident = i; 415 amr_ccb_free(amr, ac); 416 } 417 if (i != AMR_MAX_CMDS) { 418 aprint_error_dev(&amr->amr_dv, "memory exhausted\n"); 419 amr_teardown(amr); 420 return; 421 } 422 423 /* 424 * Take care of model-specific tasks. 425 */ 426 if ((apt->apt_flags & AT_QUARTZ) != 0) { 427 amr->amr_submit = amr_quartz_submit; 428 amr->amr_get_work = amr_quartz_get_work; 429 } else { 430 amr->amr_submit = amr_std_submit; 431 amr->amr_get_work = amr_std_get_work; 432 433 /* Notify the controller of the mailbox location. */ 434 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 435 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 436 437 /* Clear outstanding interrupts and enable interrupts. */ 438 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 439 amr_outb(amr, AMR_SREG_TOGL, 440 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 441 } 442 443 /* 444 * Retrieve parameters, and tell the world about us. 445 */ 446 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); 447 amr->amr_flags |= AMRF_ENQBUF; 448 amr->amr_maxqueuecnt = i; 449 aprint_normal(": AMI RAID "); 450 if (amr_init(amr, intrstr, pa) != 0) { 451 amr_teardown(amr); 452 return; 453 } 454 455 /* 456 * Cap the maximum number of outstanding commands. AMI's Linux 457 * driver doesn't trust the controller's reported value, and lockups 458 * have been seen when we do. 459 */ 460 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 461 if (amr->amr_maxqueuecnt > i) 462 amr->amr_maxqueuecnt = i; 463 464 /* Set our `shutdownhook' before we start any device activity. */ 465 if (amr_sdh == NULL) 466 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 467 468 /* Attach sub-devices. */ 469 for (j = 0; j < amr->amr_numdrives; j++) { 470 if (amr->amr_drive[j].al_size == 0) 471 continue; 472 amra.amra_unit = j; 473 474 locs[AMRCF_UNIT] = j; 475 476 amr->amr_drive[j].al_dv = config_found_sm_loc(&amr->amr_dv, 477 "amr", locs, &amra, amr_print, config_stdsubmatch); 478 } 479 480 SIMPLEQ_INIT(&amr->amr_ccb_queue); 481 482 /* XXX This doesn't work for newer boards yet. */ 483 if ((apt->apt_flags & AT_QUARTZ) == 0) { 484 rv = kthread_create(PRI_NONE, 0, NULL, amr_thread, amr, 485 &amr->amr_thread, "%s", device_xname(&amr->amr_dv)); 486 if (rv != 0) 487 aprint_error_dev(&amr->amr_dv, "unable to create thread (%d)", 488 rv); 489 else 490 amr->amr_flags |= AMRF_THREAD; 491 } 492 } 493 494 /* 495 * Free up resources. 496 */ 497 static void 498 amr_teardown(struct amr_softc *amr) 499 { 500 struct amr_ccb *ac; 501 int fl; 502 503 fl = amr->amr_flags; 504 505 if ((fl & AMRF_THREAD) != 0) { 506 amr->amr_flags |= AMRF_THREAD_EXIT; 507 wakeup(amr_thread); 508 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) 509 tsleep(&amr->amr_flags, PWAIT, "amrexit", 0); 510 } 511 if ((fl & AMRF_CCBS) != 0) { 512 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 513 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 514 } 515 free(amr->amr_ccbs, M_DEVBUF); 516 } 517 if ((fl & AMRF_ENQBUF) != 0) 518 free(amr->amr_enqbuf, M_DEVBUF); 519 if ((fl & AMRF_DMA_LOAD) != 0) 520 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 521 if ((fl & AMRF_DMA_MAP) != 0) 522 bus_dmamem_unmap(amr->amr_dmat, (void *)amr->amr_mbox, 523 amr->amr_dmasize); 524 if ((fl & AMRF_DMA_ALLOC) != 0) 525 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 526 if ((fl & AMRF_DMA_CREATE) != 0) 527 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 528 if ((fl & AMRF_PCI_INTR) != 0) 529 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 530 if ((fl & AMRF_PCI_REGS) != 0) 531 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 532 } 533 534 /* 535 * Print autoconfiguration message for a sub-device. 536 */ 537 static int 538 amr_print(void *aux, const char *pnp) 539 { 540 struct amr_attach_args *amra; 541 542 amra = (struct amr_attach_args *)aux; 543 544 if (pnp != NULL) 545 aprint_normal("block device at %s", pnp); 546 aprint_normal(" unit %d", amra->amra_unit); 547 return (UNCONF); 548 } 549 550 /* 551 * Retrieve operational parameters and describe the controller. 552 */ 553 static int 554 amr_init(struct amr_softc *amr, const char *intrstr, 555 struct pci_attach_args *pa) 556 { 557 struct amr_adapter_info *aa; 558 struct amr_prodinfo *ap; 559 struct amr_enquiry *ae; 560 struct amr_enquiry3 *aex; 561 const char *prodstr; 562 u_int i, sig, ishp; 563 char sbuf[64]; 564 565 /* 566 * Try to get 40LD product info, which tells us what the card is 567 * labelled as. 568 */ 569 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 570 amr->amr_enqbuf); 571 if (ap != NULL) { 572 aprint_normal("<%.80s>\n", ap->ap_product); 573 if (intrstr != NULL) 574 aprint_normal_dev(&amr->amr_dv, "interrupting at %s\n", 575 intrstr); 576 aprint_normal_dev(&amr->amr_dv, "firmware %.16s, BIOS %.16s, %dMB RAM\n", 577 ap->ap_firmware, ap->ap_bios, 578 le16toh(ap->ap_memsize)); 579 580 amr->amr_maxqueuecnt = ap->ap_maxio; 581 582 /* 583 * Fetch and record state of logical drives. 584 */ 585 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 586 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 587 if (aex == NULL) { 588 aprint_error_dev(&amr->amr_dv, "ENQUIRY3 failed\n"); 589 return (-1); 590 } 591 592 if (aex->ae_numldrives > __arraycount(aex->ae_drivestate)) { 593 aprint_error_dev(&amr->amr_dv, "Inquiry returned more drives (%d)" 594 " than the array can handle (%zu)\n", 595 aex->ae_numldrives, 596 __arraycount(aex->ae_drivestate)); 597 aex->ae_numldrives = __arraycount(aex->ae_drivestate); 598 } 599 if (aex->ae_numldrives > AMR_MAX_UNITS) { 600 aprint_error_dev(&amr->amr_dv, 601 "adjust AMR_MAX_UNITS to %d (currently %d)" 602 "\n", AMR_MAX_UNITS, 603 amr->amr_numdrives); 604 amr->amr_numdrives = AMR_MAX_UNITS; 605 } else 606 amr->amr_numdrives = aex->ae_numldrives; 607 608 for (i = 0; i < amr->amr_numdrives; i++) { 609 amr->amr_drive[i].al_size = 610 le32toh(aex->ae_drivesize[i]); 611 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 612 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 613 } 614 615 return (0); 616 } 617 618 /* 619 * Try 8LD extended ENQUIRY to get the controller signature. Once 620 * found, search for a product description. 621 */ 622 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 623 if (ae != NULL) { 624 i = 0; 625 sig = le32toh(ae->ae_signature); 626 627 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 628 if (amr_typestr[i].at_sig == sig) 629 break; 630 i++; 631 } 632 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 633 snprintf(sbuf, sizeof(sbuf), 634 "unknown ENQUIRY2 sig (0x%08x)", sig); 635 prodstr = sbuf; 636 } else 637 prodstr = amr_typestr[i].at_str; 638 } else { 639 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 640 if (ae == NULL) { 641 aprint_error_dev(&amr->amr_dv, "unsupported controller\n"); 642 return (-1); 643 } 644 645 switch (PCI_PRODUCT(pa->pa_id)) { 646 case PCI_PRODUCT_AMI_MEGARAID: 647 prodstr = "Series 428"; 648 break; 649 case PCI_PRODUCT_AMI_MEGARAID2: 650 prodstr = "Series 434"; 651 break; 652 default: 653 snprintf(sbuf, sizeof(sbuf), "unknown PCI dev (0x%04x)", 654 PCI_PRODUCT(pa->pa_id)); 655 prodstr = sbuf; 656 break; 657 } 658 } 659 660 /* 661 * HP NetRaid controllers have a special encoding of the firmware 662 * and BIOS versions. The AMI version seems to have it as strings 663 * whereas the HP version does it with a leading uppercase character 664 * and two binary numbers. 665 */ 666 aa = &ae->ae_adapter; 667 668 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 669 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 670 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 671 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 672 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 673 /* The AMI 438 is a NetRaid 3si in HP-land. */ 674 prodstr = "HP NetRaid 3si"; 675 } 676 ishp = 1; 677 } else 678 ishp = 0; 679 680 aprint_normal("<%s>\n", prodstr); 681 if (intrstr != NULL) 682 aprint_normal_dev(&amr->amr_dv, "interrupting at %s\n", 683 intrstr); 684 685 if (ishp) 686 aprint_normal_dev(&amr->amr_dv, "firmware <%c.%02d.%02d>, BIOS <%c.%02d.%02d>" 687 ", %dMB RAM\n", aa->aa_firmware[2], 688 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 689 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 690 else 691 aprint_normal_dev(&amr->amr_dv, "firmware <%.4s>, BIOS <%.4s>, %dMB RAM\n", 692 aa->aa_firmware, aa->aa_bios, 693 aa->aa_memorysize); 694 695 amr->amr_maxqueuecnt = aa->aa_maxio; 696 697 /* 698 * Record state of logical drives. 699 */ 700 if (ae->ae_ldrv.al_numdrives > __arraycount(ae->ae_ldrv.al_size)) { 701 aprint_error_dev(&amr->amr_dv, "Inquiry returned more drives (%d)" 702 " than the array can handle (%zu)\n", 703 ae->ae_ldrv.al_numdrives, 704 __arraycount(ae->ae_ldrv.al_size)); 705 ae->ae_ldrv.al_numdrives = __arraycount(ae->ae_ldrv.al_size); 706 } 707 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 708 aprint_error_dev(&amr->amr_dv, "adjust AMR_MAX_UNITS to %d (currently %d)\n", 709 ae->ae_ldrv.al_numdrives, 710 AMR_MAX_UNITS); 711 amr->amr_numdrives = AMR_MAX_UNITS; 712 } else 713 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 714 715 for (i = 0; i < amr->amr_numdrives; i++) { 716 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 717 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 718 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 719 } 720 721 return (0); 722 } 723 724 /* 725 * Flush the internal cache on each configured controller. Called at 726 * shutdown time. 727 */ 728 static void 729 amr_shutdown(void *cookie) 730 { 731 extern struct cfdriver amr_cd; 732 struct amr_softc *amr; 733 struct amr_ccb *ac; 734 int i, rv, s; 735 736 for (i = 0; i < amr_cd.cd_ndevs; i++) { 737 if ((amr = device_lookup_private(&amr_cd, i)) == NULL) 738 continue; 739 740 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 741 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 742 s = splbio(); 743 rv = amr_ccb_poll(amr, ac, 30000); 744 splx(s); 745 amr_ccb_free(amr, ac); 746 } 747 if (rv != 0) 748 aprint_error_dev(&amr->amr_dv, "unable to flush cache (%d)\n", rv); 749 } 750 } 751 752 /* 753 * Interrupt service routine. 754 */ 755 static int 756 amr_intr(void *cookie) 757 { 758 struct amr_softc *amr; 759 struct amr_ccb *ac; 760 struct amr_mailbox_resp mbox; 761 u_int i, forus, idx; 762 763 amr = cookie; 764 forus = 0; 765 766 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 767 /* Iterate over completed commands in this result. */ 768 for (i = 0; i < mbox.mb_nstatus; i++) { 769 idx = mbox.mb_completed[i] - 1; 770 ac = amr->amr_ccbs + idx; 771 772 if (idx >= amr->amr_maxqueuecnt) { 773 printf("%s: bad status (bogus ID: %u=%u)\n", 774 device_xname(&amr->amr_dv), i, idx); 775 continue; 776 } 777 778 if ((ac->ac_flags & AC_ACTIVE) == 0) { 779 printf("%s: bad status (not active; 0x04%x)\n", 780 device_xname(&amr->amr_dv), ac->ac_flags); 781 continue; 782 } 783 784 ac->ac_status = mbox.mb_status; 785 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 786 AC_COMPLETE; 787 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 788 789 if ((ac->ac_flags & AC_MOAN) != 0) 790 printf("%s: ccb %d completed\n", 791 device_xname(&amr->amr_dv), ac->ac_ident); 792 793 /* Pass notification to upper layers. */ 794 if (ac->ac_handler != NULL) 795 (*ac->ac_handler)(ac); 796 else 797 wakeup(ac); 798 } 799 forus = 1; 800 } 801 802 if (forus) 803 amr_ccb_enqueue(amr, NULL); 804 805 return (forus); 806 } 807 808 /* 809 * Watchdog thread. 810 */ 811 static void 812 amr_thread(void *cookie) 813 { 814 struct amr_softc *amr; 815 struct amr_ccb *ac; 816 struct amr_logdrive *al; 817 struct amr_enquiry *ae; 818 int rv, i, s; 819 820 amr = cookie; 821 ae = amr->amr_enqbuf; 822 823 for (;;) { 824 tsleep(amr_thread, PWAIT, "amrwdog", AMR_WDOG_TICKS); 825 826 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 827 amr->amr_flags ^= AMRF_THREAD_EXIT; 828 wakeup(&amr->amr_flags); 829 kthread_exit(0); 830 } 831 832 s = splbio(); 833 amr_intr(cookie); 834 ac = TAILQ_FIRST(&amr->amr_ccb_active); 835 while (ac != NULL) { 836 if (ac->ac_start_time + AMR_TIMEOUT > time_uptime) 837 break; 838 if ((ac->ac_flags & AC_MOAN) == 0) { 839 printf("%s: ccb %d timed out; mailbox:\n", 840 device_xname(&amr->amr_dv), ac->ac_ident); 841 amr_ccb_dump(amr, ac); 842 ac->ac_flags |= AC_MOAN; 843 } 844 ac = TAILQ_NEXT(ac, ac_chain.tailq); 845 } 846 splx(s); 847 848 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 849 printf("%s: ccb_alloc failed (%d)\n", 850 device_xname(&amr->amr_dv), rv); 851 continue; 852 } 853 854 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 855 856 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 857 AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 858 if (rv != 0) { 859 aprint_error_dev(&amr->amr_dv, "ccb_map failed (%d)\n", 860 rv); 861 amr_ccb_free(amr, ac); 862 continue; 863 } 864 865 rv = amr_ccb_wait(amr, ac); 866 amr_ccb_unmap(amr, ac); 867 if (rv != 0) { 868 aprint_error_dev(&amr->amr_dv, "enquiry failed (st=%d)\n", 869 ac->ac_status); 870 continue; 871 } 872 amr_ccb_free(amr, ac); 873 874 al = amr->amr_drive; 875 for (i = 0; i < __arraycount(ae->ae_ldrv.al_state); i++, al++) { 876 if (al->al_dv == NULL) 877 continue; 878 if (al->al_state == ae->ae_ldrv.al_state[i]) 879 continue; 880 881 printf("%s: state changed: %s -> %s\n", 882 device_xname(al->al_dv), 883 amr_drive_state(al->al_state, NULL), 884 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 885 886 al->al_state = ae->ae_ldrv.al_state[i]; 887 } 888 } 889 } 890 891 /* 892 * Return a text description of a logical drive's current state. 893 */ 894 const char * 895 amr_drive_state(int state, int *happy) 896 { 897 const char *str; 898 899 state = AMR_DRV_CURSTATE(state); 900 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 901 if (happy) 902 *happy = 1; 903 str = "status unknown"; 904 } else { 905 if (happy) 906 *happy = amr_dstate[state].ds_happy; 907 str = amr_dstate[state].ds_descr; 908 } 909 910 return (str); 911 } 912 913 /* 914 * Run a generic enquiry-style command. 915 */ 916 static void * 917 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 918 u_int8_t cmdqual, void *sbuf) 919 { 920 struct amr_ccb *ac; 921 u_int8_t *mb; 922 int rv; 923 924 if (amr_ccb_alloc(amr, &ac) != 0) 925 return (NULL); 926 927 /* Build the command proper. */ 928 mb = (u_int8_t *)&ac->ac_cmd; 929 mb[0] = cmd; 930 mb[2] = cmdsub; 931 mb[3] = cmdqual; 932 933 rv = amr_ccb_map(amr, ac, sbuf, AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 934 if (rv == 0) { 935 rv = amr_ccb_poll(amr, ac, 2000); 936 amr_ccb_unmap(amr, ac); 937 } 938 amr_ccb_free(amr, ac); 939 940 return (rv ? NULL : sbuf); 941 } 942 943 /* 944 * Allocate and initialise a CCB. 945 */ 946 int 947 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 948 { 949 int s; 950 951 s = splbio(); 952 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 953 splx(s); 954 return (EAGAIN); 955 } 956 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 957 splx(s); 958 959 return (0); 960 } 961 962 /* 963 * Free a CCB. 964 */ 965 void 966 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 967 { 968 int s; 969 970 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 971 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 972 ac->ac_cmd.mb_busy = 1; 973 ac->ac_handler = NULL; 974 ac->ac_flags = 0; 975 976 s = splbio(); 977 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 978 splx(s); 979 } 980 981 /* 982 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 983 * the order that they were enqueued and try to submit their command blocks 984 * to the controller for execution. 985 */ 986 void 987 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 988 { 989 int s; 990 991 s = splbio(); 992 993 if (ac != NULL) 994 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 995 996 while ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 997 if ((*amr->amr_submit)(amr, ac) != 0) 998 break; 999 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, ac_chain.simpleq); 1000 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1001 } 1002 1003 splx(s); 1004 } 1005 1006 /* 1007 * Map the specified CCB's data buffer onto the bus, and fill the 1008 * scatter-gather list. 1009 */ 1010 int 1011 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1012 int tflag) 1013 { 1014 struct amr_sgentry *sge; 1015 struct amr_mailbox_cmd *mb; 1016 int nsegs, i, rv, sgloff; 1017 bus_dmamap_t xfer; 1018 int dmaflag = 0; 1019 1020 xfer = ac->ac_xfer_map; 1021 1022 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1023 BUS_DMA_NOWAIT); 1024 if (rv != 0) 1025 return (rv); 1026 1027 mb = &ac->ac_cmd; 1028 ac->ac_xfer_size = size; 1029 ac->ac_flags |= (tflag & (AC_XFER_OUT | AC_XFER_IN)); 1030 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1031 1032 if (tflag & AC_XFER_OUT) 1033 dmaflag |= BUS_DMASYNC_PREWRITE; 1034 if (tflag & AC_XFER_IN) 1035 dmaflag |= BUS_DMASYNC_PREREAD; 1036 1037 /* We don't need to use a scatter/gather list for just 1 segment. */ 1038 nsegs = xfer->dm_nsegs; 1039 if (nsegs == 1) { 1040 mb->mb_nsgelem = 0; 1041 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1042 ac->ac_flags |= AC_NOSGL; 1043 } else { 1044 mb->mb_nsgelem = nsegs; 1045 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1046 1047 sge = (struct amr_sgentry *)((char *)amr->amr_sgls + sgloff); 1048 for (i = 0; i < nsegs; i++, sge++) { 1049 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1050 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1051 } 1052 } 1053 1054 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, dmaflag); 1055 1056 if ((ac->ac_flags & AC_NOSGL) == 0) 1057 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1058 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1059 1060 return (0); 1061 } 1062 1063 /* 1064 * Unmap the specified CCB's data buffer. 1065 */ 1066 void 1067 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1068 { 1069 int dmaflag = 0; 1070 1071 if (ac->ac_flags & AC_XFER_IN) 1072 dmaflag |= BUS_DMASYNC_POSTREAD; 1073 if (ac->ac_flags & AC_XFER_OUT) 1074 dmaflag |= BUS_DMASYNC_POSTWRITE; 1075 1076 if ((ac->ac_flags & AC_NOSGL) == 0) 1077 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1078 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1079 BUS_DMASYNC_POSTWRITE); 1080 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1081 dmaflag); 1082 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1083 } 1084 1085 /* 1086 * Submit a command to the controller and poll on completion. Return 1087 * non-zero on timeout or error. Must be called with interrupts blocked. 1088 */ 1089 int 1090 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1091 { 1092 int rv; 1093 1094 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) 1095 return (rv); 1096 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1097 1098 for (timo *= 10; timo != 0; timo--) { 1099 amr_intr(amr); 1100 if ((ac->ac_flags & AC_COMPLETE) != 0) 1101 break; 1102 DELAY(100); 1103 } 1104 1105 return (timo == 0 || ac->ac_status != 0 ? EIO : 0); 1106 } 1107 1108 /* 1109 * Submit a command to the controller and sleep on completion. Return 1110 * non-zero on error. 1111 */ 1112 int 1113 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1114 { 1115 int s; 1116 1117 s = splbio(); 1118 amr_ccb_enqueue(amr, ac); 1119 tsleep(ac, PRIBIO, "amrcmd", 0); 1120 splx(s); 1121 1122 return (ac->ac_status != 0 ? EIO : 0); 1123 } 1124 1125 #if 0 1126 /* 1127 * Wait for the mailbox to become available. 1128 */ 1129 static int 1130 amr_mbox_wait(struct amr_softc *amr) 1131 { 1132 int timo; 1133 1134 for (timo = 10000; timo != 0; timo--) { 1135 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1136 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1137 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1138 break; 1139 DELAY(100); 1140 } 1141 1142 if (timo == 0) 1143 printf("%s: controller wedged\n", device_xname(&amr->amr_dv)); 1144 1145 return (timo != 0 ? 0 : EAGAIN); 1146 } 1147 #endif 1148 1149 /* 1150 * Tell the controller that the mailbox contains a valid command. Must be 1151 * called with interrupts blocked. 1152 */ 1153 static int 1154 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1155 { 1156 u_int32_t v; 1157 1158 amr->amr_mbox->mb_poll = 0; 1159 amr->amr_mbox->mb_ack = 0; 1160 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1161 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1162 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1163 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1164 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1165 return (EAGAIN); 1166 1167 v = amr_inl(amr, AMR_QREG_IDB); 1168 if ((v & AMR_QIDB_SUBMIT) != 0) { 1169 amr->amr_mbox->mb_cmd.mb_busy = 0; 1170 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1171 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1172 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1173 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1174 return (EAGAIN); 1175 } 1176 1177 amr->amr_mbox->mb_segment = 0; 1178 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1179 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1180 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1181 1182 ac->ac_start_time = time_uptime; 1183 ac->ac_flags |= AC_ACTIVE; 1184 amr_outl(amr, AMR_QREG_IDB, 1185 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1186 return (0); 1187 } 1188 1189 static int 1190 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1191 { 1192 1193 amr->amr_mbox->mb_poll = 0; 1194 amr->amr_mbox->mb_ack = 0; 1195 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1196 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1197 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1198 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1199 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1200 return (EAGAIN); 1201 1202 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1203 amr->amr_mbox->mb_cmd.mb_busy = 0; 1204 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1205 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1206 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1207 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1208 return (EAGAIN); 1209 } 1210 1211 amr->amr_mbox->mb_segment = 0; 1212 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1213 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1214 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1215 1216 ac->ac_start_time = time_uptime; 1217 ac->ac_flags |= AC_ACTIVE; 1218 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1219 return (0); 1220 } 1221 1222 /* 1223 * Claim any work that the controller has completed; acknowledge completion, 1224 * save details of the completion in (mbsave). Must be called with 1225 * interrupts blocked. 1226 */ 1227 static int 1228 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1229 { 1230 1231 /* Work waiting for us? */ 1232 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1233 return (-1); 1234 1235 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1236 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1237 1238 /* Save the mailbox, which contains a list of completed commands. */ 1239 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1240 1241 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1242 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1243 1244 /* Ack the interrupt and mailbox transfer. */ 1245 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1246 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1247 1248 /* 1249 * This waits for the controller to notice that we've taken the 1250 * command from it. It's very inefficient, and we shouldn't do it, 1251 * but if we remove this code, we stop completing commands under 1252 * load. 1253 * 1254 * Peter J says we shouldn't do this. The documentation says we 1255 * should. Who is right? 1256 */ 1257 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1258 DELAY(10); 1259 1260 return (0); 1261 } 1262 1263 static int 1264 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1265 { 1266 u_int8_t istat; 1267 1268 /* Check for valid interrupt status. */ 1269 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1270 return (-1); 1271 1272 /* Ack the interrupt. */ 1273 amr_outb(amr, AMR_SREG_INTR, istat); 1274 1275 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1276 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1277 1278 /* Save mailbox, which contains a list of completed commands. */ 1279 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1280 1281 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1282 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1283 1284 /* Ack mailbox transfer. */ 1285 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1286 1287 return (0); 1288 } 1289 1290 static void 1291 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1292 { 1293 int i; 1294 1295 printf("%s: ", device_xname(&amr->amr_dv)); 1296 for (i = 0; i < 4; i++) 1297 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1298 printf("\n"); 1299 } 1300 1301 static int 1302 amropen(dev_t dev, int flag, int mode, struct lwp *l) 1303 { 1304 struct amr_softc *amr; 1305 1306 if ((amr = device_lookup_private(&amr_cd, minor(dev))) == NULL) 1307 return (ENXIO); 1308 if ((amr->amr_flags & AMRF_OPEN) != 0) 1309 return (EBUSY); 1310 1311 amr->amr_flags |= AMRF_OPEN; 1312 return (0); 1313 } 1314 1315 static int 1316 amrclose(dev_t dev, int flag, int mode, struct lwp *l) 1317 { 1318 struct amr_softc *amr; 1319 1320 amr = device_lookup_private(&amr_cd, minor(dev)); 1321 amr->amr_flags &= ~AMRF_OPEN; 1322 return (0); 1323 } 1324 1325 static int 1326 amrioctl(dev_t dev, u_long cmd, void *data, int flag, 1327 struct lwp *l) 1328 { 1329 struct amr_softc *amr; 1330 struct amr_user_ioctl *au; 1331 struct amr_ccb *ac; 1332 struct amr_mailbox_ioctl *mbi; 1333 unsigned long au_length; 1334 uint8_t *au_cmd; 1335 int error; 1336 void *dp = NULL, *au_buffer; 1337 1338 amr = device_lookup_private(&amr_cd, minor(dev)); 1339 1340 /* This should be compatible with the FreeBSD interface */ 1341 1342 switch (cmd) { 1343 case AMR_IO_VERSION: 1344 *(int *)data = AMR_IO_VERSION_NUMBER; 1345 return 0; 1346 case AMR_IO_COMMAND: 1347 error = kauth_authorize_device_passthru(l->l_cred, dev, 1348 KAUTH_REQ_DEVICE_RAWIO_PASSTHRU_ALL, data); 1349 if (error) 1350 return (error); 1351 1352 au = (struct amr_user_ioctl *)data; 1353 au_cmd = au->au_cmd; 1354 au_buffer = au->au_buffer; 1355 au_length = au->au_length; 1356 break; 1357 default: 1358 return ENOTTY; 1359 } 1360 1361 if (au_cmd[0] == AMR_CMD_PASS) { 1362 /* not yet */ 1363 return EOPNOTSUPP; 1364 } 1365 1366 if (au_length <= 0 || au_length > MAXPHYS || au_cmd[0] == 0x06) 1367 return (EINVAL); 1368 1369 /* 1370 * allocate kernel memory for data, doing I/O directly to user 1371 * buffer isn't that easy. 1372 */ 1373 dp = malloc(au_length, M_DEVBUF, M_WAITOK|M_ZERO); 1374 if (dp == NULL) 1375 return ENOMEM; 1376 if ((error = copyin(au_buffer, dp, au_length)) != 0) 1377 goto out; 1378 1379 /* direct command to controller */ 1380 while (amr_ccb_alloc(amr, &ac) != 0) { 1381 error = tsleep(NULL, PRIBIO | PCATCH, "armmbx", hz); 1382 if (error == EINTR) 1383 goto out; 1384 } 1385 1386 mbi = (struct amr_mailbox_ioctl *)&ac->ac_cmd; 1387 mbi->mb_command = au_cmd[0]; 1388 mbi->mb_channel = au_cmd[1]; 1389 mbi->mb_param = au_cmd[2]; 1390 mbi->mb_pad[0] = au_cmd[3]; 1391 mbi->mb_drive = au_cmd[4]; 1392 error = amr_ccb_map(amr, ac, dp, (int)au_length, 1393 AC_XFER_IN | AC_XFER_OUT); 1394 if (error == 0) { 1395 error = amr_ccb_wait(amr, ac); 1396 amr_ccb_unmap(amr, ac); 1397 if (error == 0) 1398 error = copyout(dp, au_buffer, au_length); 1399 1400 } 1401 amr_ccb_free(amr, ac); 1402 out: 1403 free(dp, M_DEVBUF); 1404 return (error); 1405 } 1406
Indexes created Thu Oct 02 14:10:14 GMT 2025