amr.c revision 1.55.2.2
1 /* $NetBSD: amr.c,v 1.55.2.2 2014/08/20 00:03:41 tls Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999,2000 Michael Smith 34 * Copyright (c) 2000 BSDi 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 * 58 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 59 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 60 */ 61 62 /* 63 * Driver for AMI RAID controllers. 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.55.2.2 2014/08/20 00:03:41 tls Exp $"); 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/kernel.h> 72 #include <sys/device.h> 73 #include <sys/queue.h> 74 #include <sys/proc.h> 75 #include <sys/buf.h> 76 #include <sys/malloc.h> 77 #include <sys/conf.h> 78 #include <sys/kthread.h> 79 #include <sys/kauth.h> 80 81 #include <machine/endian.h> 82 #include <sys/bus.h> 83 84 #include <dev/pci/pcidevs.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/amrreg.h> 87 #include <dev/pci/amrvar.h> 88 #include <dev/pci/amrio.h> 89 90 #include "locators.h" 91 92 static void amr_attach(device_t, device_t, void *); 93 static void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 94 static void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, 95 void *); 96 static int amr_init(struct amr_softc *, const char *, 97 struct pci_attach_args *pa); 98 static int amr_intr(void *); 99 static int amr_match(device_t, cfdata_t, void *); 100 static int amr_print(void *, const char *); 101 static void amr_shutdown(void *); 102 static void amr_teardown(struct amr_softc *); 103 static void amr_thread(void *); 104 105 static int amr_quartz_get_work(struct amr_softc *, 106 struct amr_mailbox_resp *); 107 static int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 108 static int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 109 static int amr_std_submit(struct amr_softc *, struct amr_ccb *); 110 111 static dev_type_open(amropen); 112 static dev_type_close(amrclose); 113 static dev_type_ioctl(amrioctl); 114 115 CFATTACH_DECL_NEW(amr, sizeof(struct amr_softc), 116 amr_match, amr_attach, NULL, NULL); 117 118 const struct cdevsw amr_cdevsw = { 119 .d_open = amropen, 120 .d_close = amrclose, 121 .d_read = noread, 122 .d_write = nowrite, 123 .d_ioctl = amrioctl, 124 .d_stop = nostop, 125 .d_tty = notty, 126 .d_poll = nopoll, 127 .d_mmap = nommap, 128 .d_kqfilter = nokqfilter, 129 .d_discard = nodiscard, 130 .d_flag = D_OTHER 131 }; 132 133 extern struct cfdriver amr_cd; 134 135 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 136 #define AT_SIG 0x02 /* Check for signature */ 137 138 static struct amr_pci_type { 139 u_short apt_vendor; 140 u_short apt_product; 141 u_short apt_flags; 142 } const amr_pci_type[] = { 143 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 144 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 145 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 146 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 150 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 151 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 152 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 153 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4ESI, AT_QUARTZ }, 154 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_PERC_4SC, AT_QUARTZ }, 155 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 156 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 157 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 158 }; 159 160 static struct amr_typestr { 161 const char *at_str; 162 int at_sig; 163 } const amr_typestr[] = { 164 { "Series 431", AMR_SIG_431 }, 165 { "Series 438", AMR_SIG_438 }, 166 { "Series 466", AMR_SIG_466 }, 167 { "Series 467", AMR_SIG_467 }, 168 { "Series 490", AMR_SIG_490 }, 169 { "Series 762", AMR_SIG_762 }, 170 { "HP NetRAID (T5)", AMR_SIG_T5 }, 171 { "HP NetRAID (T7)", AMR_SIG_T7 }, 172 }; 173 174 static struct { 175 const char *ds_descr; 176 int ds_happy; 177 } const amr_dstate[] = { 178 { "offline", 0 }, 179 { "degraded", 1 }, 180 { "optimal", 1 }, 181 { "online", 1 }, 182 { "failed", 0 }, 183 { "rebuilding", 1 }, 184 { "hotspare", 0 }, 185 }; 186 187 static void *amr_sdh; 188 189 static int amr_max_segs; 190 int amr_max_xfer; 191 192 static inline u_int8_t 193 amr_inb(struct amr_softc *amr, int off) 194 { 195 196 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 197 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 198 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 199 } 200 201 static inline u_int32_t 202 amr_inl(struct amr_softc *amr, int off) 203 { 204 205 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 206 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 207 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 208 } 209 210 static inline void 211 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 212 { 213 214 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 215 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 216 BUS_SPACE_BARRIER_WRITE); 217 } 218 219 static inline void 220 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 221 { 222 223 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 224 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 225 BUS_SPACE_BARRIER_WRITE); 226 } 227 228 /* 229 * Match a supported device. 230 */ 231 static int 232 amr_match(device_t parent, cfdata_t match, void *aux) 233 { 234 struct pci_attach_args *pa; 235 pcireg_t s; 236 int i; 237 238 pa = (struct pci_attach_args *)aux; 239 240 /* 241 * Don't match the device if it's operating in I2O mode. In this 242 * case it should be handled by the `iop' driver. 243 */ 244 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 245 return (0); 246 247 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 248 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 249 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 250 break; 251 252 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 253 return (0); 254 255 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 256 return (1); 257 258 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 259 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 260 } 261 262 /* 263 * Attach a supported device. 264 */ 265 static void 266 amr_attach(device_t parent, device_t self, void *aux) 267 { 268 struct pci_attach_args *pa; 269 struct amr_attach_args amra; 270 const struct amr_pci_type *apt; 271 struct amr_softc *amr; 272 pci_chipset_tag_t pc; 273 pci_intr_handle_t ih; 274 const char *intrstr; 275 pcireg_t reg; 276 int rseg, i, j, size, rv, memreg, ioreg; 277 struct amr_ccb *ac; 278 int locs[AMRCF_NLOCS]; 279 char intrbuf[PCI_INTRSTR_LEN]; 280 281 aprint_naive(": RAID controller\n"); 282 283 amr = device_private(self); 284 amr->amr_dv = self; 285 pa = (struct pci_attach_args *)aux; 286 pc = pa->pa_pc; 287 288 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 289 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 290 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 291 break; 292 apt = amr_pci_type + i; 293 294 memreg = ioreg = 0; 295 for (i = 0x10; i <= 0x14; i += 4) { 296 reg = pci_conf_read(pc, pa->pa_tag, i); 297 switch (PCI_MAPREG_TYPE(reg)) { 298 case PCI_MAPREG_TYPE_MEM: 299 if (PCI_MAPREG_MEM_SIZE(reg) != 0) 300 memreg = i; 301 break; 302 case PCI_MAPREG_TYPE_IO: 303 if (PCI_MAPREG_IO_SIZE(reg) != 0) 304 ioreg = i; 305 break; 306 307 } 308 } 309 310 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 311 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 312 ; 313 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 314 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 315 ; 316 else { 317 aprint_error("can't map control registers\n"); 318 amr_teardown(amr); 319 return; 320 } 321 322 amr->amr_flags |= AMRF_PCI_REGS; 323 amr->amr_dmat = pa->pa_dmat; 324 amr->amr_pc = pa->pa_pc; 325 326 /* Enable the device. */ 327 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 328 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 329 reg | PCI_COMMAND_MASTER_ENABLE); 330 331 /* Map and establish the interrupt. */ 332 if (pci_intr_map(pa, &ih)) { 333 aprint_error("can't map interrupt\n"); 334 amr_teardown(amr); 335 return; 336 } 337 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 338 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); 339 if (amr->amr_ih == NULL) { 340 aprint_error("can't establish interrupt"); 341 if (intrstr != NULL) 342 aprint_error(" at %s", intrstr); 343 aprint_error("\n"); 344 amr_teardown(amr); 345 return; 346 } 347 amr->amr_flags |= AMRF_PCI_INTR; 348 349 /* 350 * Allocate space for the mailbox and S/G lists. Some controllers 351 * don't like S/G lists to be located below 0x2000, so we allocate 352 * enough slop to enable us to compensate. 353 * 354 * The standard mailbox structure needs to be aligned on a 16-byte 355 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 356 * size, which precedes the standard mailbox. 357 */ 358 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 359 amr->amr_dmasize = size; 360 361 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, 362 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 363 aprint_error_dev(amr->amr_dv, "unable to allocate buffer, rv = %d\n", 364 rv); 365 amr_teardown(amr); 366 return; 367 } 368 amr->amr_flags |= AMRF_DMA_ALLOC; 369 370 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 371 (void **)&amr->amr_mbox, 372 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 373 aprint_error_dev(amr->amr_dv, "unable to map buffer, rv = %d\n", 374 rv); 375 amr_teardown(amr); 376 return; 377 } 378 amr->amr_flags |= AMRF_DMA_MAP; 379 380 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 381 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 382 aprint_error_dev(amr->amr_dv, "unable to create buffer DMA map, rv = %d\n", 383 rv); 384 amr_teardown(amr); 385 return; 386 } 387 amr->amr_flags |= AMRF_DMA_CREATE; 388 389 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 390 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 391 aprint_error_dev(amr->amr_dv, "unable to load buffer DMA map, rv = %d\n", 392 rv); 393 amr_teardown(amr); 394 return; 395 } 396 amr->amr_flags |= AMRF_DMA_LOAD; 397 398 memset(amr->amr_mbox, 0, size); 399 400 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 401 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 402 amr->amr_sgls = (struct amr_sgentry *)((char *)amr->amr_mbox + 403 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 404 405 /* 406 * Allocate and initalise the command control blocks. 407 */ 408 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); 409 amr->amr_ccbs = ac; 410 SLIST_INIT(&amr->amr_ccb_freelist); 411 TAILQ_INIT(&amr->amr_ccb_active); 412 amr->amr_flags |= AMRF_CCBS; 413 414 if (amr_max_xfer == 0) { 415 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), 416 device_maxphys(amr->amr_dv)); 417 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 418 } 419 amr->amr_dv->dv_maxphys = amr_max_xfer; 420 421 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 422 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 423 amr_max_segs, amr_max_xfer, 0, 424 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 425 if (rv != 0) 426 break; 427 428 ac->ac_ident = i; 429 amr_ccb_free(amr, ac); 430 } 431 if (i != AMR_MAX_CMDS) { 432 aprint_error_dev(amr->amr_dv, "memory exhausted\n"); 433 amr_teardown(amr); 434 return; 435 } 436 437 /* 438 * Take care of model-specific tasks. 439 */ 440 if ((apt->apt_flags & AT_QUARTZ) != 0) { 441 amr->amr_submit = amr_quartz_submit; 442 amr->amr_get_work = amr_quartz_get_work; 443 } else { 444 amr->amr_submit = amr_std_submit; 445 amr->amr_get_work = amr_std_get_work; 446 447 /* Notify the controller of the mailbox location. */ 448 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 449 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 450 451 /* Clear outstanding interrupts and enable interrupts. */ 452 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 453 amr_outb(amr, AMR_SREG_TOGL, 454 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 455 } 456 457 /* 458 * Retrieve parameters, and tell the world about us. 459 */ 460 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); 461 amr->amr_flags |= AMRF_ENQBUF; 462 amr->amr_maxqueuecnt = i; 463 aprint_normal(": AMI RAID "); 464 if (amr_init(amr, intrstr, pa) != 0) { 465 amr_teardown(amr); 466 return; 467 } 468 469 /* 470 * Cap the maximum number of outstanding commands. AMI's Linux 471 * driver doesn't trust the controller's reported value, and lockups 472 * have been seen when we do. 473 */ 474 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 475 if (amr->amr_maxqueuecnt > i) 476 amr->amr_maxqueuecnt = i; 477 478 /* Set our `shutdownhook' before we start any device activity. */ 479 if (amr_sdh == NULL) 480 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 481 482 /* Attach sub-devices. */ 483 for (j = 0; j < amr->amr_numdrives; j++) { 484 if (amr->amr_drive[j].al_size == 0) 485 continue; 486 amra.amra_unit = j; 487 488 locs[AMRCF_UNIT] = j; 489 490 amr->amr_drive[j].al_dv = config_found_sm_loc(amr->amr_dv, 491 "amr", locs, &amra, amr_print, config_stdsubmatch); 492 } 493 494 SIMPLEQ_INIT(&amr->amr_ccb_queue); 495 496 /* XXX This doesn't work for newer boards yet. */ 497 if ((apt->apt_flags & AT_QUARTZ) == 0) { 498 rv = kthread_create(PRI_NONE, 0, NULL, amr_thread, amr, 499 &amr->amr_thread, "%s", device_xname(amr->amr_dv)); 500 if (rv != 0) 501 aprint_error_dev(amr->amr_dv, "unable to create thread (%d)", 502 rv); 503 else 504 amr->amr_flags |= AMRF_THREAD; 505 } 506 } 507 508 /* 509 * Free up resources. 510 */ 511 static void 512 amr_teardown(struct amr_softc *amr) 513 { 514 struct amr_ccb *ac; 515 int fl; 516 517 fl = amr->amr_flags; 518 519 if ((fl & AMRF_THREAD) != 0) { 520 amr->amr_flags |= AMRF_THREAD_EXIT; 521 wakeup(amr_thread); 522 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) 523 tsleep(&amr->amr_flags, PWAIT, "amrexit", 0); 524 } 525 if ((fl & AMRF_CCBS) != 0) { 526 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 527 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 528 } 529 free(amr->amr_ccbs, M_DEVBUF); 530 } 531 if ((fl & AMRF_ENQBUF) != 0) 532 free(amr->amr_enqbuf, M_DEVBUF); 533 if ((fl & AMRF_DMA_LOAD) != 0) 534 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 535 if ((fl & AMRF_DMA_MAP) != 0) 536 bus_dmamem_unmap(amr->amr_dmat, (void *)amr->amr_mbox, 537 amr->amr_dmasize); 538 if ((fl & AMRF_DMA_ALLOC) != 0) 539 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 540 if ((fl & AMRF_DMA_CREATE) != 0) 541 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 542 if ((fl & AMRF_PCI_INTR) != 0) 543 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 544 if ((fl & AMRF_PCI_REGS) != 0) 545 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 546 } 547 548 /* 549 * Print autoconfiguration message for a sub-device. 550 */ 551 static int 552 amr_print(void *aux, const char *pnp) 553 { 554 struct amr_attach_args *amra; 555 556 amra = (struct amr_attach_args *)aux; 557 558 if (pnp != NULL) 559 aprint_normal("block device at %s", pnp); 560 aprint_normal(" unit %d", amra->amra_unit); 561 return (UNCONF); 562 } 563 564 /* 565 * Retrieve operational parameters and describe the controller. 566 */ 567 static int 568 amr_init(struct amr_softc *amr, const char *intrstr, 569 struct pci_attach_args *pa) 570 { 571 struct amr_adapter_info *aa; 572 struct amr_prodinfo *ap; 573 struct amr_enquiry *ae; 574 struct amr_enquiry3 *aex; 575 const char *prodstr; 576 u_int i, sig, ishp; 577 char sbuf[64]; 578 579 /* 580 * Try to get 40LD product info, which tells us what the card is 581 * labelled as. 582 */ 583 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 584 amr->amr_enqbuf); 585 if (ap != NULL) { 586 aprint_normal("<%.80s>\n", ap->ap_product); 587 if (intrstr != NULL) 588 aprint_normal_dev(amr->amr_dv, "interrupting at %s\n", 589 intrstr); 590 aprint_normal_dev(amr->amr_dv, "firmware %.16s, BIOS %.16s, %dMB RAM\n", 591 ap->ap_firmware, ap->ap_bios, 592 le16toh(ap->ap_memsize)); 593 594 amr->amr_maxqueuecnt = ap->ap_maxio; 595 596 /* 597 * Fetch and record state of logical drives. 598 */ 599 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 600 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 601 if (aex == NULL) { 602 aprint_error_dev(amr->amr_dv, "ENQUIRY3 failed\n"); 603 return (-1); 604 } 605 606 if (aex->ae_numldrives > __arraycount(aex->ae_drivestate)) { 607 aprint_error_dev(amr->amr_dv, "Inquiry returned more drives (%d)" 608 " than the array can handle (%zu)\n", 609 aex->ae_numldrives, 610 __arraycount(aex->ae_drivestate)); 611 aex->ae_numldrives = __arraycount(aex->ae_drivestate); 612 } 613 if (aex->ae_numldrives > AMR_MAX_UNITS) { 614 aprint_error_dev(amr->amr_dv, 615 "adjust AMR_MAX_UNITS to %d (currently %d)" 616 "\n", AMR_MAX_UNITS, 617 amr->amr_numdrives); 618 amr->amr_numdrives = AMR_MAX_UNITS; 619 } else 620 amr->amr_numdrives = aex->ae_numldrives; 621 622 for (i = 0; i < amr->amr_numdrives; i++) { 623 amr->amr_drive[i].al_size = 624 le32toh(aex->ae_drivesize[i]); 625 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 626 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 627 } 628 629 return (0); 630 } 631 632 /* 633 * Try 8LD extended ENQUIRY to get the controller signature. Once 634 * found, search for a product description. 635 */ 636 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 637 if (ae != NULL) { 638 i = 0; 639 sig = le32toh(ae->ae_signature); 640 641 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 642 if (amr_typestr[i].at_sig == sig) 643 break; 644 i++; 645 } 646 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 647 snprintf(sbuf, sizeof(sbuf), 648 "unknown ENQUIRY2 sig (0x%08x)", sig); 649 prodstr = sbuf; 650 } else 651 prodstr = amr_typestr[i].at_str; 652 } else { 653 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 654 if (ae == NULL) { 655 aprint_error_dev(amr->amr_dv, "unsupported controller\n"); 656 return (-1); 657 } 658 659 switch (PCI_PRODUCT(pa->pa_id)) { 660 case PCI_PRODUCT_AMI_MEGARAID: 661 prodstr = "Series 428"; 662 break; 663 case PCI_PRODUCT_AMI_MEGARAID2: 664 prodstr = "Series 434"; 665 break; 666 default: 667 snprintf(sbuf, sizeof(sbuf), "unknown PCI dev (0x%04x)", 668 PCI_PRODUCT(pa->pa_id)); 669 prodstr = sbuf; 670 break; 671 } 672 } 673 674 /* 675 * HP NetRaid controllers have a special encoding of the firmware 676 * and BIOS versions. The AMI version seems to have it as strings 677 * whereas the HP version does it with a leading uppercase character 678 * and two binary numbers. 679 */ 680 aa = &ae->ae_adapter; 681 682 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 683 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 684 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 685 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 686 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 687 /* The AMI 438 is a NetRaid 3si in HP-land. */ 688 prodstr = "HP NetRaid 3si"; 689 } 690 ishp = 1; 691 } else 692 ishp = 0; 693 694 aprint_normal("<%s>\n", prodstr); 695 if (intrstr != NULL) 696 aprint_normal_dev(amr->amr_dv, "interrupting at %s\n", 697 intrstr); 698 699 if (ishp) 700 aprint_normal_dev(amr->amr_dv, "firmware <%c.%02d.%02d>, BIOS <%c.%02d.%02d>" 701 ", %dMB RAM\n", aa->aa_firmware[2], 702 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 703 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 704 else 705 aprint_normal_dev(amr->amr_dv, "firmware <%.4s>, BIOS <%.4s>, %dMB RAM\n", 706 aa->aa_firmware, aa->aa_bios, 707 aa->aa_memorysize); 708 709 amr->amr_maxqueuecnt = aa->aa_maxio; 710 711 /* 712 * Record state of logical drives. 713 */ 714 if (ae->ae_ldrv.al_numdrives > __arraycount(ae->ae_ldrv.al_size)) { 715 aprint_error_dev(amr->amr_dv, "Inquiry returned more drives (%d)" 716 " than the array can handle (%zu)\n", 717 ae->ae_ldrv.al_numdrives, 718 __arraycount(ae->ae_ldrv.al_size)); 719 ae->ae_ldrv.al_numdrives = __arraycount(ae->ae_ldrv.al_size); 720 } 721 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 722 aprint_error_dev(amr->amr_dv, "adjust AMR_MAX_UNITS to %d (currently %d)\n", 723 ae->ae_ldrv.al_numdrives, 724 AMR_MAX_UNITS); 725 amr->amr_numdrives = AMR_MAX_UNITS; 726 } else 727 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 728 729 for (i = 0; i < amr->amr_numdrives; i++) { 730 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 731 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 732 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 733 } 734 735 return (0); 736 } 737 738 /* 739 * Flush the internal cache on each configured controller. Called at 740 * shutdown time. 741 */ 742 static void 743 amr_shutdown(void *cookie) 744 { 745 extern struct cfdriver amr_cd; 746 struct amr_softc *amr; 747 struct amr_ccb *ac; 748 int i, rv, s; 749 750 for (i = 0; i < amr_cd.cd_ndevs; i++) { 751 if ((amr = device_lookup_private(&amr_cd, i)) == NULL) 752 continue; 753 754 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 755 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 756 s = splbio(); 757 rv = amr_ccb_poll(amr, ac, 30000); 758 splx(s); 759 amr_ccb_free(amr, ac); 760 } 761 if (rv != 0) 762 aprint_error_dev(amr->amr_dv, "unable to flush cache (%d)\n", rv); 763 } 764 } 765 766 /* 767 * Interrupt service routine. 768 */ 769 static int 770 amr_intr(void *cookie) 771 { 772 struct amr_softc *amr; 773 struct amr_ccb *ac; 774 struct amr_mailbox_resp mbox; 775 u_int i, forus, idx; 776 777 amr = cookie; 778 forus = 0; 779 780 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 781 /* Iterate over completed commands in this result. */ 782 for (i = 0; i < mbox.mb_nstatus; i++) { 783 idx = mbox.mb_completed[i] - 1; 784 ac = amr->amr_ccbs + idx; 785 786 if (idx >= amr->amr_maxqueuecnt) { 787 printf("%s: bad status (bogus ID: %u=%u)\n", 788 device_xname(amr->amr_dv), i, idx); 789 continue; 790 } 791 792 if ((ac->ac_flags & AC_ACTIVE) == 0) { 793 printf("%s: bad status (not active; 0x04%x)\n", 794 device_xname(amr->amr_dv), ac->ac_flags); 795 continue; 796 } 797 798 ac->ac_status = mbox.mb_status; 799 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 800 AC_COMPLETE; 801 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 802 803 if ((ac->ac_flags & AC_MOAN) != 0) 804 printf("%s: ccb %d completed\n", 805 device_xname(amr->amr_dv), ac->ac_ident); 806 807 /* Pass notification to upper layers. */ 808 if (ac->ac_handler != NULL) 809 (*ac->ac_handler)(ac); 810 else 811 wakeup(ac); 812 } 813 forus = 1; 814 } 815 816 if (forus) 817 amr_ccb_enqueue(amr, NULL); 818 819 return (forus); 820 } 821 822 /* 823 * Watchdog thread. 824 */ 825 static void 826 amr_thread(void *cookie) 827 { 828 struct amr_softc *amr; 829 struct amr_ccb *ac; 830 struct amr_logdrive *al; 831 struct amr_enquiry *ae; 832 int rv, i, s; 833 834 amr = cookie; 835 ae = amr->amr_enqbuf; 836 837 for (;;) { 838 tsleep(amr_thread, PWAIT, "amrwdog", AMR_WDOG_TICKS); 839 840 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 841 amr->amr_flags ^= AMRF_THREAD_EXIT; 842 wakeup(&amr->amr_flags); 843 kthread_exit(0); 844 } 845 846 s = splbio(); 847 amr_intr(cookie); 848 ac = TAILQ_FIRST(&amr->amr_ccb_active); 849 while (ac != NULL) { 850 if (ac->ac_start_time + AMR_TIMEOUT > time_uptime) 851 break; 852 if ((ac->ac_flags & AC_MOAN) == 0) { 853 printf("%s: ccb %d timed out; mailbox:\n", 854 device_xname(amr->amr_dv), ac->ac_ident); 855 amr_ccb_dump(amr, ac); 856 ac->ac_flags |= AC_MOAN; 857 } 858 ac = TAILQ_NEXT(ac, ac_chain.tailq); 859 } 860 splx(s); 861 862 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 863 printf("%s: ccb_alloc failed (%d)\n", 864 device_xname(amr->amr_dv), rv); 865 continue; 866 } 867 868 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 869 870 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 871 AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 872 if (rv != 0) { 873 aprint_error_dev(amr->amr_dv, "ccb_map failed (%d)\n", 874 rv); 875 amr_ccb_free(amr, ac); 876 continue; 877 } 878 879 rv = amr_ccb_wait(amr, ac); 880 amr_ccb_unmap(amr, ac); 881 if (rv != 0) { 882 aprint_error_dev(amr->amr_dv, "enquiry failed (st=%d)\n", 883 ac->ac_status); 884 continue; 885 } 886 amr_ccb_free(amr, ac); 887 888 al = amr->amr_drive; 889 for (i = 0; i < __arraycount(ae->ae_ldrv.al_state); i++, al++) { 890 if (al->al_dv == NULL) 891 continue; 892 if (al->al_state == ae->ae_ldrv.al_state[i]) 893 continue; 894 895 printf("%s: state changed: %s -> %s\n", 896 device_xname(al->al_dv), 897 amr_drive_state(al->al_state, NULL), 898 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 899 900 al->al_state = ae->ae_ldrv.al_state[i]; 901 } 902 } 903 } 904 905 /* 906 * Return a text description of a logical drive's current state. 907 */ 908 const char * 909 amr_drive_state(int state, int *happy) 910 { 911 const char *str; 912 913 state = AMR_DRV_CURSTATE(state); 914 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 915 if (happy) 916 *happy = 1; 917 str = "status unknown"; 918 } else { 919 if (happy) 920 *happy = amr_dstate[state].ds_happy; 921 str = amr_dstate[state].ds_descr; 922 } 923 924 return (str); 925 } 926 927 /* 928 * Run a generic enquiry-style command. 929 */ 930 static void * 931 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 932 u_int8_t cmdqual, void *sbuf) 933 { 934 struct amr_ccb *ac; 935 u_int8_t *mb; 936 int rv; 937 938 if (amr_ccb_alloc(amr, &ac) != 0) 939 return (NULL); 940 941 /* Build the command proper. */ 942 mb = (u_int8_t *)&ac->ac_cmd; 943 mb[0] = cmd; 944 mb[2] = cmdsub; 945 mb[3] = cmdqual; 946 947 rv = amr_ccb_map(amr, ac, sbuf, AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 948 if (rv == 0) { 949 rv = amr_ccb_poll(amr, ac, 2000); 950 amr_ccb_unmap(amr, ac); 951 } 952 amr_ccb_free(amr, ac); 953 954 return (rv ? NULL : sbuf); 955 } 956 957 /* 958 * Allocate and initialise a CCB. 959 */ 960 int 961 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 962 { 963 int s; 964 965 s = splbio(); 966 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 967 splx(s); 968 return (EAGAIN); 969 } 970 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 971 splx(s); 972 973 return (0); 974 } 975 976 /* 977 * Free a CCB. 978 */ 979 void 980 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 981 { 982 int s; 983 984 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 985 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 986 ac->ac_cmd.mb_busy = 1; 987 ac->ac_handler = NULL; 988 ac->ac_flags = 0; 989 990 s = splbio(); 991 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 992 splx(s); 993 } 994 995 /* 996 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 997 * the order that they were enqueued and try to submit their command blocks 998 * to the controller for execution. 999 */ 1000 void 1001 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 1002 { 1003 int s; 1004 1005 s = splbio(); 1006 1007 if (ac != NULL) 1008 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 1009 1010 while ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1011 if ((*amr->amr_submit)(amr, ac) != 0) 1012 break; 1013 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, ac_chain.simpleq); 1014 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1015 } 1016 1017 splx(s); 1018 } 1019 1020 /* 1021 * Map the specified CCB's data buffer onto the bus, and fill the 1022 * scatter-gather list. 1023 */ 1024 int 1025 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1026 int tflag) 1027 { 1028 struct amr_sgentry *sge; 1029 struct amr_mailbox_cmd *mb; 1030 int nsegs, i, rv, sgloff; 1031 bus_dmamap_t xfer; 1032 int dmaflag = 0; 1033 1034 xfer = ac->ac_xfer_map; 1035 1036 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1037 BUS_DMA_NOWAIT); 1038 if (rv != 0) 1039 return (rv); 1040 1041 mb = &ac->ac_cmd; 1042 ac->ac_xfer_size = size; 1043 ac->ac_flags |= (tflag & (AC_XFER_OUT | AC_XFER_IN)); 1044 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1045 1046 if (tflag & AC_XFER_OUT) 1047 dmaflag |= BUS_DMASYNC_PREWRITE; 1048 if (tflag & AC_XFER_IN) 1049 dmaflag |= BUS_DMASYNC_PREREAD; 1050 1051 /* We don't need to use a scatter/gather list for just 1 segment. */ 1052 nsegs = xfer->dm_nsegs; 1053 if (nsegs == 1) { 1054 mb->mb_nsgelem = 0; 1055 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1056 ac->ac_flags |= AC_NOSGL; 1057 } else { 1058 mb->mb_nsgelem = nsegs; 1059 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1060 1061 sge = (struct amr_sgentry *)((char *)amr->amr_sgls + sgloff); 1062 for (i = 0; i < nsegs; i++, sge++) { 1063 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1064 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1065 } 1066 } 1067 1068 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, dmaflag); 1069 1070 if ((ac->ac_flags & AC_NOSGL) == 0) 1071 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1072 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1073 1074 return (0); 1075 } 1076 1077 /* 1078 * Unmap the specified CCB's data buffer. 1079 */ 1080 void 1081 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1082 { 1083 int dmaflag = 0; 1084 1085 if (ac->ac_flags & AC_XFER_IN) 1086 dmaflag |= BUS_DMASYNC_POSTREAD; 1087 if (ac->ac_flags & AC_XFER_OUT) 1088 dmaflag |= BUS_DMASYNC_POSTWRITE; 1089 1090 if ((ac->ac_flags & AC_NOSGL) == 0) 1091 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1092 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1093 BUS_DMASYNC_POSTWRITE); 1094 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1095 dmaflag); 1096 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1097 } 1098 1099 /* 1100 * Submit a command to the controller and poll on completion. Return 1101 * non-zero on timeout or error. Must be called with interrupts blocked. 1102 */ 1103 int 1104 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1105 { 1106 int rv; 1107 1108 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) 1109 return (rv); 1110 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1111 1112 for (timo *= 10; timo != 0; timo--) { 1113 amr_intr(amr); 1114 if ((ac->ac_flags & AC_COMPLETE) != 0) 1115 break; 1116 DELAY(100); 1117 } 1118 1119 return (timo == 0 || ac->ac_status != 0 ? EIO : 0); 1120 } 1121 1122 /* 1123 * Submit a command to the controller and sleep on completion. Return 1124 * non-zero on error. 1125 */ 1126 int 1127 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1128 { 1129 int s; 1130 1131 s = splbio(); 1132 amr_ccb_enqueue(amr, ac); 1133 tsleep(ac, PRIBIO, "amrcmd", 0); 1134 splx(s); 1135 1136 return (ac->ac_status != 0 ? EIO : 0); 1137 } 1138 1139 #if 0 1140 /* 1141 * Wait for the mailbox to become available. 1142 */ 1143 static int 1144 amr_mbox_wait(struct amr_softc *amr) 1145 { 1146 int timo; 1147 1148 for (timo = 10000; timo != 0; timo--) { 1149 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1150 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1151 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1152 break; 1153 DELAY(100); 1154 } 1155 1156 if (timo == 0) 1157 printf("%s: controller wedged\n", device_xname(amr->amr_dv)); 1158 1159 return (timo != 0 ? 0 : EAGAIN); 1160 } 1161 #endif 1162 1163 /* 1164 * Tell the controller that the mailbox contains a valid command. Must be 1165 * called with interrupts blocked. 1166 */ 1167 static int 1168 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1169 { 1170 u_int32_t v; 1171 1172 amr->amr_mbox->mb_poll = 0; 1173 amr->amr_mbox->mb_ack = 0; 1174 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1175 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1176 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1177 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1178 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1179 return (EAGAIN); 1180 1181 v = amr_inl(amr, AMR_QREG_IDB); 1182 if ((v & AMR_QIDB_SUBMIT) != 0) { 1183 amr->amr_mbox->mb_cmd.mb_busy = 0; 1184 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1185 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1186 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1187 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1188 return (EAGAIN); 1189 } 1190 1191 amr->amr_mbox->mb_segment = 0; 1192 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1193 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1194 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1195 1196 ac->ac_start_time = time_uptime; 1197 ac->ac_flags |= AC_ACTIVE; 1198 amr_outl(amr, AMR_QREG_IDB, 1199 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1200 return (0); 1201 } 1202 1203 static int 1204 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1205 { 1206 1207 amr->amr_mbox->mb_poll = 0; 1208 amr->amr_mbox->mb_ack = 0; 1209 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1210 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1211 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1212 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1213 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1214 return (EAGAIN); 1215 1216 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1217 amr->amr_mbox->mb_cmd.mb_busy = 0; 1218 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1219 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1220 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1221 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1222 return (EAGAIN); 1223 } 1224 1225 amr->amr_mbox->mb_segment = 0; 1226 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1227 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1228 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1229 1230 ac->ac_start_time = time_uptime; 1231 ac->ac_flags |= AC_ACTIVE; 1232 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1233 return (0); 1234 } 1235 1236 /* 1237 * Claim any work that the controller has completed; acknowledge completion, 1238 * save details of the completion in (mbsave). Must be called with 1239 * interrupts blocked. 1240 */ 1241 static int 1242 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1243 { 1244 1245 /* Work waiting for us? */ 1246 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1247 return (-1); 1248 1249 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1250 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1251 1252 /* Save the mailbox, which contains a list of completed commands. */ 1253 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1254 1255 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1256 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1257 1258 /* Ack the interrupt and mailbox transfer. */ 1259 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1260 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1261 1262 /* 1263 * This waits for the controller to notice that we've taken the 1264 * command from it. It's very inefficient, and we shouldn't do it, 1265 * but if we remove this code, we stop completing commands under 1266 * load. 1267 * 1268 * Peter J says we shouldn't do this. The documentation says we 1269 * should. Who is right? 1270 */ 1271 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1272 DELAY(10); 1273 1274 return (0); 1275 } 1276 1277 static int 1278 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1279 { 1280 u_int8_t istat; 1281 1282 /* Check for valid interrupt status. */ 1283 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1284 return (-1); 1285 1286 /* Ack the interrupt. */ 1287 amr_outb(amr, AMR_SREG_INTR, istat); 1288 1289 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1290 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1291 1292 /* Save mailbox, which contains a list of completed commands. */ 1293 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1294 1295 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1296 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1297 1298 /* Ack mailbox transfer. */ 1299 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1300 1301 return (0); 1302 } 1303 1304 static void 1305 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1306 { 1307 int i; 1308 1309 printf("%s: ", device_xname(amr->amr_dv)); 1310 for (i = 0; i < 4; i++) 1311 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1312 printf("\n"); 1313 } 1314 1315 static int 1316 amropen(dev_t dev, int flag, int mode, struct lwp *l) 1317 { 1318 struct amr_softc *amr; 1319 1320 if ((amr = device_lookup_private(&amr_cd, minor(dev))) == NULL) 1321 return (ENXIO); 1322 if ((amr->amr_flags & AMRF_OPEN) != 0) 1323 return (EBUSY); 1324 1325 amr->amr_flags |= AMRF_OPEN; 1326 return (0); 1327 } 1328 1329 static int 1330 amrclose(dev_t dev, int flag, int mode, struct lwp *l) 1331 { 1332 struct amr_softc *amr; 1333 1334 amr = device_lookup_private(&amr_cd, minor(dev)); 1335 amr->amr_flags &= ~AMRF_OPEN; 1336 return (0); 1337 } 1338 1339 static int 1340 amrioctl(dev_t dev, u_long cmd, void *data, int flag, 1341 struct lwp *l) 1342 { 1343 struct amr_softc *amr; 1344 struct amr_user_ioctl *au; 1345 struct amr_ccb *ac; 1346 struct amr_mailbox_ioctl *mbi; 1347 unsigned long au_length; 1348 uint8_t *au_cmd; 1349 int error; 1350 void *dp = NULL, *au_buffer; 1351 1352 amr = device_lookup_private(&amr_cd, minor(dev)); 1353 1354 /* This should be compatible with the FreeBSD interface */ 1355 1356 switch (cmd) { 1357 case AMR_IO_VERSION: 1358 *(int *)data = AMR_IO_VERSION_NUMBER; 1359 return 0; 1360 case AMR_IO_COMMAND: 1361 error = kauth_authorize_device_passthru(l->l_cred, dev, 1362 KAUTH_REQ_DEVICE_RAWIO_PASSTHRU_ALL, data); 1363 if (error) 1364 return (error); 1365 1366 au = (struct amr_user_ioctl *)data; 1367 au_cmd = au->au_cmd; 1368 au_buffer = au->au_buffer; 1369 au_length = au->au_length; 1370 break; 1371 default: 1372 return ENOTTY; 1373 } 1374 1375 if (au_cmd[0] == AMR_CMD_PASS) { 1376 /* not yet */ 1377 return EOPNOTSUPP; 1378 } 1379 1380 if (au_length <= 0 || au_length > device_maxphys(amr->amr_dv) || 1381 au_cmd[0] == 0x06) 1382 return (EINVAL); 1383 1384 /* 1385 * allocate kernel memory for data, doing I/O directly to user 1386 * buffer isn't that easy. 1387 */ 1388 dp = malloc(au_length, M_DEVBUF, M_WAITOK|M_ZERO); 1389 if (dp == NULL) 1390 return ENOMEM; 1391 if ((error = copyin(au_buffer, dp, au_length)) != 0) 1392 goto out; 1393 1394 /* direct command to controller */ 1395 while (amr_ccb_alloc(amr, &ac) != 0) { 1396 error = tsleep(NULL, PRIBIO | PCATCH, "armmbx", hz); 1397 if (error == EINTR) 1398 goto out; 1399 } 1400 1401 mbi = (struct amr_mailbox_ioctl *)&ac->ac_cmd; 1402 mbi->mb_command = au_cmd[0]; 1403 mbi->mb_channel = au_cmd[1]; 1404 mbi->mb_param = au_cmd[2]; 1405 mbi->mb_pad[0] = au_cmd[3]; 1406 mbi->mb_drive = au_cmd[4]; 1407 error = amr_ccb_map(amr, ac, dp, (int)au_length, 1408 AC_XFER_IN | AC_XFER_OUT); 1409 if (error == 0) { 1410 error = amr_ccb_wait(amr, ac); 1411 amr_ccb_unmap(amr, ac); 1412 if (error == 0) 1413 error = copyout(dp, au_buffer, au_length); 1414 1415 } 1416 amr_ccb_free(amr, ac); 1417 out: 1418 free(dp, M_DEVBUF); 1419 return (error); 1420 } 1421
Indexes created Thu Oct 02 14:10:14 GMT 2025