amr.c revision 1.55.2.3
1 /* $NetBSD: amr.c,v 1.55.2.3 2017/12/03 11:37:07 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999,2000 Michael Smith 34 * Copyright (c) 2000 BSDi 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 * 58 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 59 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 60 */ 61 62 /* 63 * Driver for AMI RAID controllers. 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.55.2.3 2017/12/03 11:37:07 jdolecek Exp $"); 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/kernel.h> 72 #include <sys/device.h> 73 #include <sys/queue.h> 74 #include <sys/proc.h> 75 #include <sys/buf.h> 76 #include <sys/malloc.h> 77 #include <sys/conf.h> 78 #include <sys/kthread.h> 79 #include <sys/kauth.h> 80 #include <sys/mutex.h> 81 #include <sys/condvar.h> 82 #include <sys/module.h> 83 84 #include <machine/endian.h> 85 #include <sys/bus.h> 86 87 #include <dev/pci/pcidevs.h> 88 #include <dev/pci/pcivar.h> 89 #include <dev/pci/amrreg.h> 90 #include <dev/pci/amrvar.h> 91 #include <dev/pci/amrio.h> 92 93 #include "locators.h" 94 95 #include "ioconf.h" 96 97 static void amr_attach(device_t, device_t, void *); 98 static void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 99 static void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, 100 void *); 101 static int amr_init(struct amr_softc *, const char *, 102 struct pci_attach_args *pa); 103 static int amr_intr(void *); 104 static int amr_match(device_t, cfdata_t, void *); 105 static int amr_rescan(device_t, const char *, const int *); 106 static int amr_print(void *, const char *); 107 static void amr_shutdown(void *); 108 static void amr_teardown(struct amr_softc *); 109 static void amr_quartz_thread(void *); 110 static void amr_std_thread(void *); 111 112 static int amr_quartz_get_work(struct amr_softc *, 113 struct amr_mailbox_resp *); 114 static int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 115 static int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 116 static int amr_std_submit(struct amr_softc *, struct amr_ccb *); 117 118 static dev_type_open(amropen); 119 static dev_type_close(amrclose); 120 static dev_type_ioctl(amrioctl); 121 122 CFATTACH_DECL3_NEW(amr, sizeof(struct amr_softc), 123 amr_match, amr_attach, NULL, NULL, amr_rescan, NULL, 0); 124 125 const struct cdevsw amr_cdevsw = { 126 .d_open = amropen, 127 .d_close = amrclose, 128 .d_read = noread, 129 .d_write = nowrite, 130 .d_ioctl = amrioctl, 131 .d_stop = nostop, 132 .d_tty = notty, 133 .d_poll = nopoll, 134 .d_mmap = nommap, 135 .d_kqfilter = nokqfilter, 136 .d_discard = nodiscard, 137 .d_flag = D_OTHER 138 }; 139 140 extern struct cfdriver amr_cd; 141 142 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 143 #define AT_SIG 0x02 /* Check for signature */ 144 145 static struct amr_pci_type { 146 u_short apt_vendor; 147 u_short apt_product; 148 u_short apt_flags; 149 } const amr_pci_type[] = { 150 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 151 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 152 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 153 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 157 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 158 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 159 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 160 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4ESI, AT_QUARTZ }, 161 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_PERC_4SC, AT_QUARTZ }, 162 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 163 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 164 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 165 }; 166 167 static struct amr_typestr { 168 const char *at_str; 169 int at_sig; 170 } const amr_typestr[] = { 171 { "Series 431", AMR_SIG_431 }, 172 { "Series 438", AMR_SIG_438 }, 173 { "Series 466", AMR_SIG_466 }, 174 { "Series 467", AMR_SIG_467 }, 175 { "Series 490", AMR_SIG_490 }, 176 { "Series 762", AMR_SIG_762 }, 177 { "HP NetRAID (T5)", AMR_SIG_T5 }, 178 { "HP NetRAID (T7)", AMR_SIG_T7 }, 179 }; 180 181 static struct { 182 const char *ds_descr; 183 int ds_happy; 184 } const amr_dstate[] = { 185 { "offline", 0 }, 186 { "degraded", 1 }, 187 { "optimal", 1 }, 188 { "online", 1 }, 189 { "failed", 0 }, 190 { "rebuilding", 1 }, 191 { "hotspare", 0 }, 192 }; 193 194 static void *amr_sdh; 195 196 static kcondvar_t thread_cv; 197 static kmutex_t thread_mutex; 198 199 static int amr_max_segs; 200 int amr_max_xfer; 201 202 static inline u_int8_t 203 amr_inb(struct amr_softc *amr, int off) 204 { 205 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 206 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 207 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 208 } 209 210 static inline u_int32_t 211 amr_inl(struct amr_softc *amr, int off) 212 { 213 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 214 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 215 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 216 } 217 218 static inline void 219 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 220 { 221 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 222 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 223 BUS_SPACE_BARRIER_WRITE); 224 } 225 226 static inline void 227 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 228 { 229 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 230 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 231 BUS_SPACE_BARRIER_WRITE); 232 } 233 234 /* 235 * Match a supported device. 236 */ 237 static int 238 amr_match(device_t parent, cfdata_t match, void *aux) 239 { 240 struct pci_attach_args *pa; 241 pcireg_t s; 242 int i; 243 244 pa = (struct pci_attach_args *)aux; 245 246 /* 247 * Don't match the device if it's operating in I2O mode. In this 248 * case it should be handled by the `iop' driver. 249 */ 250 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 251 return (0); 252 253 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 254 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 255 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 256 break; 257 258 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 259 return (0); 260 261 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 262 return (1); 263 264 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 265 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 266 } 267 268 /* 269 * Attach a supported device. 270 */ 271 static void 272 amr_attach(device_t parent, device_t self, void *aux) 273 { 274 struct pci_attach_args *pa; 275 const struct amr_pci_type *apt; 276 struct amr_softc *amr; 277 pci_chipset_tag_t pc; 278 pci_intr_handle_t ih; 279 const char *intrstr; 280 pcireg_t reg; 281 int rseg, i, size, rv, memreg, ioreg; 282 struct amr_ccb *ac; 283 char intrbuf[PCI_INTRSTR_LEN]; 284 285 aprint_naive(": RAID controller\n"); 286 287 amr = device_private(self); 288 amr->amr_dv = self; 289 290 mutex_init(&amr->amr_mutex, MUTEX_DEFAULT, IPL_BIO); 291 292 pa = (struct pci_attach_args *)aux; 293 pc = pa->pa_pc; 294 295 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 296 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 297 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 298 break; 299 apt = amr_pci_type + i; 300 301 memreg = ioreg = 0; 302 for (i = 0x10; i <= 0x14; i += 4) { 303 reg = pci_conf_read(pc, pa->pa_tag, i); 304 switch (PCI_MAPREG_TYPE(reg)) { 305 case PCI_MAPREG_TYPE_MEM: 306 if (PCI_MAPREG_MEM_SIZE(reg) != 0) 307 memreg = i; 308 break; 309 case PCI_MAPREG_TYPE_IO: 310 if (PCI_MAPREG_IO_SIZE(reg) != 0) 311 ioreg = i; 312 break; 313 } 314 } 315 316 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 317 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 318 ; 319 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 320 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 321 ; 322 else { 323 aprint_error("can't map control registers\n"); 324 amr_teardown(amr); 325 return; 326 } 327 328 amr->amr_flags |= AMRF_PCI_REGS; 329 amr->amr_dmat = pa->pa_dmat; 330 amr->amr_pc = pa->pa_pc; 331 332 /* Enable the device. */ 333 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 334 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 335 reg | PCI_COMMAND_MASTER_ENABLE); 336 337 /* Map and establish the interrupt. */ 338 if (pci_intr_map(pa, &ih)) { 339 aprint_error("can't map interrupt\n"); 340 amr_teardown(amr); 341 return; 342 } 343 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 344 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); 345 if (amr->amr_ih == NULL) { 346 aprint_error("can't establish interrupt"); 347 if (intrstr != NULL) 348 aprint_error(" at %s", intrstr); 349 aprint_error("\n"); 350 amr_teardown(amr); 351 return; 352 } 353 amr->amr_flags |= AMRF_PCI_INTR; 354 355 /* 356 * Allocate space for the mailbox and S/G lists. Some controllers 357 * don't like S/G lists to be located below 0x2000, so we allocate 358 * enough slop to enable us to compensate. 359 * 360 * The standard mailbox structure needs to be aligned on a 16-byte 361 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 362 * size, which precedes the standard mailbox. 363 */ 364 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 365 amr->amr_dmasize = size; 366 367 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, 368 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 369 aprint_error_dev(amr->amr_dv, 370 "unable to allocate buffer, rv = %d\n", rv); 371 amr_teardown(amr); 372 return; 373 } 374 amr->amr_flags |= AMRF_DMA_ALLOC; 375 376 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 377 (void **)&amr->amr_mbox, 378 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 379 aprint_error_dev(amr->amr_dv, "unable to map buffer, rv = %d\n", 380 rv); 381 amr_teardown(amr); 382 return; 383 } 384 amr->amr_flags |= AMRF_DMA_MAP; 385 386 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 387 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 388 aprint_error_dev(amr->amr_dv, 389 "unable to create buffer DMA map, rv = %d\n", rv); 390 amr_teardown(amr); 391 return; 392 } 393 amr->amr_flags |= AMRF_DMA_CREATE; 394 395 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 396 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 397 aprint_error_dev(amr->amr_dv, 398 "unable to load buffer DMA map, rv = %d\n", rv); 399 amr_teardown(amr); 400 return; 401 } 402 amr->amr_flags |= AMRF_DMA_LOAD; 403 404 memset(amr->amr_mbox, 0, size); 405 406 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 407 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 408 amr->amr_sgls = (struct amr_sgentry *)((char *)amr->amr_mbox + 409 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 410 411 /* 412 * Allocate and initalise the command control blocks. 413 */ 414 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); 415 amr->amr_ccbs = ac; 416 SLIST_INIT(&amr->amr_ccb_freelist); 417 TAILQ_INIT(&amr->amr_ccb_active); 418 amr->amr_flags |= AMRF_CCBS; 419 420 if (amr_max_xfer == 0) { 421 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), 422 device_maxphys(amr->amr_dv)); 423 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 424 } 425 amr->amr_dv->dv_maxphys = amr_max_xfer; 426 427 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 428 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 429 amr_max_segs, amr_max_xfer, 0, 430 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 431 if (rv != 0) 432 break; 433 434 ac->ac_ident = i; 435 cv_init(&ac->ac_cv, "amr1ccb"); 436 mutex_init(&ac->ac_mutex, MUTEX_DEFAULT, IPL_NONE); 437 amr_ccb_free(amr, ac); 438 } 439 if (i != AMR_MAX_CMDS) { 440 aprint_error_dev(amr->amr_dv, "memory exhausted\n"); 441 amr_teardown(amr); 442 return; 443 } 444 445 /* 446 * Take care of model-specific tasks. 447 */ 448 if ((apt->apt_flags & AT_QUARTZ) != 0) { 449 amr->amr_submit = amr_quartz_submit; 450 amr->amr_get_work = amr_quartz_get_work; 451 } else { 452 amr->amr_submit = amr_std_submit; 453 amr->amr_get_work = amr_std_get_work; 454 455 /* Notify the controller of the mailbox location. */ 456 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 457 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 458 459 /* Clear outstanding interrupts and enable interrupts. */ 460 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 461 amr_outb(amr, AMR_SREG_TOGL, 462 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 463 } 464 465 /* 466 * Retrieve parameters, and tell the world about us. 467 */ 468 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); 469 amr->amr_flags |= AMRF_ENQBUF; 470 amr->amr_maxqueuecnt = i; 471 aprint_normal(": AMI RAID "); 472 if (amr_init(amr, intrstr, pa) != 0) { 473 amr_teardown(amr); 474 return; 475 } 476 477 /* 478 * Cap the maximum number of outstanding commands. AMI's Linux 479 * driver doesn't trust the controller's reported value, and lockups 480 * have been seen when we do. 481 */ 482 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 483 if (amr->amr_maxqueuecnt > i) 484 amr->amr_maxqueuecnt = i; 485 486 /* Set our `shutdownhook' before we start any device activity. */ 487 if (amr_sdh == NULL) 488 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 489 490 /* Attach sub-devices. */ 491 amr_rescan(self, "amr", 0); 492 493 SIMPLEQ_INIT(&amr->amr_ccb_queue); 494 495 cv_init(&thread_cv, "amrwdog"); 496 mutex_init(&thread_mutex, MUTEX_DEFAULT, IPL_NONE); 497 498 if ((apt->apt_flags & AT_QUARTZ) == 0) { 499 rv = kthread_create(PRI_NONE, KTHREAD_MPSAFE, NULL, 500 amr_std_thread, amr, &amr->amr_thread, 501 "%s", device_xname(amr->amr_dv)); 502 } else { 503 rv = kthread_create(PRI_NONE, KTHREAD_MPSAFE, NULL, 504 amr_quartz_thread, amr, &amr->amr_thread, 505 "%s", device_xname(amr->amr_dv)); 506 } 507 if (rv != 0) 508 aprint_error_dev(amr->amr_dv, "unable to create thread (%d)", 509 rv); 510 else 511 amr->amr_flags |= AMRF_THREAD; 512 } 513 514 static int 515 amr_rescan(device_t self, const char *attr, const int *flags) 516 { 517 int j; 518 int locs[AMRCF_NLOCS]; 519 struct amr_attach_args amra; 520 struct amr_softc *amr; 521 522 amr = device_private(self); 523 for (j = 0; j < amr->amr_numdrives; j++) { 524 if (amr->amr_drive[j].al_dv) 525 continue; 526 if (amr->amr_drive[j].al_size == 0) 527 continue; 528 amra.amra_unit = j; 529 530 locs[AMRCF_UNIT] = j; 531 532 amr->amr_drive[j].al_dv = config_found_sm_loc(amr->amr_dv, 533 attr, locs, &amra, amr_print, config_stdsubmatch); 534 } 535 return 0; 536 } 537 538 /* 539 * Free up resources. 540 */ 541 static void 542 amr_teardown(struct amr_softc *amr) 543 { 544 struct amr_ccb *ac; 545 int fl; 546 547 fl = amr->amr_flags; 548 549 if ((fl & AMRF_THREAD) != 0) { 550 amr->amr_flags |= AMRF_THREAD_EXIT; 551 mutex_enter(&thread_mutex); 552 cv_broadcast(&thread_cv); 553 mutex_exit(&thread_mutex); 554 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 555 mutex_enter(&thread_mutex); 556 cv_wait(&thread_cv, &thread_mutex); 557 mutex_exit(&thread_mutex); 558 } 559 } 560 if ((fl & AMRF_CCBS) != 0) { 561 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 562 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 563 } 564 free(amr->amr_ccbs, M_DEVBUF); 565 } 566 if ((fl & AMRF_ENQBUF) != 0) 567 free(amr->amr_enqbuf, M_DEVBUF); 568 if ((fl & AMRF_DMA_LOAD) != 0) 569 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 570 if ((fl & AMRF_DMA_MAP) != 0) 571 bus_dmamem_unmap(amr->amr_dmat, (void *)amr->amr_mbox, 572 amr->amr_dmasize); 573 if ((fl & AMRF_DMA_ALLOC) != 0) 574 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 575 if ((fl & AMRF_DMA_CREATE) != 0) 576 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 577 if ((fl & AMRF_PCI_INTR) != 0) 578 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 579 if ((fl & AMRF_PCI_REGS) != 0) 580 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 581 } 582 583 /* 584 * Print autoconfiguration message for a sub-device. 585 */ 586 static int 587 amr_print(void *aux, const char *pnp) 588 { 589 struct amr_attach_args *amra; 590 591 amra = (struct amr_attach_args *)aux; 592 593 if (pnp != NULL) 594 aprint_normal("block device at %s", pnp); 595 aprint_normal(" unit %d", amra->amra_unit); 596 return (UNCONF); 597 } 598 599 /* 600 * Retrieve operational parameters and describe the controller. 601 */ 602 static int 603 amr_init(struct amr_softc *amr, const char *intrstr, 604 struct pci_attach_args *pa) 605 { 606 struct amr_adapter_info *aa; 607 struct amr_prodinfo *ap; 608 struct amr_enquiry *ae; 609 struct amr_enquiry3 *aex; 610 const char *prodstr; 611 u_int i, sig, ishp; 612 char sbuf[64]; 613 614 /* 615 * Try to get 40LD product info, which tells us what the card is 616 * labelled as. 617 */ 618 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 619 amr->amr_enqbuf); 620 if (ap != NULL) { 621 aprint_normal("<%.80s>\n", ap->ap_product); 622 if (intrstr != NULL) 623 aprint_normal_dev(amr->amr_dv, "interrupting at %s\n", 624 intrstr); 625 aprint_normal_dev(amr->amr_dv, 626 "firmware %.16s, BIOS %.16s, %dMB RAM\n", 627 ap->ap_firmware, ap->ap_bios, le16toh(ap->ap_memsize)); 628 629 amr->amr_maxqueuecnt = ap->ap_maxio; 630 631 /* 632 * Fetch and record state of logical drives. 633 */ 634 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 635 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 636 if (aex == NULL) { 637 aprint_error_dev(amr->amr_dv, "ENQUIRY3 failed\n"); 638 return (-1); 639 } 640 641 if (aex->ae_numldrives > __arraycount(aex->ae_drivestate)) { 642 aprint_error_dev(amr->amr_dv, "Inquiry returned more " 643 "drives (%d) than the array can handle (%zu)\n", 644 aex->ae_numldrives, 645 __arraycount(aex->ae_drivestate)); 646 aex->ae_numldrives = __arraycount(aex->ae_drivestate); 647 } 648 if (aex->ae_numldrives > AMR_MAX_UNITS) { 649 aprint_error_dev(amr->amr_dv, 650 "adjust AMR_MAX_UNITS to %d (currently %d)\n", 651 AMR_MAX_UNITS, amr->amr_numdrives); 652 amr->amr_numdrives = AMR_MAX_UNITS; 653 } else 654 amr->amr_numdrives = aex->ae_numldrives; 655 656 for (i = 0; i < amr->amr_numdrives; i++) { 657 amr->amr_drive[i].al_size = 658 le32toh(aex->ae_drivesize[i]); 659 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 660 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 661 } 662 663 return (0); 664 } 665 666 /* 667 * Try 8LD extended ENQUIRY to get the controller signature. Once 668 * found, search for a product description. 669 */ 670 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 671 if (ae != NULL) { 672 i = 0; 673 sig = le32toh(ae->ae_signature); 674 675 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 676 if (amr_typestr[i].at_sig == sig) 677 break; 678 i++; 679 } 680 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 681 snprintf(sbuf, sizeof(sbuf), 682 "unknown ENQUIRY2 sig (0x%08x)", sig); 683 prodstr = sbuf; 684 } else 685 prodstr = amr_typestr[i].at_str; 686 } else { 687 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 688 if (ae == NULL) { 689 aprint_error_dev(amr->amr_dv, 690 "unsupported controller\n"); 691 return (-1); 692 } 693 694 switch (PCI_PRODUCT(pa->pa_id)) { 695 case PCI_PRODUCT_AMI_MEGARAID: 696 prodstr = "Series 428"; 697 break; 698 case PCI_PRODUCT_AMI_MEGARAID2: 699 prodstr = "Series 434"; 700 break; 701 default: 702 snprintf(sbuf, sizeof(sbuf), 703 "unknown PCI dev (0x%04x)", 704 PCI_PRODUCT(pa->pa_id)); 705 prodstr = sbuf; 706 break; 707 } 708 } 709 710 /* 711 * HP NetRaid controllers have a special encoding of the firmware 712 * and BIOS versions. The AMI version seems to have it as strings 713 * whereas the HP version does it with a leading uppercase character 714 * and two binary numbers. 715 */ 716 aa = &ae->ae_adapter; 717 718 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 719 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 720 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 721 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 722 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 723 /* The AMI 438 is a NetRaid 3si in HP-land. */ 724 prodstr = "HP NetRaid 3si"; 725 } 726 ishp = 1; 727 } else 728 ishp = 0; 729 730 aprint_normal("<%s>\n", prodstr); 731 if (intrstr != NULL) 732 aprint_normal_dev(amr->amr_dv, "interrupting at %s\n", 733 intrstr); 734 735 if (ishp) 736 aprint_normal_dev(amr->amr_dv, "firmware <%c.%02d.%02d>, " 737 "BIOS <%c.%02d.%02d>, %dMB RAM\n", aa->aa_firmware[2], 738 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 739 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 740 else 741 aprint_normal_dev(amr->amr_dv, "firmware <%.4s>, BIOS <%.4s>, " 742 "%dMB RAM\n", aa->aa_firmware, aa->aa_bios, 743 aa->aa_memorysize); 744 745 amr->amr_maxqueuecnt = aa->aa_maxio; 746 747 /* 748 * Record state of logical drives. 749 */ 750 if (ae->ae_ldrv.al_numdrives > __arraycount(ae->ae_ldrv.al_size)) { 751 aprint_error_dev(amr->amr_dv, "Inquiry returned more drives " 752 "(%d) than the array can handle (%zu)\n", 753 ae->ae_ldrv.al_numdrives, 754 __arraycount(ae->ae_ldrv.al_size)); 755 ae->ae_ldrv.al_numdrives = __arraycount(ae->ae_ldrv.al_size); 756 } 757 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 758 aprint_error_dev(amr->amr_dv, 759 "adjust AMR_MAX_UNITS to %d (currently %d)\n", 760 ae->ae_ldrv.al_numdrives, AMR_MAX_UNITS); 761 amr->amr_numdrives = AMR_MAX_UNITS; 762 } else 763 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 764 765 for (i = 0; i < amr->amr_numdrives; i++) { 766 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 767 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 768 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 769 } 770 771 return (0); 772 } 773 774 /* 775 * Flush the internal cache on each configured controller. Called at 776 * shutdown time. 777 */ 778 static void 779 amr_shutdown(void *cookie) 780 { 781 extern struct cfdriver amr_cd; 782 struct amr_softc *amr; 783 struct amr_ccb *ac; 784 int i, rv; 785 786 for (i = 0; i < amr_cd.cd_ndevs; i++) { 787 if ((amr = device_lookup_private(&amr_cd, i)) == NULL) 788 continue; 789 790 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 791 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 792 rv = amr_ccb_poll(amr, ac, 30000); 793 amr_ccb_free(amr, ac); 794 } 795 if (rv != 0) 796 aprint_error_dev(amr->amr_dv, 797 "unable to flush cache (%d)\n", rv); 798 } 799 } 800 801 /* 802 * Interrupt service routine. 803 */ 804 static int 805 amr_intr(void *cookie) 806 { 807 struct amr_softc *amr; 808 struct amr_ccb *ac; 809 struct amr_mailbox_resp mbox; 810 u_int i, forus, idx; 811 812 amr = cookie; 813 forus = 0; 814 815 mutex_spin_enter(&amr->amr_mutex); 816 817 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 818 /* Iterate over completed commands in this result. */ 819 for (i = 0; i < mbox.mb_nstatus; i++) { 820 idx = mbox.mb_completed[i] - 1; 821 ac = amr->amr_ccbs + idx; 822 823 if (idx >= amr->amr_maxqueuecnt) { 824 printf("%s: bad status (bogus ID: %u=%u)\n", 825 device_xname(amr->amr_dv), i, idx); 826 continue; 827 } 828 829 if ((ac->ac_flags & AC_ACTIVE) == 0) { 830 printf("%s: bad status (not active; 0x04%x)\n", 831 device_xname(amr->amr_dv), ac->ac_flags); 832 continue; 833 } 834 835 ac->ac_status = mbox.mb_status; 836 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 837 AC_COMPLETE; 838 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 839 840 if ((ac->ac_flags & AC_MOAN) != 0) 841 printf("%s: ccb %d completed\n", 842 device_xname(amr->amr_dv), ac->ac_ident); 843 844 /* Pass notification to upper layers. */ 845 mutex_spin_exit(&amr->amr_mutex); 846 if (ac->ac_handler != NULL) { 847 (*ac->ac_handler)(ac); 848 } else { 849 mutex_enter(&ac->ac_mutex); 850 cv_signal(&ac->ac_cv); 851 mutex_exit(&ac->ac_mutex); 852 } 853 mutex_spin_enter(&amr->amr_mutex); 854 } 855 forus = 1; 856 } 857 858 mutex_spin_exit(&amr->amr_mutex); 859 860 if (forus) 861 amr_ccb_enqueue(amr, NULL); 862 863 return (forus); 864 } 865 866 /* 867 * Watchdog thread. 868 */ 869 static void 870 amr_quartz_thread(void *cookie) 871 { 872 struct amr_softc *amr; 873 struct amr_ccb *ac; 874 875 amr = cookie; 876 877 for (;;) { 878 mutex_enter(&thread_mutex); 879 cv_timedwait(&thread_cv, &thread_mutex, AMR_WDOG_TICKS); 880 mutex_exit(&thread_mutex); 881 882 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 883 amr->amr_flags ^= AMRF_THREAD_EXIT; 884 mutex_enter(&thread_mutex); 885 cv_signal(&thread_cv); 886 mutex_exit(&thread_mutex); 887 kthread_exit(0); 888 } 889 890 if (amr_intr(amr) == 0) 891 amr_ccb_enqueue(amr, NULL); 892 893 mutex_spin_enter(&amr->amr_mutex); 894 ac = TAILQ_FIRST(&amr->amr_ccb_active); 895 while (ac != NULL) { 896 if (ac->ac_start_time + AMR_TIMEOUT > time_uptime) 897 break; 898 if ((ac->ac_flags & AC_MOAN) == 0) { 899 printf("%s: ccb %d timed out; mailbox:\n", 900 device_xname(amr->amr_dv), ac->ac_ident); 901 amr_ccb_dump(amr, ac); 902 ac->ac_flags |= AC_MOAN; 903 } 904 ac = TAILQ_NEXT(ac, ac_chain.tailq); 905 } 906 mutex_spin_exit(&amr->amr_mutex); 907 } 908 } 909 910 static void 911 amr_std_thread(void *cookie) 912 { 913 struct amr_softc *amr; 914 struct amr_ccb *ac; 915 struct amr_logdrive *al; 916 struct amr_enquiry *ae; 917 int rv, i; 918 919 amr = cookie; 920 ae = amr->amr_enqbuf; 921 922 for (;;) { 923 mutex_enter(&thread_mutex); 924 cv_timedwait(&thread_cv, &thread_mutex, AMR_WDOG_TICKS); 925 mutex_exit(&thread_mutex); 926 927 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 928 amr->amr_flags ^= AMRF_THREAD_EXIT; 929 mutex_enter(&thread_mutex); 930 cv_signal(&thread_cv); 931 mutex_exit(&thread_mutex); 932 kthread_exit(0); 933 } 934 935 if (amr_intr(amr) == 0) 936 amr_ccb_enqueue(amr, NULL); 937 938 mutex_spin_enter(&amr->amr_mutex); 939 ac = TAILQ_FIRST(&amr->amr_ccb_active); 940 while (ac != NULL) { 941 if (ac->ac_start_time + AMR_TIMEOUT > time_uptime) 942 break; 943 if ((ac->ac_flags & AC_MOAN) == 0) { 944 printf("%s: ccb %d timed out; mailbox:\n", 945 device_xname(amr->amr_dv), ac->ac_ident); 946 amr_ccb_dump(amr, ac); 947 ac->ac_flags |= AC_MOAN; 948 } 949 ac = TAILQ_NEXT(ac, ac_chain.tailq); 950 } 951 mutex_spin_exit(&amr->amr_mutex); 952 953 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 954 printf("%s: ccb_alloc failed (%d)\n", 955 device_xname(amr->amr_dv), rv); 956 continue; 957 } 958 959 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 960 961 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 962 AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 963 if (rv != 0) { 964 aprint_error_dev(amr->amr_dv, "ccb_map failed (%d)\n", 965 rv); 966 amr_ccb_free(amr, ac); 967 continue; 968 } 969 970 rv = amr_ccb_wait(amr, ac); 971 amr_ccb_unmap(amr, ac); 972 if (rv != 0) { 973 aprint_error_dev(amr->amr_dv, 974 "enquiry failed (st=%d)\n", ac->ac_status); 975 continue; 976 } 977 amr_ccb_free(amr, ac); 978 979 al = amr->amr_drive; 980 for (i = 0; i < __arraycount(ae->ae_ldrv.al_state); i++, al++) { 981 if (al->al_dv == NULL) 982 continue; 983 if (al->al_state == ae->ae_ldrv.al_state[i]) 984 continue; 985 986 printf("%s: state changed: %s -> %s\n", 987 device_xname(al->al_dv), 988 amr_drive_state(al->al_state, NULL), 989 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 990 991 al->al_state = ae->ae_ldrv.al_state[i]; 992 } 993 } 994 } 995 996 /* 997 * Return a text description of a logical drive's current state. 998 */ 999 const char * 1000 amr_drive_state(int state, int *happy) 1001 { 1002 const char *str; 1003 1004 state = AMR_DRV_CURSTATE(state); 1005 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 1006 if (happy) 1007 *happy = 1; 1008 str = "status unknown"; 1009 } else { 1010 if (happy) 1011 *happy = amr_dstate[state].ds_happy; 1012 str = amr_dstate[state].ds_descr; 1013 } 1014 1015 return (str); 1016 } 1017 1018 /* 1019 * Run a generic enquiry-style command. 1020 */ 1021 static void * 1022 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 1023 u_int8_t cmdqual, void *sbuf) 1024 { 1025 struct amr_ccb *ac; 1026 u_int8_t *mb; 1027 int rv; 1028 1029 if (amr_ccb_alloc(amr, &ac) != 0) 1030 return (NULL); 1031 1032 /* Build the command proper. */ 1033 mb = (u_int8_t *)&ac->ac_cmd; 1034 mb[0] = cmd; 1035 mb[2] = cmdsub; 1036 mb[3] = cmdqual; 1037 1038 rv = amr_ccb_map(amr, ac, sbuf, AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 1039 if (rv == 0) { 1040 rv = amr_ccb_poll(amr, ac, 2000); 1041 amr_ccb_unmap(amr, ac); 1042 } 1043 amr_ccb_free(amr, ac); 1044 1045 return (rv ? NULL : sbuf); 1046 } 1047 1048 /* 1049 * Allocate and initialise a CCB. 1050 */ 1051 int 1052 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 1053 { 1054 mutex_spin_enter(&amr->amr_mutex); 1055 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 1056 mutex_spin_exit(&amr->amr_mutex); 1057 return (EAGAIN); 1058 } 1059 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 1060 mutex_spin_exit(&amr->amr_mutex); 1061 1062 return (0); 1063 } 1064 1065 /* 1066 * Free a CCB. 1067 */ 1068 void 1069 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 1070 { 1071 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 1072 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 1073 ac->ac_cmd.mb_busy = 1; 1074 ac->ac_handler = NULL; 1075 ac->ac_flags = 0; 1076 1077 mutex_spin_enter(&amr->amr_mutex); 1078 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 1079 mutex_spin_exit(&amr->amr_mutex); 1080 } 1081 1082 /* 1083 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1084 * the order that they were enqueued and try to submit their command blocks 1085 * to the controller for execution. 1086 */ 1087 void 1088 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 1089 { 1090 if (ac != NULL) { 1091 mutex_spin_enter(&amr->amr_mutex); 1092 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 1093 mutex_spin_exit(&amr->amr_mutex); 1094 } 1095 1096 while (SIMPLEQ_FIRST(&amr->amr_ccb_queue) != NULL) { 1097 mutex_spin_enter(&amr->amr_mutex); 1098 if ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1099 if ((*amr->amr_submit)(amr, ac) != 0) { 1100 mutex_spin_exit(&amr->amr_mutex); 1101 break; 1102 } 1103 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, 1104 ac_chain.simpleq); 1105 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, 1106 ac_chain.tailq); 1107 } 1108 mutex_spin_exit(&amr->amr_mutex); 1109 } 1110 } 1111 1112 /* 1113 * Map the specified CCB's data buffer onto the bus, and fill the 1114 * scatter-gather list. 1115 */ 1116 int 1117 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1118 int tflag) 1119 { 1120 struct amr_sgentry *sge; 1121 struct amr_mailbox_cmd *mb; 1122 int nsegs, i, rv, sgloff; 1123 bus_dmamap_t xfer; 1124 int dmaflag = 0; 1125 1126 xfer = ac->ac_xfer_map; 1127 1128 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1129 BUS_DMA_NOWAIT); 1130 if (rv != 0) 1131 return (rv); 1132 1133 mb = &ac->ac_cmd; 1134 ac->ac_xfer_size = size; 1135 ac->ac_flags |= (tflag & (AC_XFER_OUT | AC_XFER_IN)); 1136 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1137 1138 if (tflag & AC_XFER_OUT) 1139 dmaflag |= BUS_DMASYNC_PREWRITE; 1140 if (tflag & AC_XFER_IN) 1141 dmaflag |= BUS_DMASYNC_PREREAD; 1142 1143 /* We don't need to use a scatter/gather list for just 1 segment. */ 1144 nsegs = xfer->dm_nsegs; 1145 if (nsegs == 1) { 1146 mb->mb_nsgelem = 0; 1147 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1148 ac->ac_flags |= AC_NOSGL; 1149 } else { 1150 mb->mb_nsgelem = nsegs; 1151 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1152 1153 sge = (struct amr_sgentry *)((char *)amr->amr_sgls + sgloff); 1154 for (i = 0; i < nsegs; i++, sge++) { 1155 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1156 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1157 } 1158 } 1159 1160 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, dmaflag); 1161 1162 if ((ac->ac_flags & AC_NOSGL) == 0) 1163 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1164 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1165 1166 return (0); 1167 } 1168 1169 /* 1170 * Unmap the specified CCB's data buffer. 1171 */ 1172 void 1173 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1174 { 1175 int dmaflag = 0; 1176 1177 if (ac->ac_flags & AC_XFER_IN) 1178 dmaflag |= BUS_DMASYNC_POSTREAD; 1179 if (ac->ac_flags & AC_XFER_OUT) 1180 dmaflag |= BUS_DMASYNC_POSTWRITE; 1181 1182 if ((ac->ac_flags & AC_NOSGL) == 0) 1183 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1184 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1185 BUS_DMASYNC_POSTWRITE); 1186 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1187 dmaflag); 1188 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1189 } 1190 1191 /* 1192 * Submit a command to the controller and poll on completion. Return 1193 * non-zero on timeout or error. 1194 */ 1195 int 1196 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1197 { 1198 int rv, i; 1199 1200 mutex_spin_enter(&amr->amr_mutex); 1201 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) { 1202 mutex_spin_exit(&amr->amr_mutex); 1203 return (rv); 1204 } 1205 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1206 mutex_spin_exit(&amr->amr_mutex); 1207 1208 for (i = timo * 10; i > 0; i--) { 1209 amr_intr(amr); 1210 if ((ac->ac_flags & AC_COMPLETE) != 0) 1211 break; 1212 DELAY(100); 1213 } 1214 1215 if (i == 0) 1216 printf("%s: polled operation timed out after %d ms\n", 1217 device_xname(amr->amr_dv), timo); 1218 1219 return ((i == 0 || ac->ac_status != 0) ? EIO : 0); 1220 } 1221 1222 /* 1223 * Submit a command to the controller and sleep on completion. Return 1224 * non-zero on error. 1225 */ 1226 int 1227 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1228 { 1229 amr_ccb_enqueue(amr, ac); 1230 mutex_enter(&ac->ac_mutex); 1231 cv_wait(&ac->ac_cv, &ac->ac_mutex); 1232 mutex_exit(&ac->ac_mutex); 1233 1234 return (ac->ac_status != 0 ? EIO : 0); 1235 } 1236 1237 #if 0 1238 /* 1239 * Wait for the mailbox to become available. 1240 */ 1241 static int 1242 amr_mbox_wait(struct amr_softc *amr) 1243 { 1244 int timo; 1245 1246 for (timo = 10000; timo != 0; timo--) { 1247 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1248 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1249 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1250 break; 1251 DELAY(100); 1252 } 1253 1254 if (timo == 0) 1255 printf("%s: controller wedged\n", device_xname(amr->amr_dv)); 1256 1257 return (timo != 0 ? 0 : EAGAIN); 1258 } 1259 #endif 1260 1261 /* 1262 * Tell the controller that the mailbox contains a valid command. Must be 1263 * called with interrupts blocked. 1264 */ 1265 static int 1266 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1267 { 1268 int i = 0; 1269 u_int32_t v; 1270 1271 amr->amr_mbox->mb_poll = 0; 1272 amr->amr_mbox->mb_ack = 0; 1273 1274 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1275 sizeof(struct amr_mailbox), 1276 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1277 1278 v = amr_inl(amr, AMR_QREG_ODB); 1279 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1280 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1281 while ((amr->amr_mbox->mb_cmd.mb_busy != 0) && (i++ < 10)) { 1282 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1283 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1284 /* This is a no-op read that flushes pending mailbox updates */ 1285 v = amr_inl(amr, AMR_QREG_ODB); 1286 DELAY(1); 1287 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1288 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1289 } 1290 1291 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1292 return (EAGAIN); 1293 1294 v = amr_inl(amr, AMR_QREG_IDB); 1295 if ((v & AMR_QIDB_SUBMIT) != 0) { 1296 amr->amr_mbox->mb_cmd.mb_busy = 0; 1297 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1298 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1299 printf("%s: submit failed\n", device_xname(amr->amr_dv)); 1300 return (EAGAIN); 1301 } 1302 1303 amr->amr_mbox->mb_segment = 0; 1304 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1305 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1306 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1307 1308 ac->ac_start_time = time_uptime; 1309 ac->ac_flags |= AC_ACTIVE; 1310 1311 amr_outl(amr, AMR_QREG_IDB, 1312 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1313 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1314 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTWRITE); 1315 1316 return (0); 1317 } 1318 1319 static int 1320 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1321 { 1322 1323 amr->amr_mbox->mb_poll = 0; 1324 amr->amr_mbox->mb_ack = 0; 1325 1326 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1327 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1328 1329 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1330 return (EAGAIN); 1331 1332 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1333 amr->amr_mbox->mb_cmd.mb_busy = 0; 1334 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1335 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1336 return (EAGAIN); 1337 } 1338 1339 amr->amr_mbox->mb_segment = 0; 1340 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1341 1342 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1343 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1344 1345 ac->ac_start_time = time_uptime; 1346 ac->ac_flags |= AC_ACTIVE; 1347 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1348 1349 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1350 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTWRITE); 1351 1352 return (0); 1353 } 1354 1355 /* 1356 * Claim any work that the controller has completed; acknowledge completion, 1357 * save details of the completion in (mbsave). Must be called with 1358 * interrupts blocked. 1359 */ 1360 static int 1361 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1362 { 1363 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1364 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1365 1366 /* Work waiting for us? */ 1367 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1368 return (-1); 1369 1370 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1371 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1372 1373 /* Save the mailbox, which contains a list of completed commands. */ 1374 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1375 1376 /* Ack the interrupt and mailbox transfer. */ 1377 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1378 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1379 1380 /* 1381 * This waits for the controller to notice that we've taken the 1382 * command from it. It's very inefficient, and we shouldn't do it, 1383 * but if we remove this code, we stop completing commands under 1384 * load. 1385 * 1386 * Peter J says we shouldn't do this. The documentation says we 1387 * should. Who is right? 1388 */ 1389 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1390 DELAY(10); 1391 1392 return (0); 1393 } 1394 1395 static int 1396 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1397 { 1398 u_int8_t istat; 1399 1400 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1401 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1402 1403 /* Check for valid interrupt status. */ 1404 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1405 return (-1); 1406 1407 /* Ack the interrupt. */ 1408 amr_outb(amr, AMR_SREG_INTR, istat); 1409 1410 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1411 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1412 1413 /* Save mailbox, which contains a list of completed commands. */ 1414 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1415 1416 /* Ack mailbox transfer. */ 1417 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1418 1419 return (0); 1420 } 1421 1422 static void 1423 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1424 { 1425 int i; 1426 1427 printf("%s: ", device_xname(amr->amr_dv)); 1428 for (i = 0; i < 4; i++) 1429 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1430 printf("\n"); 1431 } 1432 1433 static int 1434 amropen(dev_t dev, int flag, int mode, struct lwp *l) 1435 { 1436 struct amr_softc *amr; 1437 1438 if ((amr = device_lookup_private(&amr_cd, minor(dev))) == NULL) 1439 return (ENXIO); 1440 if ((amr->amr_flags & AMRF_OPEN) != 0) 1441 return (EBUSY); 1442 1443 amr->amr_flags |= AMRF_OPEN; 1444 return (0); 1445 } 1446 1447 static int 1448 amrclose(dev_t dev, int flag, int mode, struct lwp *l) 1449 { 1450 struct amr_softc *amr; 1451 1452 amr = device_lookup_private(&amr_cd, minor(dev)); 1453 amr->amr_flags &= ~AMRF_OPEN; 1454 return (0); 1455 } 1456 1457 /* used below to correct for a firmware bug */ 1458 static unsigned long 1459 amrioctl_buflen(unsigned long len) 1460 { 1461 if (len <= 4 * 1024) 1462 return (4 * 1024); 1463 if (len <= 8 * 1024) 1464 return (8 * 1024); 1465 if (len <= 32 * 1024) 1466 return (32 * 1024); 1467 if (len <= 64 * 1024) 1468 return (64 * 1024); 1469 return (len); 1470 } 1471 1472 static int 1473 amrioctl(dev_t dev, u_long cmd, void *data, int flag, 1474 struct lwp *l) 1475 { 1476 struct amr_softc *amr; 1477 struct amr_user_ioctl *au; 1478 struct amr_ccb *ac; 1479 struct amr_mailbox_ioctl *mbi; 1480 unsigned long au_length; 1481 uint8_t *au_cmd; 1482 int error; 1483 void *dp = NULL, *au_buffer; 1484 1485 amr = device_lookup_private(&amr_cd, minor(dev)); 1486 1487 /* This should be compatible with the FreeBSD interface */ 1488 1489 switch (cmd) { 1490 case AMR_IO_VERSION: 1491 *(int *)data = AMR_IO_VERSION_NUMBER; 1492 return 0; 1493 case AMR_IO_COMMAND: 1494 error = kauth_authorize_device_passthru(l->l_cred, dev, 1495 KAUTH_REQ_DEVICE_RAWIO_PASSTHRU_ALL, data); 1496 if (error) 1497 return (error); 1498 1499 au = (struct amr_user_ioctl *)data; 1500 au_cmd = au->au_cmd; 1501 au_buffer = au->au_buffer; 1502 au_length = au->au_length; 1503 break; 1504 default: 1505 return ENOTTY; 1506 } 1507 1508 if (au_cmd[0] == AMR_CMD_PASS) { 1509 /* not yet */ 1510 return EOPNOTSUPP; 1511 } 1512 1513 if (au_length <= 0 || au_length > device_maxphys(amr->amr_dv) || 1514 au_cmd[0] == 0x06) 1515 return (EINVAL); 1516 1517 /* 1518 * allocate kernel memory for data, doing I/O directly to user 1519 * buffer isn't that easy. Correct allocation size for a bug 1520 * in at least some versions of the device firmware, by using 1521 * the amrioctl_buflen() function, defined above. 1522 */ 1523 dp = malloc(amrioctl_buflen(au_length), M_DEVBUF, M_WAITOK|M_ZERO); 1524 if (dp == NULL) 1525 return ENOMEM; 1526 if ((error = copyin(au_buffer, dp, au_length)) != 0) 1527 goto out; 1528 1529 /* direct command to controller */ 1530 while (amr_ccb_alloc(amr, &ac) != 0) { 1531 mutex_enter(&thread_mutex); 1532 error = cv_timedwait_sig(&thread_cv, &thread_mutex, hz); 1533 mutex_exit(&thread_mutex); 1534 if (error == EINTR) 1535 goto out; 1536 } 1537 1538 mbi = (struct amr_mailbox_ioctl *)&ac->ac_cmd; 1539 mbi->mb_command = au_cmd[0]; 1540 mbi->mb_channel = au_cmd[1]; 1541 mbi->mb_param = au_cmd[2]; 1542 mbi->mb_pad[0] = au_cmd[3]; 1543 mbi->mb_drive = au_cmd[4]; 1544 error = amr_ccb_map(amr, ac, dp, (int)au_length, 1545 AC_XFER_IN | AC_XFER_OUT); 1546 if (error == 0) { 1547 error = amr_ccb_wait(amr, ac); 1548 amr_ccb_unmap(amr, ac); 1549 if (error == 0) 1550 error = copyout(dp, au_buffer, au_length); 1551 1552 } 1553 amr_ccb_free(amr, ac); 1554 out: 1555 free(dp, M_DEVBUF); 1556 return (error); 1557 } 1558 1559 MODULE(MODULE_CLASS_DRIVER, amr, "pci"); 1560 1561 #ifdef _MODULE 1562 #include "ioconf.c" 1563 #endif 1564 1565 static int 1566 amr_modcmd(modcmd_t cmd, void *opaque) 1567 { 1568 int error = 0; 1569 1570 #ifdef _MODULE 1571 switch (cmd) { 1572 case MODULE_CMD_INIT: 1573 error = config_init_component(cfdriver_ioconf_amr, 1574 cfattach_ioconf_amr, cfdata_ioconf_amr); 1575 break; 1576 case MODULE_CMD_FINI: 1577 error = config_fini_component(cfdriver_ioconf_amr, 1578 cfattach_ioconf_amr, cfdata_ioconf_amr); 1579 break; 1580 default: 1581 error = ENOTTY; 1582 break; 1583 } 1584 #endif 1585 1586 return error; 1587 } 1588 1589
Indexes created Thu Oct 02 14:10:14 GMT 2025