amr.c revision 1.65
1 /* $NetBSD: amr.c,v 1.65 2019/11/10 21:16:36 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999,2000 Michael Smith 34 * Copyright (c) 2000 BSDi 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 * 58 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 59 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 60 */ 61 62 /* 63 * Driver for AMI RAID controllers. 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.65 2019/11/10 21:16:36 chs Exp $"); 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/kernel.h> 72 #include <sys/device.h> 73 #include <sys/queue.h> 74 #include <sys/proc.h> 75 #include <sys/buf.h> 76 #include <sys/malloc.h> 77 #include <sys/conf.h> 78 #include <sys/kthread.h> 79 #include <sys/kauth.h> 80 #include <sys/mutex.h> 81 #include <sys/condvar.h> 82 #include <sys/module.h> 83 84 #include <machine/endian.h> 85 #include <sys/bus.h> 86 87 #include <dev/pci/pcidevs.h> 88 #include <dev/pci/pcivar.h> 89 #include <dev/pci/amrreg.h> 90 #include <dev/pci/amrvar.h> 91 #include <dev/pci/amrio.h> 92 93 #include "locators.h" 94 95 #include "ioconf.h" 96 97 static void amr_attach(device_t, device_t, void *); 98 static void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 99 static void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, 100 void *); 101 static int amr_init(struct amr_softc *, const char *, 102 struct pci_attach_args *pa); 103 static int amr_intr(void *); 104 static int amr_match(device_t, cfdata_t, void *); 105 static int amr_rescan(device_t, const char *, const int *); 106 static int amr_print(void *, const char *); 107 static void amr_shutdown(void *); 108 static void amr_teardown(struct amr_softc *); 109 static void amr_quartz_thread(void *); 110 static void amr_std_thread(void *); 111 112 static int amr_quartz_get_work(struct amr_softc *, 113 struct amr_mailbox_resp *); 114 static int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 115 static int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 116 static int amr_std_submit(struct amr_softc *, struct amr_ccb *); 117 118 static dev_type_open(amropen); 119 static dev_type_close(amrclose); 120 static dev_type_ioctl(amrioctl); 121 122 CFATTACH_DECL3_NEW(amr, sizeof(struct amr_softc), 123 amr_match, amr_attach, NULL, NULL, amr_rescan, NULL, 0); 124 125 const struct cdevsw amr_cdevsw = { 126 .d_open = amropen, 127 .d_close = amrclose, 128 .d_read = noread, 129 .d_write = nowrite, 130 .d_ioctl = amrioctl, 131 .d_stop = nostop, 132 .d_tty = notty, 133 .d_poll = nopoll, 134 .d_mmap = nommap, 135 .d_kqfilter = nokqfilter, 136 .d_discard = nodiscard, 137 .d_flag = D_OTHER 138 }; 139 140 extern struct cfdriver amr_cd; 141 142 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 143 #define AT_SIG 0x02 /* Check for signature */ 144 145 static struct amr_pci_type { 146 u_short apt_vendor; 147 u_short apt_product; 148 u_short apt_flags; 149 } const amr_pci_type[] = { 150 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 151 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 152 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 153 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 157 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 158 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 159 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 160 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4ESI, AT_QUARTZ }, 161 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_PERC_4SC, AT_QUARTZ }, 162 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 163 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 164 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 165 }; 166 167 static struct amr_typestr { 168 const char *at_str; 169 int at_sig; 170 } const amr_typestr[] = { 171 { "Series 431", AMR_SIG_431 }, 172 { "Series 438", AMR_SIG_438 }, 173 { "Series 466", AMR_SIG_466 }, 174 { "Series 467", AMR_SIG_467 }, 175 { "Series 490", AMR_SIG_490 }, 176 { "Series 762", AMR_SIG_762 }, 177 { "HP NetRAID (T5)", AMR_SIG_T5 }, 178 { "HP NetRAID (T7)", AMR_SIG_T7 }, 179 }; 180 181 static struct { 182 const char *ds_descr; 183 int ds_happy; 184 } const amr_dstate[] = { 185 { "offline", 0 }, 186 { "degraded", 1 }, 187 { "optimal", 1 }, 188 { "online", 1 }, 189 { "failed", 0 }, 190 { "rebuilding", 1 }, 191 { "hotspare", 0 }, 192 }; 193 194 static void *amr_sdh; 195 196 static kcondvar_t thread_cv; 197 static kmutex_t thread_mutex; 198 199 static int amr_max_segs; 200 int amr_max_xfer; 201 202 static inline u_int8_t 203 amr_inb(struct amr_softc *amr, int off) 204 { 205 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 206 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 207 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 208 } 209 210 static inline u_int32_t 211 amr_inl(struct amr_softc *amr, int off) 212 { 213 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 214 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 215 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 216 } 217 218 static inline void 219 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 220 { 221 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 222 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 223 BUS_SPACE_BARRIER_WRITE); 224 } 225 226 static inline void 227 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 228 { 229 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 230 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 231 BUS_SPACE_BARRIER_WRITE); 232 } 233 234 /* 235 * Match a supported device. 236 */ 237 static int 238 amr_match(device_t parent, cfdata_t match, void *aux) 239 { 240 struct pci_attach_args *pa; 241 pcireg_t s; 242 int i; 243 244 pa = (struct pci_attach_args *)aux; 245 246 /* 247 * Don't match the device if it's operating in I2O mode. In this 248 * case it should be handled by the `iop' driver. 249 */ 250 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 251 return (0); 252 253 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 254 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 255 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 256 break; 257 258 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 259 return (0); 260 261 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 262 return (1); 263 264 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 265 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 266 } 267 268 /* 269 * Attach a supported device. 270 */ 271 static void 272 amr_attach(device_t parent, device_t self, void *aux) 273 { 274 struct pci_attach_args *pa; 275 const struct amr_pci_type *apt; 276 struct amr_softc *amr; 277 pci_chipset_tag_t pc; 278 pci_intr_handle_t ih; 279 const char *intrstr; 280 pcireg_t reg; 281 int rseg, i, size, rv, memreg, ioreg; 282 struct amr_ccb *ac; 283 char intrbuf[PCI_INTRSTR_LEN]; 284 285 aprint_naive(": RAID controller\n"); 286 287 amr = device_private(self); 288 amr->amr_dv = self; 289 290 mutex_init(&amr->amr_mutex, MUTEX_DEFAULT, IPL_BIO); 291 292 pa = (struct pci_attach_args *)aux; 293 pc = pa->pa_pc; 294 295 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 296 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 297 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 298 break; 299 apt = amr_pci_type + i; 300 301 memreg = ioreg = 0; 302 for (i = 0x10; i <= 0x14; i += 4) { 303 reg = pci_conf_read(pc, pa->pa_tag, i); 304 switch (PCI_MAPREG_TYPE(reg)) { 305 case PCI_MAPREG_TYPE_MEM: 306 if (PCI_MAPREG_MEM_SIZE(reg) != 0) 307 memreg = i; 308 break; 309 case PCI_MAPREG_TYPE_IO: 310 if (PCI_MAPREG_IO_SIZE(reg) != 0) 311 ioreg = i; 312 break; 313 } 314 } 315 316 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 317 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 318 ; 319 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 320 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 321 ; 322 else { 323 aprint_error("can't map control registers\n"); 324 amr_teardown(amr); 325 return; 326 } 327 328 amr->amr_flags |= AMRF_PCI_REGS; 329 amr->amr_dmat = pa->pa_dmat; 330 amr->amr_pc = pa->pa_pc; 331 332 /* Enable the device. */ 333 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 334 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 335 reg | PCI_COMMAND_MASTER_ENABLE); 336 337 /* Map and establish the interrupt. */ 338 if (pci_intr_map(pa, &ih)) { 339 aprint_error("can't map interrupt\n"); 340 amr_teardown(amr); 341 return; 342 } 343 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 344 amr->amr_ih = pci_intr_establish_xname(pc, ih, IPL_BIO, amr_intr, amr, 345 device_xname(self)); 346 if (amr->amr_ih == NULL) { 347 aprint_error("can't establish interrupt"); 348 if (intrstr != NULL) 349 aprint_error(" at %s", intrstr); 350 aprint_error("\n"); 351 amr_teardown(amr); 352 return; 353 } 354 amr->amr_flags |= AMRF_PCI_INTR; 355 356 /* 357 * Allocate space for the mailbox and S/G lists. Some controllers 358 * don't like S/G lists to be located below 0x2000, so we allocate 359 * enough slop to enable us to compensate. 360 * 361 * The standard mailbox structure needs to be aligned on a 16-byte 362 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 363 * size, which precedes the standard mailbox. 364 */ 365 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 366 amr->amr_dmasize = size; 367 368 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, 369 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 370 aprint_error_dev(amr->amr_dv, 371 "unable to allocate buffer, rv = %d\n", rv); 372 amr_teardown(amr); 373 return; 374 } 375 amr->amr_flags |= AMRF_DMA_ALLOC; 376 377 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 378 (void **)&amr->amr_mbox, 379 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 380 aprint_error_dev(amr->amr_dv, "unable to map buffer, rv = %d\n", 381 rv); 382 amr_teardown(amr); 383 return; 384 } 385 amr->amr_flags |= AMRF_DMA_MAP; 386 387 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 388 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 389 aprint_error_dev(amr->amr_dv, 390 "unable to create buffer DMA map, rv = %d\n", rv); 391 amr_teardown(amr); 392 return; 393 } 394 amr->amr_flags |= AMRF_DMA_CREATE; 395 396 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 397 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 398 aprint_error_dev(amr->amr_dv, 399 "unable to load buffer DMA map, rv = %d\n", rv); 400 amr_teardown(amr); 401 return; 402 } 403 amr->amr_flags |= AMRF_DMA_LOAD; 404 405 memset(amr->amr_mbox, 0, size); 406 407 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 408 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 409 amr->amr_sgls = (struct amr_sgentry *)((char *)amr->amr_mbox + 410 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 411 412 /* 413 * Allocate and initalise the command control blocks. 414 */ 415 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_WAITOK | M_ZERO); 416 amr->amr_ccbs = ac; 417 SLIST_INIT(&amr->amr_ccb_freelist); 418 TAILQ_INIT(&amr->amr_ccb_active); 419 amr->amr_flags |= AMRF_CCBS; 420 421 if (amr_max_xfer == 0) { 422 amr_max_xfer = uimin(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); 423 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 424 } 425 426 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 427 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 428 amr_max_segs, amr_max_xfer, 0, 429 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 430 if (rv != 0) 431 break; 432 433 ac->ac_ident = i; 434 cv_init(&ac->ac_cv, "amr1ccb"); 435 mutex_init(&ac->ac_mutex, MUTEX_DEFAULT, IPL_NONE); 436 amr_ccb_free(amr, ac); 437 } 438 if (i != AMR_MAX_CMDS) { 439 aprint_error_dev(amr->amr_dv, "memory exhausted\n"); 440 amr_teardown(amr); 441 return; 442 } 443 444 /* 445 * Take care of model-specific tasks. 446 */ 447 if ((apt->apt_flags & AT_QUARTZ) != 0) { 448 amr->amr_submit = amr_quartz_submit; 449 amr->amr_get_work = amr_quartz_get_work; 450 } else { 451 amr->amr_submit = amr_std_submit; 452 amr->amr_get_work = amr_std_get_work; 453 454 /* Notify the controller of the mailbox location. */ 455 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 456 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 457 458 /* Clear outstanding interrupts and enable interrupts. */ 459 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 460 amr_outb(amr, AMR_SREG_TOGL, 461 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 462 } 463 464 /* 465 * Retrieve parameters, and tell the world about us. 466 */ 467 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_WAITOK); 468 amr->amr_flags |= AMRF_ENQBUF; 469 amr->amr_maxqueuecnt = i; 470 aprint_normal(": AMI RAID "); 471 if (amr_init(amr, intrstr, pa) != 0) { 472 amr_teardown(amr); 473 return; 474 } 475 476 /* 477 * Cap the maximum number of outstanding commands. AMI's Linux 478 * driver doesn't trust the controller's reported value, and lockups 479 * have been seen when we do. 480 */ 481 amr->amr_maxqueuecnt = uimin(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 482 if (amr->amr_maxqueuecnt > i) 483 amr->amr_maxqueuecnt = i; 484 485 /* Set our `shutdownhook' before we start any device activity. */ 486 if (amr_sdh == NULL) 487 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 488 489 /* Attach sub-devices. */ 490 amr_rescan(self, "amr", 0); 491 492 SIMPLEQ_INIT(&amr->amr_ccb_queue); 493 494 cv_init(&thread_cv, "amrwdog"); 495 mutex_init(&thread_mutex, MUTEX_DEFAULT, IPL_NONE); 496 497 if ((apt->apt_flags & AT_QUARTZ) == 0) { 498 rv = kthread_create(PRI_NONE, KTHREAD_MPSAFE, NULL, 499 amr_std_thread, amr, &amr->amr_thread, 500 "%s", device_xname(amr->amr_dv)); 501 } else { 502 rv = kthread_create(PRI_NONE, KTHREAD_MPSAFE, NULL, 503 amr_quartz_thread, amr, &amr->amr_thread, 504 "%s", device_xname(amr->amr_dv)); 505 } 506 if (rv != 0) 507 aprint_error_dev(amr->amr_dv, "unable to create thread (%d)", 508 rv); 509 else 510 amr->amr_flags |= AMRF_THREAD; 511 } 512 513 static int 514 amr_rescan(device_t self, const char *attr, const int *flags) 515 { 516 int j; 517 int locs[AMRCF_NLOCS]; 518 struct amr_attach_args amra; 519 struct amr_softc *amr; 520 521 amr = device_private(self); 522 for (j = 0; j < amr->amr_numdrives; j++) { 523 if (amr->amr_drive[j].al_dv) 524 continue; 525 if (amr->amr_drive[j].al_size == 0) 526 continue; 527 amra.amra_unit = j; 528 529 locs[AMRCF_UNIT] = j; 530 531 amr->amr_drive[j].al_dv = config_found_sm_loc(amr->amr_dv, 532 attr, locs, &amra, amr_print, config_stdsubmatch); 533 } 534 return 0; 535 } 536 537 /* 538 * Free up resources. 539 */ 540 static void 541 amr_teardown(struct amr_softc *amr) 542 { 543 struct amr_ccb *ac; 544 int fl; 545 546 fl = amr->amr_flags; 547 548 if ((fl & AMRF_THREAD) != 0) { 549 amr->amr_flags |= AMRF_THREAD_EXIT; 550 mutex_enter(&thread_mutex); 551 cv_broadcast(&thread_cv); 552 mutex_exit(&thread_mutex); 553 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 554 mutex_enter(&thread_mutex); 555 cv_wait(&thread_cv, &thread_mutex); 556 mutex_exit(&thread_mutex); 557 } 558 } 559 if ((fl & AMRF_CCBS) != 0) { 560 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 561 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 562 } 563 free(amr->amr_ccbs, M_DEVBUF); 564 } 565 if ((fl & AMRF_ENQBUF) != 0) 566 free(amr->amr_enqbuf, M_DEVBUF); 567 if ((fl & AMRF_DMA_LOAD) != 0) 568 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 569 if ((fl & AMRF_DMA_MAP) != 0) 570 bus_dmamem_unmap(amr->amr_dmat, (void *)amr->amr_mbox, 571 amr->amr_dmasize); 572 if ((fl & AMRF_DMA_ALLOC) != 0) 573 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 574 if ((fl & AMRF_DMA_CREATE) != 0) 575 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 576 if ((fl & AMRF_PCI_INTR) != 0) 577 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 578 if ((fl & AMRF_PCI_REGS) != 0) 579 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 580 } 581 582 /* 583 * Print autoconfiguration message for a sub-device. 584 */ 585 static int 586 amr_print(void *aux, const char *pnp) 587 { 588 struct amr_attach_args *amra; 589 590 amra = (struct amr_attach_args *)aux; 591 592 if (pnp != NULL) 593 aprint_normal("block device at %s", pnp); 594 aprint_normal(" unit %d", amra->amra_unit); 595 return (UNCONF); 596 } 597 598 /* 599 * Retrieve operational parameters and describe the controller. 600 */ 601 static int 602 amr_init(struct amr_softc *amr, const char *intrstr, 603 struct pci_attach_args *pa) 604 { 605 struct amr_adapter_info *aa; 606 struct amr_prodinfo *ap; 607 struct amr_enquiry *ae; 608 struct amr_enquiry3 *aex; 609 const char *prodstr; 610 u_int i, sig, ishp; 611 char sbuf[64]; 612 613 /* 614 * Try to get 40LD product info, which tells us what the card is 615 * labelled as. 616 */ 617 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 618 amr->amr_enqbuf); 619 if (ap != NULL) { 620 aprint_normal("<%.80s>\n", ap->ap_product); 621 if (intrstr != NULL) 622 aprint_normal_dev(amr->amr_dv, "interrupting at %s\n", 623 intrstr); 624 aprint_normal_dev(amr->amr_dv, 625 "firmware %.16s, BIOS %.16s, %dMB RAM\n", 626 ap->ap_firmware, ap->ap_bios, le16toh(ap->ap_memsize)); 627 628 amr->amr_maxqueuecnt = ap->ap_maxio; 629 630 /* 631 * Fetch and record state of logical drives. 632 */ 633 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 634 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 635 if (aex == NULL) { 636 aprint_error_dev(amr->amr_dv, "ENQUIRY3 failed\n"); 637 return (-1); 638 } 639 640 if (aex->ae_numldrives > __arraycount(aex->ae_drivestate)) { 641 aprint_error_dev(amr->amr_dv, "Inquiry returned more " 642 "drives (%d) than the array can handle (%zu)\n", 643 aex->ae_numldrives, 644 __arraycount(aex->ae_drivestate)); 645 aex->ae_numldrives = __arraycount(aex->ae_drivestate); 646 } 647 if (aex->ae_numldrives > AMR_MAX_UNITS) { 648 aprint_error_dev(amr->amr_dv, 649 "adjust AMR_MAX_UNITS to %d (currently %d)\n", 650 AMR_MAX_UNITS, amr->amr_numdrives); 651 amr->amr_numdrives = AMR_MAX_UNITS; 652 } else 653 amr->amr_numdrives = aex->ae_numldrives; 654 655 for (i = 0; i < amr->amr_numdrives; i++) { 656 amr->amr_drive[i].al_size = 657 le32toh(aex->ae_drivesize[i]); 658 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 659 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 660 } 661 662 return (0); 663 } 664 665 /* 666 * Try 8LD extended ENQUIRY to get the controller signature. Once 667 * found, search for a product description. 668 */ 669 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 670 if (ae != NULL) { 671 i = 0; 672 sig = le32toh(ae->ae_signature); 673 674 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 675 if (amr_typestr[i].at_sig == sig) 676 break; 677 i++; 678 } 679 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 680 snprintf(sbuf, sizeof(sbuf), 681 "unknown ENQUIRY2 sig (0x%08x)", sig); 682 prodstr = sbuf; 683 } else 684 prodstr = amr_typestr[i].at_str; 685 } else { 686 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 687 if (ae == NULL) { 688 aprint_error_dev(amr->amr_dv, 689 "unsupported controller\n"); 690 return (-1); 691 } 692 693 switch (PCI_PRODUCT(pa->pa_id)) { 694 case PCI_PRODUCT_AMI_MEGARAID: 695 prodstr = "Series 428"; 696 break; 697 case PCI_PRODUCT_AMI_MEGARAID2: 698 prodstr = "Series 434"; 699 break; 700 default: 701 snprintf(sbuf, sizeof(sbuf), 702 "unknown PCI dev (0x%04x)", 703 PCI_PRODUCT(pa->pa_id)); 704 prodstr = sbuf; 705 break; 706 } 707 } 708 709 /* 710 * HP NetRaid controllers have a special encoding of the firmware 711 * and BIOS versions. The AMI version seems to have it as strings 712 * whereas the HP version does it with a leading uppercase character 713 * and two binary numbers. 714 */ 715 aa = &ae->ae_adapter; 716 717 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 718 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 719 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 720 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 721 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 722 /* The AMI 438 is a NetRaid 3si in HP-land. */ 723 prodstr = "HP NetRaid 3si"; 724 } 725 ishp = 1; 726 } else 727 ishp = 0; 728 729 aprint_normal("<%s>\n", prodstr); 730 if (intrstr != NULL) 731 aprint_normal_dev(amr->amr_dv, "interrupting at %s\n", 732 intrstr); 733 734 if (ishp) 735 aprint_normal_dev(amr->amr_dv, "firmware <%c.%02d.%02d>, " 736 "BIOS <%c.%02d.%02d>, %dMB RAM\n", aa->aa_firmware[2], 737 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 738 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 739 else 740 aprint_normal_dev(amr->amr_dv, "firmware <%.4s>, BIOS <%.4s>, " 741 "%dMB RAM\n", aa->aa_firmware, aa->aa_bios, 742 aa->aa_memorysize); 743 744 amr->amr_maxqueuecnt = aa->aa_maxio; 745 746 /* 747 * Record state of logical drives. 748 */ 749 if (ae->ae_ldrv.al_numdrives > __arraycount(ae->ae_ldrv.al_size)) { 750 aprint_error_dev(amr->amr_dv, "Inquiry returned more drives " 751 "(%d) than the array can handle (%zu)\n", 752 ae->ae_ldrv.al_numdrives, 753 __arraycount(ae->ae_ldrv.al_size)); 754 ae->ae_ldrv.al_numdrives = __arraycount(ae->ae_ldrv.al_size); 755 } 756 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 757 aprint_error_dev(amr->amr_dv, 758 "adjust AMR_MAX_UNITS to %d (currently %d)\n", 759 ae->ae_ldrv.al_numdrives, AMR_MAX_UNITS); 760 amr->amr_numdrives = AMR_MAX_UNITS; 761 } else 762 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 763 764 for (i = 0; i < amr->amr_numdrives; i++) { 765 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 766 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 767 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 768 } 769 770 return (0); 771 } 772 773 /* 774 * Flush the internal cache on each configured controller. Called at 775 * shutdown time. 776 */ 777 static void 778 amr_shutdown(void *cookie) 779 { 780 extern struct cfdriver amr_cd; 781 struct amr_softc *amr; 782 struct amr_ccb *ac; 783 int i, rv; 784 785 for (i = 0; i < amr_cd.cd_ndevs; i++) { 786 if ((amr = device_lookup_private(&amr_cd, i)) == NULL) 787 continue; 788 789 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 790 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 791 rv = amr_ccb_poll(amr, ac, 30000); 792 amr_ccb_free(amr, ac); 793 } 794 if (rv != 0) 795 aprint_error_dev(amr->amr_dv, 796 "unable to flush cache (%d)\n", rv); 797 } 798 } 799 800 /* 801 * Interrupt service routine. 802 */ 803 static int 804 amr_intr(void *cookie) 805 { 806 struct amr_softc *amr; 807 struct amr_ccb *ac; 808 struct amr_mailbox_resp mbox; 809 u_int i, forus, idx; 810 811 amr = cookie; 812 forus = 0; 813 814 mutex_spin_enter(&amr->amr_mutex); 815 816 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 817 /* Iterate over completed commands in this result. */ 818 for (i = 0; i < mbox.mb_nstatus; i++) { 819 idx = mbox.mb_completed[i] - 1; 820 ac = amr->amr_ccbs + idx; 821 822 if (idx >= amr->amr_maxqueuecnt) { 823 printf("%s: bad status (bogus ID: %u=%u)\n", 824 device_xname(amr->amr_dv), i, idx); 825 continue; 826 } 827 828 if ((ac->ac_flags & AC_ACTIVE) == 0) { 829 printf("%s: bad status (not active; 0x04%x)\n", 830 device_xname(amr->amr_dv), ac->ac_flags); 831 continue; 832 } 833 834 ac->ac_status = mbox.mb_status; 835 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 836 AC_COMPLETE; 837 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 838 839 if ((ac->ac_flags & AC_MOAN) != 0) 840 printf("%s: ccb %d completed\n", 841 device_xname(amr->amr_dv), ac->ac_ident); 842 843 /* Pass notification to upper layers. */ 844 mutex_spin_exit(&amr->amr_mutex); 845 if (ac->ac_handler != NULL) { 846 (*ac->ac_handler)(ac); 847 } else { 848 mutex_enter(&ac->ac_mutex); 849 cv_signal(&ac->ac_cv); 850 mutex_exit(&ac->ac_mutex); 851 } 852 mutex_spin_enter(&amr->amr_mutex); 853 } 854 forus = 1; 855 } 856 857 mutex_spin_exit(&amr->amr_mutex); 858 859 if (forus) 860 amr_ccb_enqueue(amr, NULL); 861 862 return (forus); 863 } 864 865 /* 866 * Watchdog thread. 867 */ 868 static void 869 amr_quartz_thread(void *cookie) 870 { 871 struct amr_softc *amr; 872 struct amr_ccb *ac; 873 874 amr = cookie; 875 876 for (;;) { 877 mutex_enter(&thread_mutex); 878 cv_timedwait(&thread_cv, &thread_mutex, AMR_WDOG_TICKS); 879 mutex_exit(&thread_mutex); 880 881 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 882 amr->amr_flags ^= AMRF_THREAD_EXIT; 883 mutex_enter(&thread_mutex); 884 cv_signal(&thread_cv); 885 mutex_exit(&thread_mutex); 886 kthread_exit(0); 887 } 888 889 if (amr_intr(amr) == 0) 890 amr_ccb_enqueue(amr, NULL); 891 892 mutex_spin_enter(&amr->amr_mutex); 893 ac = TAILQ_FIRST(&amr->amr_ccb_active); 894 while (ac != NULL) { 895 if (ac->ac_start_time + AMR_TIMEOUT > time_uptime) 896 break; 897 if ((ac->ac_flags & AC_MOAN) == 0) { 898 printf("%s: ccb %d timed out; mailbox:\n", 899 device_xname(amr->amr_dv), ac->ac_ident); 900 amr_ccb_dump(amr, ac); 901 ac->ac_flags |= AC_MOAN; 902 } 903 ac = TAILQ_NEXT(ac, ac_chain.tailq); 904 } 905 mutex_spin_exit(&amr->amr_mutex); 906 } 907 } 908 909 static void 910 amr_std_thread(void *cookie) 911 { 912 struct amr_softc *amr; 913 struct amr_ccb *ac; 914 struct amr_logdrive *al; 915 struct amr_enquiry *ae; 916 int rv, i; 917 918 amr = cookie; 919 ae = amr->amr_enqbuf; 920 921 for (;;) { 922 mutex_enter(&thread_mutex); 923 cv_timedwait(&thread_cv, &thread_mutex, AMR_WDOG_TICKS); 924 mutex_exit(&thread_mutex); 925 926 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 927 amr->amr_flags ^= AMRF_THREAD_EXIT; 928 mutex_enter(&thread_mutex); 929 cv_signal(&thread_cv); 930 mutex_exit(&thread_mutex); 931 kthread_exit(0); 932 } 933 934 if (amr_intr(amr) == 0) 935 amr_ccb_enqueue(amr, NULL); 936 937 mutex_spin_enter(&amr->amr_mutex); 938 ac = TAILQ_FIRST(&amr->amr_ccb_active); 939 while (ac != NULL) { 940 if (ac->ac_start_time + AMR_TIMEOUT > time_uptime) 941 break; 942 if ((ac->ac_flags & AC_MOAN) == 0) { 943 printf("%s: ccb %d timed out; mailbox:\n", 944 device_xname(amr->amr_dv), ac->ac_ident); 945 amr_ccb_dump(amr, ac); 946 ac->ac_flags |= AC_MOAN; 947 } 948 ac = TAILQ_NEXT(ac, ac_chain.tailq); 949 } 950 mutex_spin_exit(&amr->amr_mutex); 951 952 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 953 printf("%s: ccb_alloc failed (%d)\n", 954 device_xname(amr->amr_dv), rv); 955 continue; 956 } 957 958 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 959 960 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 961 AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 962 if (rv != 0) { 963 aprint_error_dev(amr->amr_dv, "ccb_map failed (%d)\n", 964 rv); 965 amr_ccb_free(amr, ac); 966 continue; 967 } 968 969 rv = amr_ccb_wait(amr, ac); 970 amr_ccb_unmap(amr, ac); 971 if (rv != 0) { 972 aprint_error_dev(amr->amr_dv, 973 "enquiry failed (st=%d)\n", ac->ac_status); 974 continue; 975 } 976 amr_ccb_free(amr, ac); 977 978 al = amr->amr_drive; 979 for (i = 0; i < __arraycount(ae->ae_ldrv.al_state); i++, al++) { 980 if (al->al_dv == NULL) 981 continue; 982 if (al->al_state == ae->ae_ldrv.al_state[i]) 983 continue; 984 985 printf("%s: state changed: %s -> %s\n", 986 device_xname(al->al_dv), 987 amr_drive_state(al->al_state, NULL), 988 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 989 990 al->al_state = ae->ae_ldrv.al_state[i]; 991 } 992 } 993 } 994 995 /* 996 * Return a text description of a logical drive's current state. 997 */ 998 const char * 999 amr_drive_state(int state, int *happy) 1000 { 1001 const char *str; 1002 1003 state = AMR_DRV_CURSTATE(state); 1004 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 1005 if (happy) 1006 *happy = 1; 1007 str = "status unknown"; 1008 } else { 1009 if (happy) 1010 *happy = amr_dstate[state].ds_happy; 1011 str = amr_dstate[state].ds_descr; 1012 } 1013 1014 return (str); 1015 } 1016 1017 /* 1018 * Run a generic enquiry-style command. 1019 */ 1020 static void * 1021 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 1022 u_int8_t cmdqual, void *sbuf) 1023 { 1024 struct amr_ccb *ac; 1025 u_int8_t *mb; 1026 int rv; 1027 1028 if (amr_ccb_alloc(amr, &ac) != 0) 1029 return (NULL); 1030 1031 /* Build the command proper. */ 1032 mb = (u_int8_t *)&ac->ac_cmd; 1033 mb[0] = cmd; 1034 mb[2] = cmdsub; 1035 mb[3] = cmdqual; 1036 1037 rv = amr_ccb_map(amr, ac, sbuf, AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 1038 if (rv == 0) { 1039 rv = amr_ccb_poll(amr, ac, 2000); 1040 amr_ccb_unmap(amr, ac); 1041 } 1042 amr_ccb_free(amr, ac); 1043 1044 return (rv ? NULL : sbuf); 1045 } 1046 1047 /* 1048 * Allocate and initialise a CCB. 1049 */ 1050 int 1051 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 1052 { 1053 mutex_spin_enter(&amr->amr_mutex); 1054 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 1055 mutex_spin_exit(&amr->amr_mutex); 1056 return (EAGAIN); 1057 } 1058 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 1059 mutex_spin_exit(&amr->amr_mutex); 1060 1061 return (0); 1062 } 1063 1064 /* 1065 * Free a CCB. 1066 */ 1067 void 1068 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 1069 { 1070 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 1071 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 1072 ac->ac_cmd.mb_busy = 1; 1073 ac->ac_handler = NULL; 1074 ac->ac_flags = 0; 1075 1076 mutex_spin_enter(&amr->amr_mutex); 1077 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 1078 mutex_spin_exit(&amr->amr_mutex); 1079 } 1080 1081 /* 1082 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1083 * the order that they were enqueued and try to submit their command blocks 1084 * to the controller for execution. 1085 */ 1086 void 1087 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 1088 { 1089 if (ac != NULL) { 1090 mutex_spin_enter(&amr->amr_mutex); 1091 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 1092 mutex_spin_exit(&amr->amr_mutex); 1093 } 1094 1095 while (SIMPLEQ_FIRST(&amr->amr_ccb_queue) != NULL) { 1096 mutex_spin_enter(&amr->amr_mutex); 1097 if ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1098 if ((*amr->amr_submit)(amr, ac) != 0) { 1099 mutex_spin_exit(&amr->amr_mutex); 1100 break; 1101 } 1102 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, 1103 ac_chain.simpleq); 1104 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, 1105 ac_chain.tailq); 1106 } 1107 mutex_spin_exit(&amr->amr_mutex); 1108 } 1109 } 1110 1111 /* 1112 * Map the specified CCB's data buffer onto the bus, and fill the 1113 * scatter-gather list. 1114 */ 1115 int 1116 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1117 int tflag) 1118 { 1119 struct amr_sgentry *sge; 1120 struct amr_mailbox_cmd *mb; 1121 int nsegs, i, rv, sgloff; 1122 bus_dmamap_t xfer; 1123 int dmaflag = 0; 1124 1125 xfer = ac->ac_xfer_map; 1126 1127 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1128 BUS_DMA_NOWAIT); 1129 if (rv != 0) 1130 return (rv); 1131 1132 mb = &ac->ac_cmd; 1133 ac->ac_xfer_size = size; 1134 ac->ac_flags |= (tflag & (AC_XFER_OUT | AC_XFER_IN)); 1135 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1136 1137 if (tflag & AC_XFER_OUT) 1138 dmaflag |= BUS_DMASYNC_PREWRITE; 1139 if (tflag & AC_XFER_IN) 1140 dmaflag |= BUS_DMASYNC_PREREAD; 1141 1142 /* We don't need to use a scatter/gather list for just 1 segment. */ 1143 nsegs = xfer->dm_nsegs; 1144 if (nsegs == 1) { 1145 mb->mb_nsgelem = 0; 1146 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1147 ac->ac_flags |= AC_NOSGL; 1148 } else { 1149 mb->mb_nsgelem = nsegs; 1150 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1151 1152 sge = (struct amr_sgentry *)((char *)amr->amr_sgls + sgloff); 1153 for (i = 0; i < nsegs; i++, sge++) { 1154 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1155 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1156 } 1157 } 1158 1159 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, dmaflag); 1160 1161 if ((ac->ac_flags & AC_NOSGL) == 0) 1162 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1163 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1164 1165 return (0); 1166 } 1167 1168 /* 1169 * Unmap the specified CCB's data buffer. 1170 */ 1171 void 1172 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1173 { 1174 int dmaflag = 0; 1175 1176 if (ac->ac_flags & AC_XFER_IN) 1177 dmaflag |= BUS_DMASYNC_POSTREAD; 1178 if (ac->ac_flags & AC_XFER_OUT) 1179 dmaflag |= BUS_DMASYNC_POSTWRITE; 1180 1181 if ((ac->ac_flags & AC_NOSGL) == 0) 1182 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1183 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1184 BUS_DMASYNC_POSTWRITE); 1185 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1186 dmaflag); 1187 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1188 } 1189 1190 /* 1191 * Submit a command to the controller and poll on completion. Return 1192 * non-zero on timeout or error. 1193 */ 1194 int 1195 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1196 { 1197 int rv, i; 1198 1199 mutex_spin_enter(&amr->amr_mutex); 1200 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) { 1201 mutex_spin_exit(&amr->amr_mutex); 1202 return (rv); 1203 } 1204 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1205 mutex_spin_exit(&amr->amr_mutex); 1206 1207 for (i = timo * 10; i > 0; i--) { 1208 amr_intr(amr); 1209 if ((ac->ac_flags & AC_COMPLETE) != 0) 1210 break; 1211 DELAY(100); 1212 } 1213 1214 if (i == 0) 1215 printf("%s: polled operation timed out after %d ms\n", 1216 device_xname(amr->amr_dv), timo); 1217 1218 return ((i == 0 || ac->ac_status != 0) ? EIO : 0); 1219 } 1220 1221 /* 1222 * Submit a command to the controller and sleep on completion. Return 1223 * non-zero on error. 1224 */ 1225 int 1226 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1227 { 1228 amr_ccb_enqueue(amr, ac); 1229 mutex_enter(&ac->ac_mutex); 1230 cv_wait(&ac->ac_cv, &ac->ac_mutex); 1231 mutex_exit(&ac->ac_mutex); 1232 1233 return (ac->ac_status != 0 ? EIO : 0); 1234 } 1235 1236 #if 0 1237 /* 1238 * Wait for the mailbox to become available. 1239 */ 1240 static int 1241 amr_mbox_wait(struct amr_softc *amr) 1242 { 1243 int timo; 1244 1245 for (timo = 10000; timo != 0; timo--) { 1246 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1247 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1248 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1249 break; 1250 DELAY(100); 1251 } 1252 1253 if (timo == 0) 1254 printf("%s: controller wedged\n", device_xname(amr->amr_dv)); 1255 1256 return (timo != 0 ? 0 : EAGAIN); 1257 } 1258 #endif 1259 1260 /* 1261 * Tell the controller that the mailbox contains a valid command. Must be 1262 * called with interrupts blocked. 1263 */ 1264 static int 1265 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1266 { 1267 int i = 0; 1268 u_int32_t v; 1269 1270 amr->amr_mbox->mb_poll = 0; 1271 amr->amr_mbox->mb_ack = 0; 1272 1273 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1274 sizeof(struct amr_mailbox), 1275 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1276 1277 v = amr_inl(amr, AMR_QREG_ODB); 1278 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1279 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1280 while ((amr->amr_mbox->mb_cmd.mb_busy != 0) && (i++ < 10)) { 1281 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1282 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1283 /* This is a no-op read that flushes pending mailbox updates */ 1284 v = amr_inl(amr, AMR_QREG_ODB); 1285 DELAY(1); 1286 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1287 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1288 } 1289 1290 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1291 return (EAGAIN); 1292 1293 v = amr_inl(amr, AMR_QREG_IDB); 1294 if ((v & AMR_QIDB_SUBMIT) != 0) { 1295 amr->amr_mbox->mb_cmd.mb_busy = 0; 1296 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1297 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1298 printf("%s: submit failed\n", device_xname(amr->amr_dv)); 1299 return (EAGAIN); 1300 } 1301 1302 amr->amr_mbox->mb_segment = 0; 1303 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1304 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1305 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1306 1307 ac->ac_start_time = time_uptime; 1308 ac->ac_flags |= AC_ACTIVE; 1309 1310 amr_outl(amr, AMR_QREG_IDB, 1311 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1312 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1313 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTWRITE); 1314 1315 return (0); 1316 } 1317 1318 static int 1319 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1320 { 1321 1322 amr->amr_mbox->mb_poll = 0; 1323 amr->amr_mbox->mb_ack = 0; 1324 1325 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1326 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1327 1328 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1329 return (EAGAIN); 1330 1331 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1332 amr->amr_mbox->mb_cmd.mb_busy = 0; 1333 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1334 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1335 return (EAGAIN); 1336 } 1337 1338 amr->amr_mbox->mb_segment = 0; 1339 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1340 1341 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1342 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1343 1344 ac->ac_start_time = time_uptime; 1345 ac->ac_flags |= AC_ACTIVE; 1346 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1347 1348 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1349 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTWRITE); 1350 1351 return (0); 1352 } 1353 1354 /* 1355 * Claim any work that the controller has completed; acknowledge completion, 1356 * save details of the completion in (mbsave). Must be called with 1357 * interrupts blocked. 1358 */ 1359 static int 1360 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1361 { 1362 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1363 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1364 1365 /* Work waiting for us? */ 1366 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1367 return (-1); 1368 1369 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1370 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1371 1372 /* Save the mailbox, which contains a list of completed commands. */ 1373 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1374 1375 /* Ack the interrupt and mailbox transfer. */ 1376 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1377 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1378 1379 /* 1380 * This waits for the controller to notice that we've taken the 1381 * command from it. It's very inefficient, and we shouldn't do it, 1382 * but if we remove this code, we stop completing commands under 1383 * load. 1384 * 1385 * Peter J says we shouldn't do this. The documentation says we 1386 * should. Who is right? 1387 */ 1388 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1389 DELAY(10); 1390 1391 return (0); 1392 } 1393 1394 static int 1395 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1396 { 1397 u_int8_t istat; 1398 1399 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1400 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1401 1402 /* Check for valid interrupt status. */ 1403 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1404 return (-1); 1405 1406 /* Ack the interrupt. */ 1407 amr_outb(amr, AMR_SREG_INTR, istat); 1408 1409 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1410 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1411 1412 /* Save mailbox, which contains a list of completed commands. */ 1413 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1414 1415 /* Ack mailbox transfer. */ 1416 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1417 1418 return (0); 1419 } 1420 1421 static void 1422 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1423 { 1424 int i; 1425 1426 printf("%s: ", device_xname(amr->amr_dv)); 1427 for (i = 0; i < 4; i++) 1428 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1429 printf("\n"); 1430 } 1431 1432 static int 1433 amropen(dev_t dev, int flag, int mode, struct lwp *l) 1434 { 1435 struct amr_softc *amr; 1436 1437 if ((amr = device_lookup_private(&amr_cd, minor(dev))) == NULL) 1438 return (ENXIO); 1439 if ((amr->amr_flags & AMRF_OPEN) != 0) 1440 return (EBUSY); 1441 1442 amr->amr_flags |= AMRF_OPEN; 1443 return (0); 1444 } 1445 1446 static int 1447 amrclose(dev_t dev, int flag, int mode, struct lwp *l) 1448 { 1449 struct amr_softc *amr; 1450 1451 amr = device_lookup_private(&amr_cd, minor(dev)); 1452 amr->amr_flags &= ~AMRF_OPEN; 1453 return (0); 1454 } 1455 1456 /* used below to correct for a firmware bug */ 1457 static unsigned long 1458 amrioctl_buflen(unsigned long len) 1459 { 1460 if (len <= 4 * 1024) 1461 return (4 * 1024); 1462 if (len <= 8 * 1024) 1463 return (8 * 1024); 1464 if (len <= 32 * 1024) 1465 return (32 * 1024); 1466 if (len <= 64 * 1024) 1467 return (64 * 1024); 1468 return (len); 1469 } 1470 1471 static int 1472 amrioctl(dev_t dev, u_long cmd, void *data, int flag, 1473 struct lwp *l) 1474 { 1475 struct amr_softc *amr; 1476 struct amr_user_ioctl *au; 1477 struct amr_ccb *ac; 1478 struct amr_mailbox_ioctl *mbi; 1479 unsigned long au_length; 1480 uint8_t *au_cmd; 1481 int error; 1482 void *dp = NULL, *au_buffer; 1483 1484 amr = device_lookup_private(&amr_cd, minor(dev)); 1485 1486 /* This should be compatible with the FreeBSD interface */ 1487 1488 switch (cmd) { 1489 case AMR_IO_VERSION: 1490 *(int *)data = AMR_IO_VERSION_NUMBER; 1491 return 0; 1492 case AMR_IO_COMMAND: 1493 error = kauth_authorize_device_passthru(l->l_cred, dev, 1494 KAUTH_REQ_DEVICE_RAWIO_PASSTHRU_ALL, data); 1495 if (error) 1496 return (error); 1497 1498 au = (struct amr_user_ioctl *)data; 1499 au_cmd = au->au_cmd; 1500 au_buffer = au->au_buffer; 1501 au_length = au->au_length; 1502 break; 1503 default: 1504 return ENOTTY; 1505 } 1506 1507 if (au_cmd[0] == AMR_CMD_PASS) { 1508 /* not yet */ 1509 return EOPNOTSUPP; 1510 } 1511 1512 if (au_length <= 0 || au_length > MAXPHYS || au_cmd[0] == 0x06) 1513 return (EINVAL); 1514 1515 /* 1516 * allocate kernel memory for data, doing I/O directly to user 1517 * buffer isn't that easy. Correct allocation size for a bug 1518 * in at least some versions of the device firmware, by using 1519 * the amrioctl_buflen() function, defined above. 1520 */ 1521 dp = malloc(amrioctl_buflen(au_length), M_DEVBUF, M_WAITOK|M_ZERO); 1522 if (dp == NULL) 1523 return ENOMEM; 1524 if ((error = copyin(au_buffer, dp, au_length)) != 0) 1525 goto out; 1526 1527 /* direct command to controller */ 1528 while (amr_ccb_alloc(amr, &ac) != 0) { 1529 mutex_enter(&thread_mutex); 1530 error = cv_timedwait_sig(&thread_cv, &thread_mutex, hz); 1531 mutex_exit(&thread_mutex); 1532 if (error == EINTR) 1533 goto out; 1534 } 1535 1536 mbi = (struct amr_mailbox_ioctl *)&ac->ac_cmd; 1537 mbi->mb_command = au_cmd[0]; 1538 mbi->mb_channel = au_cmd[1]; 1539 mbi->mb_param = au_cmd[2]; 1540 mbi->mb_pad[0] = au_cmd[3]; 1541 mbi->mb_drive = au_cmd[4]; 1542 error = amr_ccb_map(amr, ac, dp, (int)au_length, 1543 AC_XFER_IN | AC_XFER_OUT); 1544 if (error == 0) { 1545 error = amr_ccb_wait(amr, ac); 1546 amr_ccb_unmap(amr, ac); 1547 if (error == 0) 1548 error = copyout(dp, au_buffer, au_length); 1549 1550 } 1551 amr_ccb_free(amr, ac); 1552 out: 1553 free(dp, M_DEVBUF); 1554 return (error); 1555 } 1556 1557 MODULE(MODULE_CLASS_DRIVER, amr, "pci"); 1558 1559 #ifdef _MODULE 1560 #include "ioconf.c" 1561 #endif 1562 1563 static int 1564 amr_modcmd(modcmd_t cmd, void *opaque) 1565 { 1566 int error = 0; 1567 1568 #ifdef _MODULE 1569 switch (cmd) { 1570 case MODULE_CMD_INIT: 1571 error = config_init_component(cfdriver_ioconf_amr, 1572 cfattach_ioconf_amr, cfdata_ioconf_amr); 1573 break; 1574 case MODULE_CMD_FINI: 1575 error = config_fini_component(cfdriver_ioconf_amr, 1576 cfattach_ioconf_amr, cfdata_ioconf_amr); 1577 break; 1578 default: 1579 error = ENOTTY; 1580 break; 1581 } 1582 #endif 1583 1584 return error; 1585 } 1586
Indexes created Thu Oct 02 14:10:14 GMT 2025