arcmsrvar.h revision 1.14.12.1
1 /* $NetBSD: arcmsrvar.h,v 1.14.12.1 2012/12/02 05:46:03 tls Exp $ */ 2 /* Derived from $OpenBSD: arc.c,v 1.68 2007/10/27 03:28:27 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2007 Juan Romero Pardines <xtraeme (at) netbsd.org> 6 * Copyright (c) 2006 David Gwynne <dlg (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #ifndef _PCI_ARCMSRVAR_H_ 22 #define _PCI_ARCMSRVAR_H_ 23 24 #define ARC_PCI_BAR PCI_MAPREG_START 25 26 #define ARC_REG_INB_MSG0 0x0010 27 #define ARC_REG_INB_MSG0_NOP (0x00000000) 28 #define ARC_REG_INB_MSG0_GET_CONFIG (0x00000001) 29 #define ARC_REG_INB_MSG0_SET_CONFIG (0x00000002) 30 #define ARC_REG_INB_MSG0_ABORT_CMD (0x00000003) 31 #define ARC_REG_INB_MSG0_STOP_BGRB (0x00000004) 32 #define ARC_REG_INB_MSG0_FLUSH_CACHE (0x00000005) 33 #define ARC_REG_INB_MSG0_START_BGRB (0x00000006) 34 #define ARC_REG_INB_MSG0_CHK331PENDING (0x00000007) 35 #define ARC_REG_INB_MSG0_SYNC_TIMER (0x00000008) 36 #define ARC_REG_INB_MSG1 0x0014 37 #define ARC_REG_OUTB_ADDR0 0x0018 38 #define ARC_REG_OUTB_ADDR1 0x001c 39 #define ARC_REG_OUTB_ADDR1_FIRMWARE_OK (1<<31) 40 #define ARC_REG_INB_DOORBELL 0x0020 41 #define ARC_REG_INB_DOORBELL_WRITE_OK (1<<0) 42 #define ARC_REG_INB_DOORBELL_READ_OK (1<<1) 43 #define ARC_REG_OUTB_DOORBELL 0x002c 44 #define ARC_REG_OUTB_DOORBELL_WRITE_OK (1<<0) 45 #define ARC_REG_OUTB_DOORBELL_READ_OK (1<<1) 46 #define ARC_REG_INTRSTAT 0x0030 47 #define ARC_REG_INTRSTAT_MSG0 (1<<0) 48 #define ARC_REG_INTRSTAT_MSG1 (1<<1) 49 #define ARC_REG_INTRSTAT_DOORBELL (1<<2) 50 #define ARC_REG_INTRSTAT_POSTQUEUE (1<<3) 51 #define ARC_REG_INTRSTAT_PCI (1<<4) 52 #define ARC_REG_INTRMASK 0x0034 53 #define ARC_REG_INTRMASK_MSG0 (1<<0) 54 #define ARC_REG_INTRMASK_MSG1 (1<<1) 55 #define ARC_REG_INTRMASK_DOORBELL (1<<2) 56 #define ARC_REG_INTRMASK_POSTQUEUE (1<<3) 57 #define ARC_REG_INTRMASK_PCI (1<<4) 58 #define ARC_REG_POST_QUEUE 0x0040 59 #define ARC_REG_POST_QUEUE_ADDR_SHIFT 5 60 #define ARC_REG_POST_QUEUE_IAMBIOS (1<<30) 61 #define ARC_REG_POST_QUEUE_BIGFRAME (1<<31) 62 #define ARC_REG_REPLY_QUEUE 0x0044 63 #define ARC_REG_REPLY_QUEUE_ADDR_SHIFT 5 64 #define ARC_REG_REPLY_QUEUE_ERR (1<<28) 65 #define ARC_REG_REPLY_QUEUE_IAMBIOS (1<<30) 66 #define ARC_REG_MSGBUF 0x0a00 67 #define ARC_REG_MSGBUF_LEN 1024 68 #define ARC_REG_IOC_WBUF_LEN 0x0e00 69 #define ARC_REG_IOC_WBUF 0x0e04 70 #define ARC_REG_IOC_RBUF_LEN 0x0f00 71 #define ARC_REG_IOC_RBUF 0x0f04 72 #define ARC_REG_IOC_RWBUF_MAXLEN 124 /* for both RBUF and WBUF */ 73 74 struct arc_msg_firmware_info { 75 uint32_t signature; 76 #define ARC_FWINFO_SIGNATURE_GET_CONFIG (0x87974060) 77 uint32_t request_len; 78 uint32_t queue_len; 79 uint32_t sdram_size; 80 uint32_t sata_ports; 81 uint8_t vendor[40]; 82 uint8_t model[8]; 83 uint8_t fw_version[16]; 84 uint8_t device_map[16]; 85 } __packed; 86 87 struct arc_msg_scsicmd { 88 uint8_t bus; 89 uint8_t target; 90 uint8_t lun; 91 uint8_t function; 92 93 uint8_t cdb_len; 94 uint8_t sgl_len; 95 uint8_t flags; 96 #define ARC_MSG_SCSICMD_FLAG_SGL_BSIZE_512 (1<<0) 97 #define ARC_MSG_SCSICMD_FLAG_FROM_BIOS (1<<1) 98 #define ARC_MSG_SCSICMD_FLAG_WRITE (1<<2) 99 #define ARC_MSG_SCSICMD_FLAG_SIMPLEQ (0x00) 100 #define ARC_MSG_SCSICMD_FLAG_HEADQ (0x08) 101 #define ARC_MSG_SCSICMD_FLAG_ORDERQ (0x10) 102 uint8_t reserved; 103 104 uint32_t context; 105 uint32_t data_len; 106 107 #define ARC_MSG_CDBLEN 16 108 uint8_t cdb[ARC_MSG_CDBLEN]; 109 110 uint8_t status; 111 #define ARC_MSG_STATUS_SELTIMEOUT 0xf0 112 #define ARC_MSG_STATUS_ABORTED 0xf1 113 #define ARC_MSG_STATUS_INIT_FAIL 0xf2 114 #define ARC_MSG_SENSELEN 15 115 uint8_t sense_data[ARC_MSG_SENSELEN]; 116 117 /* followed by an sgl */ 118 } __packed; 119 120 struct arc_sge { 121 uint32_t sg_hdr; 122 #define ARC_SGE_64BIT (1<<24) 123 uint32_t sg_lo_addr; 124 uint32_t sg_hi_addr; 125 } __packed; 126 127 #define ARC_MAX_TARGET 16 128 #define ARC_MAX_LUN 8 129 #define ARC_MAX_IOCMDLEN 512 130 #define ARC_MAX_XFER_BLOCKS 4096 131 #define ARC_BLOCKSIZE 512 132 #define ARC_MAX_XFER (MIN(MACHINE_MAXPHYS, \ 133 ARC_MAX_XFER_BLOCKS * ARC_BLOCKSIZE)) 134 135 /* 136 * the firmware deals with up to 256 or 512 byte command frames. 137 */ 138 139 /* 140 * sizeof(struct arc_msg_scsicmd) + (sizeof(struct arc_sge) * 38) == 508. 141 */ 142 #define ARC_SGL_MAXLEN 38 143 /* 144 * sizeof(struct arc_msg_scsicmd) + (sizeof(struct arc_sge) * 17) == 252. 145 */ 146 #define ARC_SGL_256LEN 17 147 148 struct arc_io_cmd { 149 struct arc_msg_scsicmd cmd; 150 struct arc_sge sgl[ARC_SGL_MAXLEN]; 151 } __packed; 152 153 /* 154 * definitions of the firmware commands sent via the doorbells. 155 */ 156 struct arc_fw_hdr { 157 uint8_t byte1; 158 uint8_t byte2; 159 uint8_t byte3; 160 } __packed; 161 162 struct arc_fw_bufhdr { 163 struct arc_fw_hdr hdr; 164 uint16_t len; 165 } __packed; 166 167 /* Firmware command codes */ 168 #define ARC_FW_CHECK_PASS 0x14 /* opcode + 1 byte length + password */ 169 #define ARC_FW_GETEVENTS 0x1a /* opcode + 1 byte for page 0/1/2/3 */ 170 #define ARC_FW_GETHWMON 0x1b /* opcode + arc_fw_hwmon */ 171 #define ARC_FW_RAIDINFO 0x20 /* opcode + raid# */ 172 #define ARC_FW_VOLINFO 0x21 /* opcode + vol# */ 173 #define ARC_FW_DISKINFO 0x22 /* opcode + physdisk# */ 174 #define ARC_FW_SYSINFO 0x23 /* opcode. reply is fw_sysinfo */ 175 #define ARC_FW_CLEAREVENTS 0x24 /* opcode only */ 176 #define ARC_FW_MUTE_ALARM 0x30 /* opcode only */ 177 #define ARC_FW_SET_ALARM 0x31 /* opcode + 1 byte for setting */ 178 #define ARC_FW_SET_ALARM_DISABLE 0x00 179 #define ARC_FW_SET_ALARM_ENABLE 0x01 180 #define ARC_FW_SET_PASS 0x32 /* opcode + 1 byte length + password */ 181 #define ARC_FW_REBUILD_PRIO 0x34 /* Rebuild priority for disks */ 182 #define ARC_FW_REBUILD_PRIO_ULTRALOW (1<<0) 183 #define ARC_FW_REBUILD_PRIO_LOW (1<<1) 184 #define ARC_FW_REBUILD_PRIO_NORMAL (1<<2) 185 #define ARC_FW_REBUILD_PRIO_HIGH (1<<3) 186 #define ARC_FW_SET_MAXATA_MODE 0x35 /* opcode + 1 byte mode */ 187 #define ARC_FW_SET_MAXATA_MODE_133 (1<<0) 188 #define ARC_FW_SET_MAXATA_MODE_100 (1<<1) 189 #define ARC_FW_SET_MAXATA_MODE_66 (1<<2) 190 #define ARC_FW_SET_MAXATA_MODE_33 (1<<3) 191 #define ARC_FW_NOP 0x38 /* opcode only */ 192 /* 193 * Structure for ARC_FW_CREATE_PASSTHRU: 194 * 195 * byte 2 command code 0x40 196 * byte 3 device # 197 * byte 4 scsi channel (0/1) 198 * byte 5 scsi id (0/15) 199 * byte 6 scsi lun (0/7) 200 * byte 7 tagged queue (1 enabled) 201 * byte 8 cache mode (1 enabled) 202 * byte 9 max speed ((0/1/2/3/4 -> 33/66/100/133/150) 203 */ 204 #define ARC_FW_CREATE_PASSTHRU 0x40 205 #define ARC_FW_DELETE_PASSTHRU 0x42 /* opcode + device# */ 206 207 /* 208 * Structure for ARC_FW_CREATE_RAIDSET: 209 * 210 * byte 2 command code 0x50 211 * byte 3-6 device mask 212 * byte 7-22 raidset name (byte 7 == 0 use default) 213 */ 214 #define ARC_FW_CREATE_RAIDSET 0x50 215 #define ARC_FW_DELETE_RAIDSET 0x51 /* opcode + raidset# */ 216 #define ARC_FW_CREATE_HOTSPARE 0x54 /* opcode + 4 bytes device mask */ 217 #define ARC_FW_DELETE_HOTSPARE 0x55 /* opcode + 4 bytes device mask */ 218 219 /* 220 * Structure for ARC_FW_CREATE_VOLUME/ARC_FW_MODIFY_VOLUME: 221 * 222 * byte 2 command code 0x60 223 * byte 3 raidset# 224 * byte 4-19 volume set name (byte 4 == 0 use default) 225 * byte 20-27 volume capacity in blocks 226 * byte 28 raid level 227 * byte 29 stripe size 228 * byte 30 channel 229 * byte 31 ID 230 * byte 32 LUN 231 * byte 33 1 enable tag queuing 232 * byte 33 1 enable cache 233 * byte 35 speed 0/1/2/3/4 -> 33/66/100/133/150 234 * byte 36 1 for quick init (only for CREATE_VOLUME) 235 */ 236 #define ARC_FW_CREATE_VOLUME 0x60 237 #define ARC_FW_MODIFY_VOLUME 0x61 238 #define ARC_FW_DELETE_VOLUME 0x62 /* opcode + vol# */ 239 #define ARC_FW_START_CHECKVOL 0x63 /* opcode + vol# */ 240 #define ARC_FW_STOP_CHECKVOL 0x64 /* opcode only */ 241 242 /* Status codes for the firmware command codes */ 243 #define ARC_FW_CMD_OK 0x41 244 #define ARC_FW_CMD_RAIDINVAL 0x42 245 #define ARC_FW_CMD_VOLINVAL 0x43 246 #define ARC_FW_CMD_NORAID 0x44 247 #define ARC_FW_CMD_NOVOLUME 0x45 248 #define ARC_FW_CMD_NOPHYSDRV 0x46 249 #define ARC_FW_CMD_PARAM_ERR 0x47 250 #define ARC_FW_CMD_UNSUPPORTED 0x48 251 #define ARC_FW_CMD_DISKCFG_CHGD 0x49 252 #define ARC_FW_CMD_PASS_INVAL 0x4a 253 #define ARC_FW_CMD_NODISKSPACE 0x4b 254 #define ARC_FW_CMD_CHECKSUM_ERR 0x4c 255 #define ARC_FW_CMD_PASS_REQD 0x4d 256 257 struct arc_fw_hwmon { 258 uint8_t nfans; 259 uint8_t nvoltages; 260 uint8_t ntemps; 261 uint8_t npower; 262 uint16_t fan0; /* RPM */ 263 uint16_t fan1; /* RPM */ 264 uint16_t voltage_orig0; /* original value * 1000 */ 265 uint16_t voltage_val0; /* value */ 266 uint16_t voltage_orig1; /* original value * 1000 */ 267 uint16_t voltage_val1; /* value */ 268 uint16_t voltage_orig2; 269 uint16_t voltage_val2; 270 uint8_t temp0; 271 uint8_t temp1; 272 uint8_t pwr_indicator; /* (bit0 : power#0, bit1 : power#1) */ 273 uint8_t ups_indicator; 274 } __packed; 275 276 struct arc_fw_comminfo { 277 uint8_t baud_rate; 278 uint8_t data_bits; 279 uint8_t stop_bits; 280 uint8_t parity; 281 uint8_t flow_control; 282 } __packed; 283 284 struct arc_fw_scsiattr { 285 uint8_t channel; /* channel for SCSI target (0/1) */ 286 uint8_t target; 287 uint8_t lun; 288 uint8_t tagged; 289 uint8_t cache; 290 uint8_t speed; 291 } __packed; 292 293 struct arc_fw_raidinfo { 294 uint8_t set_name[16]; 295 uint32_t capacity; 296 uint32_t capacity2; 297 uint32_t fail_mask; 298 uint8_t device_array[32]; 299 uint8_t member_devices; 300 uint8_t new_member_devices; 301 uint8_t raid_state; 302 uint8_t volumes; 303 uint8_t volume_list[16]; 304 uint8_t reserved1[3]; 305 uint8_t free_segments; 306 uint32_t raw_stripes[8]; 307 uint8_t reserved2[12]; 308 } __packed; 309 310 struct arc_fw_volinfo { 311 uint8_t set_name[16]; 312 uint32_t capacity; 313 uint32_t capacity2; 314 uint32_t fail_mask; 315 uint32_t stripe_size; /* in blocks */ 316 uint32_t new_fail_mask; 317 uint32_t new_stripe_size; 318 uint32_t volume_status; 319 #define ARC_FW_VOL_STATUS_NORMAL 0x00 320 #define ARC_FW_VOL_STATUS_INITTING (1<<0) 321 #define ARC_FW_VOL_STATUS_FAILED (1<<1) 322 #define ARC_FW_VOL_STATUS_MIGRATING (1<<2) 323 #define ARC_FW_VOL_STATUS_REBUILDING (1<<3) 324 #define ARC_FW_VOL_STATUS_NEED_INIT (1<<4) 325 #define ARC_FW_VOL_STATUS_NEED_MIGRATE (1<<5) 326 #define ARC_FW_VOL_STATUS_INIT_FLAG (1<<6) 327 #define ARC_FW_VOL_STATUS_NEED_REGEN (1<<7) 328 #define ARC_FW_VOL_STATUS_CHECKING (1<<8) 329 #define ARC_FW_VOL_STATUS_NEED_CHECK (1<<9) 330 uint32_t progress; 331 struct arc_fw_scsiattr scsi_attr; 332 uint8_t member_disks; 333 uint8_t raid_level; 334 #define ARC_FW_VOL_RAIDLEVEL_0 0x00 335 #define ARC_FW_VOL_RAIDLEVEL_1 0x01 336 #define ARC_FW_VOL_RAIDLEVEL_3 0x02 337 #define ARC_FW_VOL_RAIDLEVEL_5 0x03 338 #define ARC_FW_VOL_RAIDLEVEL_6 0x04 339 #define ARC_FW_VOL_RAIDLEVEL_PASSTHRU 0x05 340 uint8_t new_member_disks; 341 uint8_t new_raid_level; 342 uint8_t raid_set_number; 343 uint8_t reserved[5]; 344 } __packed; 345 346 struct arc_fw_diskinfo { 347 uint8_t model[40]; 348 uint8_t serial[20]; 349 uint8_t firmware_rev[8]; 350 uint32_t capacity; 351 uint32_t capacity2; 352 uint8_t device_state; 353 #define ARC_FW_DISK_NORMAL 0x88 /* disk attached/initialized */ 354 #define ARC_FW_DISK_PASSTHRU 0x8a /* pass through disk in normal state */ 355 #define ARC_FW_DISK_HOTSPARE 0xa8 /* hotspare disk in normal state */ 356 #define ARC_FW_DISK_UNUSED 0xc8 /* free/unused disk in normal state */ 357 #define ARC_FW_DISK_FAILED 0x10 /* disk in failed state */ 358 uint8_t pio_mode; 359 uint8_t current_udma_mode; 360 uint8_t udma_mode; 361 uint8_t drive_select; 362 uint8_t raid_number; /* 0xff unowned */ 363 struct arc_fw_scsiattr scsi_attr; 364 uint8_t reserved[40]; 365 } __packed; 366 367 struct arc_fw_sysinfo { 368 uint8_t vendor_name[40]; 369 uint8_t serial_number[16]; 370 uint8_t firmware_version[16]; 371 uint8_t boot_version[16]; 372 uint8_t mb_version[16]; 373 uint8_t model_name[8]; 374 375 uint8_t local_ip[4]; 376 uint8_t current_ip[4]; 377 378 uint32_t time_tick; 379 uint32_t cpu_speed; 380 uint32_t icache; 381 uint32_t dcache; 382 uint32_t scache; 383 uint32_t memory_size; 384 uint32_t memory_speed; 385 uint32_t events; 386 387 uint8_t gsiMacAddress[6]; 388 uint8_t gsiDhcp; 389 390 uint8_t alarm; 391 uint8_t channel_usage; 392 uint8_t max_ata_mode; 393 uint8_t sdram_ecc; 394 uint8_t rebuild_priority; 395 struct arc_fw_comminfo comm_a; 396 struct arc_fw_comminfo comm_b; 397 uint8_t ide_channels; 398 uint8_t scsi_host_channels; 399 uint8_t ide_host_channels; 400 uint8_t max_volume_set; 401 uint8_t max_raid_set; 402 uint8_t ether_port; 403 uint8_t raid6_engine; 404 uint8_t reserved[75]; 405 } __packed; 406 407 /* 408 * autconf(9) glue. 409 */ 410 struct arc_ccb; 411 TAILQ_HEAD(arc_ccb_list, arc_ccb); 412 413 typedef struct arc_edata { 414 envsys_data_t arc_sensor; 415 int arc_diskid; 416 int arc_volid; 417 } arc_edata_t; 418 419 struct arc_softc { 420 struct scsipi_channel sc_chan; 421 struct scsipi_adapter sc_adapter; 422 423 pci_chipset_tag_t sc_pc; 424 pcitag_t sc_tag; 425 426 bus_space_tag_t sc_iot; 427 bus_space_handle_t sc_ioh; 428 bus_size_t sc_ios; 429 bus_dma_tag_t sc_dmat; 430 431 void *sc_ih; 432 433 int sc_req_count; 434 435 struct arc_dmamem *sc_requests; 436 struct arc_ccb *sc_ccbs; 437 struct arc_ccb_list sc_ccb_free; 438 439 struct lwp *sc_lwp; 440 volatile int sc_talking; 441 kmutex_t sc_mutex; 442 kcondvar_t sc_condvar; 443 krwlock_t sc_rwlock; 444 445 struct sysmon_envsys *sc_sme; 446 arc_edata_t *sc_arc_sensors; 447 int sc_nsensors; 448 449 size_t sc_maxraidset; /* max raid sets */ 450 size_t sc_maxvolset; /* max volume sets */ 451 size_t sc_cchans; /* connected channels */ 452 453 device_t sc_dev; /* self */ 454 device_t sc_scsibus_dv; 455 }; 456 457 /* 458 * interface for scsi midlayer to talk to. 459 */ 460 void arc_scsi_cmd(struct scsipi_channel *, scsipi_adapter_req_t, void *); 461 462 /* 463 * code to deal with getting bits in and out of the bus space. 464 */ 465 uint32_t arc_read(struct arc_softc *, bus_size_t); 466 void arc_read_region(struct arc_softc *, bus_size_t, void *, 467 size_t); 468 void arc_write(struct arc_softc *, bus_size_t, uint32_t); 469 void arc_write_region(struct arc_softc *, bus_size_t, void *, 470 size_t); 471 int arc_wait_eq(struct arc_softc *, bus_size_t, uint32_t, 472 uint32_t); 473 int arc_wait_ne(struct arc_softc *, bus_size_t, uint32_t, 474 uint32_t); 475 int arc_msg0(struct arc_softc *, uint32_t); 476 477 #define arc_push(_s, _r) arc_write((_s), ARC_REG_POST_QUEUE, (_r)) 478 #define arc_pop(_s) arc_read((_s), ARC_REG_REPLY_QUEUE) 479 480 /* 481 * wrap up the bus_dma api. 482 */ 483 struct arc_dmamem { 484 bus_dmamap_t adm_map; 485 bus_dma_segment_t adm_seg; 486 size_t adm_size; 487 void *adm_kva; 488 }; 489 #define ARC_DMA_MAP(_adm) ((_adm)->adm_map) 490 #define ARC_DMA_DVA(_adm) ((_adm)->adm_map->dm_segs[0].ds_addr) 491 #define ARC_DMA_KVA(_adm) ((void *)(_adm)->adm_kva) 492 493 struct arc_dmamem *arc_dmamem_alloc(struct arc_softc *, size_t); 494 void arc_dmamem_free(struct arc_softc *, 495 struct arc_dmamem *); 496 497 /* 498 * stuff to manage a scsi command. 499 */ 500 struct arc_ccb { 501 struct arc_softc *ccb_sc; 502 int ccb_id; 503 504 struct scsipi_xfer *ccb_xs; 505 506 bus_dmamap_t ccb_dmamap; 507 bus_addr_t ccb_offset; 508 struct arc_io_cmd *ccb_cmd; 509 uint32_t ccb_cmd_post; 510 511 TAILQ_ENTRY(arc_ccb) ccb_link; 512 }; 513 514 int arc_alloc_ccbs(device_t); 515 struct arc_ccb *arc_get_ccb(struct arc_softc *); 516 void arc_put_ccb(struct arc_softc *, struct arc_ccb *); 517 int arc_load_xs(struct arc_ccb *); 518 int arc_complete(struct arc_softc *, struct arc_ccb *, int); 519 void arc_scsi_cmd_done(struct arc_softc *, struct arc_ccb *, 520 uint32_t); 521 522 /* 523 * real stuff for dealing with the hardware. 524 */ 525 int arc_map_pci_resources(device_t, struct pci_attach_args *); 526 void arc_unmap_pci_resources(struct arc_softc *); 527 int arc_query_firmware(device_t); 528 529 /* 530 * stuff to do messaging via the doorbells. 531 */ 532 void arc_lock(struct arc_softc *); 533 void arc_unlock(struct arc_softc *); 534 void arc_wait(struct arc_softc *); 535 uint8_t arc_msg_cksum(void *, uint16_t); 536 int arc_msgbuf(struct arc_softc *, void *, size_t, void *, size_t); 537 538 #endif /* ! _PCI_ARCMSRVAR_H_ */ 539
Indexes created Wed Oct 22 13:09:56 GMT 2025