Home | History | Annotate | Line # | Download | only in pci
arcmsrvar.h revision 1.5.4.2
      1 /*	$NetBSD: arcmsrvar.h,v 1.5.4.2 2007/12/08 18:19:41 mjf Exp $ */
      2 /*	Derived from $OpenBSD: arc.c,v 1.68 2007/10/27 03:28:27 dlg Exp $ */
      3 
      4 /*
      5  * Copyright (c) 2006 David Gwynne <dlg (at) openbsd.org>
      6  *
      7  * Permission to use, copy, modify, and distribute this software for any
      8  * purpose with or without fee is hereby granted, provided that the above
      9  * copyright notice and this permission notice appear in all copies.
     10  *
     11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
     12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
     13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
     14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
     15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
     16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
     17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
     18  */
     19 
     20 #ifndef _PCI_ARCMSRVAR_H_
     21 #define _PCI_ARCMSRVAR_H_
     22 
     23 #define ARC_PCI_BAR			PCI_MAPREG_START
     24 
     25 #define ARC_REG_INB_MSG0		0x0010
     26 #define  ARC_REG_INB_MSG0_NOP			(0x00000000)
     27 #define  ARC_REG_INB_MSG0_GET_CONFIG		(0x00000001)
     28 #define  ARC_REG_INB_MSG0_SET_CONFIG		(0x00000002)
     29 #define  ARC_REG_INB_MSG0_ABORT_CMD		(0x00000003)
     30 #define  ARC_REG_INB_MSG0_STOP_BGRB		(0x00000004)
     31 #define  ARC_REG_INB_MSG0_FLUSH_CACHE		(0x00000005)
     32 #define  ARC_REG_INB_MSG0_START_BGRB		(0x00000006)
     33 #define  ARC_REG_INB_MSG0_CHK331PENDING		(0x00000007)
     34 #define  ARC_REG_INB_MSG0_SYNC_TIMER		(0x00000008)
     35 #define ARC_REG_INB_MSG1		0x0014
     36 #define ARC_REG_OUTB_ADDR0		0x0018
     37 #define ARC_REG_OUTB_ADDR1		0x001c
     38 #define  ARC_REG_OUTB_ADDR1_FIRMWARE_OK		(1<<31)
     39 #define ARC_REG_INB_DOORBELL		0x0020
     40 #define  ARC_REG_INB_DOORBELL_WRITE_OK		(1<<0)
     41 #define  ARC_REG_INB_DOORBELL_READ_OK		(1<<1)
     42 #define ARC_REG_OUTB_DOORBELL		0x002c
     43 #define  ARC_REG_OUTB_DOORBELL_WRITE_OK		(1<<0)
     44 #define  ARC_REG_OUTB_DOORBELL_READ_OK		(1<<1)
     45 #define ARC_REG_INTRSTAT		0x0030
     46 #define  ARC_REG_INTRSTAT_MSG0			(1<<0)
     47 #define  ARC_REG_INTRSTAT_MSG1			(1<<1)
     48 #define  ARC_REG_INTRSTAT_DOORBELL		(1<<2)
     49 #define  ARC_REG_INTRSTAT_POSTQUEUE		(1<<3)
     50 #define  ARC_REG_INTRSTAT_PCI			(1<<4)
     51 #define ARC_REG_INTRMASK		0x0034
     52 #define  ARC_REG_INTRMASK_MSG0			(1<<0)
     53 #define  ARC_REG_INTRMASK_MSG1			(1<<1)
     54 #define  ARC_REG_INTRMASK_DOORBELL		(1<<2)
     55 #define  ARC_REG_INTRMASK_POSTQUEUE		(1<<3)
     56 #define  ARC_REG_INTRMASK_PCI			(1<<4)
     57 #define ARC_REG_POST_QUEUE		0x0040
     58 #define  ARC_REG_POST_QUEUE_ADDR_SHIFT		5
     59 #define  ARC_REG_POST_QUEUE_IAMBIOS		(1<<30)
     60 #define  ARC_REG_POST_QUEUE_BIGFRAME		(1<<31)
     61 #define ARC_REG_REPLY_QUEUE		0x0044
     62 #define  ARC_REG_REPLY_QUEUE_ADDR_SHIFT		5
     63 #define  ARC_REG_REPLY_QUEUE_ERR		(1<<28)
     64 #define  ARC_REG_REPLY_QUEUE_IAMBIOS		(1<<30)
     65 #define ARC_REG_MSGBUF			0x0a00
     66 #define  ARC_REG_MSGBUF_LEN		1024
     67 #define ARC_REG_IOC_WBUF_LEN		0x0e00
     68 #define ARC_REG_IOC_WBUF		0x0e04
     69 #define ARC_REG_IOC_RBUF_LEN		0x0f00
     70 #define ARC_REG_IOC_RBUF		0x0f04
     71 #define  ARC_REG_IOC_RWBUF_MAXLEN	124 /* for both RBUF and WBUF */
     72 
     73 struct arc_msg_firmware_info {
     74 	uint32_t	signature;
     75 #define ARC_FWINFO_SIGNATURE_GET_CONFIG		(0x87974060)
     76 	uint32_t	request_len;
     77 	uint32_t	queue_len;
     78 	uint32_t	sdram_size;
     79 	uint32_t	sata_ports;
     80 	uint8_t		vendor[40];
     81 	uint8_t		model[8];
     82 	uint8_t		fw_version[16];
     83 	uint8_t		device_map[16];
     84 } __packed;
     85 
     86 struct arc_msg_scsicmd {
     87 	uint8_t		bus;
     88 	uint8_t		target;
     89 	uint8_t		lun;
     90 	uint8_t		function;
     91 
     92 	uint8_t		cdb_len;
     93 	uint8_t		sgl_len;
     94 	uint8_t		flags;
     95 #define ARC_MSG_SCSICMD_FLAG_SGL_BSIZE_512	(1<<0)
     96 #define ARC_MSG_SCSICMD_FLAG_FROM_BIOS		(1<<1)
     97 #define ARC_MSG_SCSICMD_FLAG_WRITE		(1<<2)
     98 #define ARC_MSG_SCSICMD_FLAG_SIMPLEQ		(0x00)
     99 #define ARC_MSG_SCSICMD_FLAG_HEADQ		(0x08)
    100 #define ARC_MSG_SCSICMD_FLAG_ORDERQ		(0x10)
    101 	uint8_t		reserved;
    102 
    103 	uint32_t	context;
    104 	uint32_t	data_len;
    105 
    106 #define ARC_MSG_CDBLEN				16
    107 	uint8_t		cdb[ARC_MSG_CDBLEN];
    108 
    109 	uint8_t		status;
    110 #define ARC_MSG_STATUS_SELTIMEOUT		0xf0
    111 #define ARC_MSG_STATUS_ABORTED			0xf1
    112 #define ARC_MSG_STATUS_INIT_FAIL		0xf2
    113 #define ARC_MSG_SENSELEN			15
    114 	uint8_t		sense_data[ARC_MSG_SENSELEN];
    115 
    116 	/* followed by an sgl */
    117 } __packed;
    118 
    119 struct arc_sge {
    120 	uint32_t	sg_hdr;
    121 #define ARC_SGE_64BIT				(1<<24)
    122 	uint32_t	sg_lo_addr;
    123 	uint32_t	sg_hi_addr;
    124 } __packed;
    125 
    126 #define ARC_MAX_TARGET		16
    127 #define ARC_MAX_LUN		8
    128 #define ARC_MAX_IOCMDLEN	512
    129 #define ARC_BLOCKSIZE		512
    130 
    131 /*
    132  * the firmware deals with up to 256 or 512 byte command frames.
    133  */
    134 
    135 /*
    136  * sizeof(struct arc_msg_scsicmd) + (sizeof(struct arc_sge) * 38) == 508.
    137  */
    138 #define ARC_SGL_MAXLEN		38
    139 /*
    140  * sizeof(struct arc_msg_scsicmd) + (sizeof(struct arc_sge) * 17) == 252.
    141  */
    142 #define ARC_SGL_256LEN		17
    143 
    144 struct arc_io_cmd {
    145 	struct arc_msg_scsicmd	cmd;
    146 	struct arc_sge		sgl[ARC_SGL_MAXLEN];
    147 } __packed;
    148 
    149 /*
    150  * definitions of the firmware commands sent via the doorbells.
    151  */
    152 struct arc_fw_hdr {
    153 	uint8_t		byte1;
    154 	uint8_t		byte2;
    155 	uint8_t		byte3;
    156 } __packed;
    157 
    158 struct arc_fw_bufhdr {
    159 	struct arc_fw_hdr	hdr;
    160 	uint16_t		len;
    161 } __packed;
    162 
    163 #define ARC_FW_RAIDINFO		0x20	/* opcode + raid# */
    164 #define ARC_FW_VOLINFO		0x21	/* opcode + vol# */
    165 #define ARC_FW_DISKINFO		0x22	/* opcode + physdisk# */
    166 #define ARC_FW_SYSINFO		0x23	/* opcode. reply is fw_sysinfo */
    167 #define ARC_FW_MUTE_ALARM	0x30	/* opcode only */
    168 #define ARC_FW_SET_ALARM	0x31	/* opcode + 1 byte for setting */
    169 #define  ARC_FW_SET_ALARM_DISABLE		0x00
    170 #define  ARC_FW_SET_ALARM_ENABLE		0x01
    171 #define ARC_FW_NOP		0x38	/* opcode only */
    172 
    173 #define ARC_FW_CMD_OK		0x41
    174 #define ARC_FW_CMD_PASS_REQD	0x4d
    175 
    176 struct arc_fw_comminfo {
    177 	uint8_t		baud_rate;
    178 	uint8_t		data_bits;
    179 	uint8_t		stop_bits;
    180 	uint8_t		parity;
    181 	uint8_t		flow_control;
    182 } __packed;
    183 
    184 struct arc_fw_scsiattr {
    185 	uint8_t		channel;	/* channel for SCSI target (0/1) */
    186 	uint8_t		target;
    187 	uint8_t		lun;
    188 	uint8_t		tagged;
    189 	uint8_t		cache;
    190 	uint8_t		speed;
    191 } __packed;
    192 
    193 struct arc_fw_raidinfo {
    194 	uint8_t		set_name[16];
    195 	uint32_t	capacity;
    196 	uint32_t	capacity2;
    197 	uint32_t	fail_mask;
    198 	uint8_t		device_array[32];
    199 	uint8_t		member_devices;
    200 	uint8_t		new_member_devices;
    201 	uint8_t		raid_state;
    202 	uint8_t		volumes;
    203 	uint8_t		volume_list[16];
    204 	uint8_t		reserved1[3];
    205 	uint8_t		free_segments;
    206 	uint32_t	raw_stripes[8];
    207 	uint8_t		reserved2[12];
    208 } __packed;
    209 
    210 struct arc_fw_volinfo {
    211 	uint8_t		set_name[16];
    212 	uint32_t	capacity;
    213 	uint32_t	capacity2;
    214 	uint32_t	fail_mask;
    215 	uint32_t	stripe_size;	/* in blocks */
    216 	uint32_t	new_fail_mask;
    217 	uint32_t	new_stripe_size;
    218 	uint32_t	volume_status;
    219 #define ARC_FW_VOL_STATUS_NORMAL	0x00
    220 #define ARC_FW_VOL_STATUS_INITTING	(1<<0)
    221 #define ARC_FW_VOL_STATUS_FAILED	(1<<1)
    222 #define ARC_FW_VOL_STATUS_MIGRATING	(1<<2)
    223 #define ARC_FW_VOL_STATUS_REBUILDING	(1<<3)
    224 #define ARC_FW_VOL_STATUS_NEED_INIT	(1<<4)
    225 #define ARC_FW_VOL_STATUS_NEED_MIGRATE	(1<<5)
    226 #define ARC_FW_VOL_STATUS_INIT_FLAG	(1<<6)
    227 #define ARC_FW_VOL_STATUS_NEED_REGEN	(1<<7)
    228 #define ARC_FW_VOL_STATUS_CHECKING	(1<<8)
    229 #define ARC_FW_VOL_STATUS_NEED_CHECK	(1<<9)
    230 	uint32_t	progress;
    231 	struct arc_fw_scsiattr	scsi_attr;
    232 	uint8_t		member_disks;
    233 	uint8_t		raid_level;
    234 #define ARC_FW_VOL_RAIDLEVEL_0		0x00
    235 #define ARC_FW_VOL_RAIDLEVEL_1		0x01
    236 #define ARC_FW_VOL_RAIDLEVEL_3		0x02
    237 #define ARC_FW_VOL_RAIDLEVEL_5		0x03
    238 #define ARC_FW_VOL_RAIDLEVEL_6		0x04
    239 #define ARC_FW_VOL_RAIDLEVEL_PASSTHRU	0x05
    240 	uint8_t		new_member_disks;
    241 	uint8_t		new_raid_level;
    242 	uint8_t		raid_set_number;
    243 	uint8_t		reserved[5];
    244 } __packed;
    245 
    246 struct arc_fw_diskinfo {
    247 	uint8_t		model[40];
    248 	uint8_t		serial[20];
    249 	uint8_t		firmware_rev[8];
    250 	uint32_t	capacity;
    251 	uint32_t	capacity2;
    252 	uint8_t		device_state;
    253 	uint8_t		pio_mode;
    254 	uint8_t		current_udma_mode;
    255 	uint8_t		udma_mode;
    256 	uint8_t		drive_select;
    257 	uint8_t		raid_number;	/* 0xff unowned */
    258 	struct arc_fw_scsiattr	scsi_attr;
    259 	uint8_t		reserved[40];
    260 } __packed;
    261 
    262 struct arc_fw_sysinfo {
    263 	uint8_t		vendor_name[40];
    264 	uint8_t		serial_number[16];
    265 	uint8_t		firmware_version[16];
    266 	uint8_t		boot_version[16];
    267 	uint8_t		mb_version[16];
    268 	uint8_t		model_name[8];
    269 
    270 	uint8_t		local_ip[4];
    271 	uint8_t		current_ip[4];
    272 
    273 	uint32_t	time_tick;
    274 	uint32_t	cpu_speed;
    275 	uint32_t	icache;
    276 	uint32_t	dcache;
    277 	uint32_t	scache;
    278 	uint32_t	memory_size;
    279 	uint32_t	memory_speed;
    280 	uint32_t	events;
    281 
    282 	uint8_t		gsiMacAddress[6];
    283 	uint8_t		gsiDhcp;
    284 
    285 	uint8_t		alarm;
    286 	uint8_t		channel_usage;
    287 	uint8_t		max_ata_mode;
    288 	uint8_t		sdram_ecc;
    289 	uint8_t		rebuild_priority;
    290 	struct arc_fw_comminfo	comm_a;
    291 	struct arc_fw_comminfo	comm_b;
    292 	uint8_t		ide_channels;
    293 	uint8_t		scsi_host_channels;
    294 	uint8_t		ide_host_channels;
    295 	uint8_t		max_volume_set;
    296 	uint8_t		max_raid_set;
    297 	uint8_t		ether_port;
    298 	uint8_t		raid6_engine;
    299 	uint8_t		reserved[75];
    300 } __packed;
    301 
    302 /*
    303  * autconf(9) glue.
    304  */
    305 struct arc_ccb;
    306 TAILQ_HEAD(arc_ccb_list, arc_ccb);
    307 
    308 struct arc_softc {
    309 	struct device		sc_dev;
    310 	struct scsipi_channel	sc_chan;
    311 	struct scsipi_adapter	sc_adapter;
    312 
    313 	pci_chipset_tag_t	sc_pc;
    314 	pcitag_t		sc_tag;
    315 
    316 	bus_space_tag_t		sc_iot;
    317 	bus_space_handle_t	sc_ioh;
    318 	bus_size_t		sc_ios;
    319 	bus_dma_tag_t		sc_dmat;
    320 
    321 	void			*sc_ih;
    322 
    323 	void			*sc_shutdownhook;
    324 
    325 	int			sc_req_count;
    326 
    327 	struct arc_dmamem	*sc_requests;
    328 	struct arc_ccb		*sc_ccbs;
    329 	struct arc_ccb_list	sc_ccb_free;
    330 
    331 	struct lwp		*sc_lwp;
    332 	volatile int		sc_talking;
    333 	kmutex_t		sc_mutex;
    334 	kcondvar_t		sc_condvar;
    335 	krwlock_t		sc_rwlock;
    336 
    337 	struct sysmon_envsys	*sc_sme;
    338 	envsys_data_t		*sc_sensors;
    339 	int			sc_nsensors;
    340 };
    341 
    342 /*
    343  * interface for scsi midlayer to talk to.
    344  */
    345 void 	arc_scsi_cmd(struct scsipi_channel *, scsipi_adapter_req_t, void *);
    346 
    347 /*
    348  * code to deal with getting bits in and out of the bus space.
    349  */
    350 uint32_t 	arc_read(struct arc_softc *, bus_size_t);
    351 void 	arc_read_region(struct arc_softc *, bus_size_t, void *, size_t);
    352 void 	arc_write(struct arc_softc *, bus_size_t, uint32_t);
    353 void 	arc_write_region(struct arc_softc *, bus_size_t, void *, size_t);
    354 int 	arc_wait_eq(struct arc_softc *, bus_size_t, uint32_t, uint32_t);
    355 int 	arc_wait_ne(struct arc_softc *, bus_size_t, uint32_t, uint32_t);
    356 int	arc_msg0(struct arc_softc *, uint32_t);
    357 
    358 #define arc_push(_s, _r)	arc_write((_s), ARC_REG_POST_QUEUE, (_r))
    359 #define arc_pop(_s)		arc_read((_s), ARC_REG_REPLY_QUEUE)
    360 
    361 /*
    362  * wrap up the bus_dma api.
    363  */
    364 struct arc_dmamem {
    365 	bus_dmamap_t		adm_map;
    366 	bus_dma_segment_t	adm_seg;
    367 	size_t			adm_size;
    368 	void			*adm_kva;
    369 };
    370 #define ARC_DMA_MAP(_adm)	((_adm)->adm_map)
    371 #define ARC_DMA_DVA(_adm)	((_adm)->adm_map->dm_segs[0].ds_addr)
    372 #define ARC_DMA_KVA(_adm)	((void *)(_adm)->adm_kva)
    373 
    374 struct arc_dmamem 	*arc_dmamem_alloc(struct arc_softc *, size_t);
    375 void 	arc_dmamem_free(struct arc_softc *, struct arc_dmamem *);
    376 
    377 /*
    378  * stuff to manage a scsi command.
    379  */
    380 struct arc_ccb {
    381 	struct arc_softc	*ccb_sc;
    382 	int			ccb_id;
    383 
    384 	struct scsipi_xfer	*ccb_xs;
    385 
    386 	bus_dmamap_t		ccb_dmamap;
    387 	bus_addr_t		ccb_offset;
    388 	struct arc_io_cmd	*ccb_cmd;
    389 	uint32_t		ccb_cmd_post;
    390 
    391 	TAILQ_ENTRY(arc_ccb)	ccb_link;
    392 };
    393 
    394 int 	arc_alloc_ccbs(struct arc_softc *);
    395 struct arc_ccb	*arc_get_ccb(struct arc_softc *);
    396 void 	arc_put_ccb(struct arc_softc *, struct arc_ccb *);
    397 int 	arc_load_xs(struct arc_ccb *);
    398 int 	arc_complete(struct arc_softc *, struct arc_ccb *, int);
    399 void 	arc_scsi_cmd_done(struct arc_softc *, struct arc_ccb *, uint32_t);
    400 
    401 /*
    402  * real stuff for dealing with the hardware.
    403  */
    404 int 	arc_map_pci_resources(struct arc_softc *, struct pci_attach_args *);
    405 void 	arc_unmap_pci_resources(struct arc_softc *);
    406 int 	arc_query_firmware(struct arc_softc *);
    407 
    408 /*
    409  * stuff to do messaging via the doorbells.
    410  */
    411 void 	arc_lock(struct arc_softc *);
    412 void 	arc_unlock(struct arc_softc *);
    413 void 	arc_wait(struct arc_softc *);
    414 uint8_t 	arc_msg_cksum(void *, uint16_t);
    415 int 	arc_msgbuf(struct arc_softc *, void *, size_t, void *, size_t);
    416 
    417 #endif /* ! _PCI_ARCMSRVAR_H_ */
    418