arcmsrvar.h revision 1.5.4.3
1 /* $NetBSD: arcmsrvar.h,v 1.5.4.3 2007/12/27 00:45:14 mjf Exp $ */ 2 /* Derived from $OpenBSD: arc.c,v 1.68 2007/10/27 03:28:27 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2006 David Gwynne <dlg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _PCI_ARCMSRVAR_H_ 21 #define _PCI_ARCMSRVAR_H_ 22 23 #define ARC_PCI_BAR PCI_MAPREG_START 24 25 #define ARC_REG_INB_MSG0 0x0010 26 #define ARC_REG_INB_MSG0_NOP (0x00000000) 27 #define ARC_REG_INB_MSG0_GET_CONFIG (0x00000001) 28 #define ARC_REG_INB_MSG0_SET_CONFIG (0x00000002) 29 #define ARC_REG_INB_MSG0_ABORT_CMD (0x00000003) 30 #define ARC_REG_INB_MSG0_STOP_BGRB (0x00000004) 31 #define ARC_REG_INB_MSG0_FLUSH_CACHE (0x00000005) 32 #define ARC_REG_INB_MSG0_START_BGRB (0x00000006) 33 #define ARC_REG_INB_MSG0_CHK331PENDING (0x00000007) 34 #define ARC_REG_INB_MSG0_SYNC_TIMER (0x00000008) 35 #define ARC_REG_INB_MSG1 0x0014 36 #define ARC_REG_OUTB_ADDR0 0x0018 37 #define ARC_REG_OUTB_ADDR1 0x001c 38 #define ARC_REG_OUTB_ADDR1_FIRMWARE_OK (1<<31) 39 #define ARC_REG_INB_DOORBELL 0x0020 40 #define ARC_REG_INB_DOORBELL_WRITE_OK (1<<0) 41 #define ARC_REG_INB_DOORBELL_READ_OK (1<<1) 42 #define ARC_REG_OUTB_DOORBELL 0x002c 43 #define ARC_REG_OUTB_DOORBELL_WRITE_OK (1<<0) 44 #define ARC_REG_OUTB_DOORBELL_READ_OK (1<<1) 45 #define ARC_REG_INTRSTAT 0x0030 46 #define ARC_REG_INTRSTAT_MSG0 (1<<0) 47 #define ARC_REG_INTRSTAT_MSG1 (1<<1) 48 #define ARC_REG_INTRSTAT_DOORBELL (1<<2) 49 #define ARC_REG_INTRSTAT_POSTQUEUE (1<<3) 50 #define ARC_REG_INTRSTAT_PCI (1<<4) 51 #define ARC_REG_INTRMASK 0x0034 52 #define ARC_REG_INTRMASK_MSG0 (1<<0) 53 #define ARC_REG_INTRMASK_MSG1 (1<<1) 54 #define ARC_REG_INTRMASK_DOORBELL (1<<2) 55 #define ARC_REG_INTRMASK_POSTQUEUE (1<<3) 56 #define ARC_REG_INTRMASK_PCI (1<<4) 57 #define ARC_REG_POST_QUEUE 0x0040 58 #define ARC_REG_POST_QUEUE_ADDR_SHIFT 5 59 #define ARC_REG_POST_QUEUE_IAMBIOS (1<<30) 60 #define ARC_REG_POST_QUEUE_BIGFRAME (1<<31) 61 #define ARC_REG_REPLY_QUEUE 0x0044 62 #define ARC_REG_REPLY_QUEUE_ADDR_SHIFT 5 63 #define ARC_REG_REPLY_QUEUE_ERR (1<<28) 64 #define ARC_REG_REPLY_QUEUE_IAMBIOS (1<<30) 65 #define ARC_REG_MSGBUF 0x0a00 66 #define ARC_REG_MSGBUF_LEN 1024 67 #define ARC_REG_IOC_WBUF_LEN 0x0e00 68 #define ARC_REG_IOC_WBUF 0x0e04 69 #define ARC_REG_IOC_RBUF_LEN 0x0f00 70 #define ARC_REG_IOC_RBUF 0x0f04 71 #define ARC_REG_IOC_RWBUF_MAXLEN 124 /* for both RBUF and WBUF */ 72 73 struct arc_msg_firmware_info { 74 uint32_t signature; 75 #define ARC_FWINFO_SIGNATURE_GET_CONFIG (0x87974060) 76 uint32_t request_len; 77 uint32_t queue_len; 78 uint32_t sdram_size; 79 uint32_t sata_ports; 80 uint8_t vendor[40]; 81 uint8_t model[8]; 82 uint8_t fw_version[16]; 83 uint8_t device_map[16]; 84 } __packed; 85 86 struct arc_msg_scsicmd { 87 uint8_t bus; 88 uint8_t target; 89 uint8_t lun; 90 uint8_t function; 91 92 uint8_t cdb_len; 93 uint8_t sgl_len; 94 uint8_t flags; 95 #define ARC_MSG_SCSICMD_FLAG_SGL_BSIZE_512 (1<<0) 96 #define ARC_MSG_SCSICMD_FLAG_FROM_BIOS (1<<1) 97 #define ARC_MSG_SCSICMD_FLAG_WRITE (1<<2) 98 #define ARC_MSG_SCSICMD_FLAG_SIMPLEQ (0x00) 99 #define ARC_MSG_SCSICMD_FLAG_HEADQ (0x08) 100 #define ARC_MSG_SCSICMD_FLAG_ORDERQ (0x10) 101 uint8_t reserved; 102 103 uint32_t context; 104 uint32_t data_len; 105 106 #define ARC_MSG_CDBLEN 16 107 uint8_t cdb[ARC_MSG_CDBLEN]; 108 109 uint8_t status; 110 #define ARC_MSG_STATUS_SELTIMEOUT 0xf0 111 #define ARC_MSG_STATUS_ABORTED 0xf1 112 #define ARC_MSG_STATUS_INIT_FAIL 0xf2 113 #define ARC_MSG_SENSELEN 15 114 uint8_t sense_data[ARC_MSG_SENSELEN]; 115 116 /* followed by an sgl */ 117 } __packed; 118 119 struct arc_sge { 120 uint32_t sg_hdr; 121 #define ARC_SGE_64BIT (1<<24) 122 uint32_t sg_lo_addr; 123 uint32_t sg_hi_addr; 124 } __packed; 125 126 #define ARC_MAX_TARGET 16 127 #define ARC_MAX_LUN 8 128 #define ARC_MAX_IOCMDLEN 512 129 #define ARC_BLOCKSIZE 512 130 131 /* 132 * the firmware deals with up to 256 or 512 byte command frames. 133 */ 134 135 /* 136 * sizeof(struct arc_msg_scsicmd) + (sizeof(struct arc_sge) * 38) == 508. 137 */ 138 #define ARC_SGL_MAXLEN 38 139 /* 140 * sizeof(struct arc_msg_scsicmd) + (sizeof(struct arc_sge) * 17) == 252. 141 */ 142 #define ARC_SGL_256LEN 17 143 144 struct arc_io_cmd { 145 struct arc_msg_scsicmd cmd; 146 struct arc_sge sgl[ARC_SGL_MAXLEN]; 147 } __packed; 148 149 /* 150 * definitions of the firmware commands sent via the doorbells. 151 */ 152 struct arc_fw_hdr { 153 uint8_t byte1; 154 uint8_t byte2; 155 uint8_t byte3; 156 } __packed; 157 158 struct arc_fw_bufhdr { 159 struct arc_fw_hdr hdr; 160 uint16_t len; 161 } __packed; 162 163 /* Firmware command codes */ 164 #define ARC_FW_CHECK_PASS 0x14 /* opcode + 1 byte length + password */ 165 #define ARC_FW_GETEVENTS 0x1a /* opcode + 1 byte for page 0/1/2/3 */ 166 #define ARC_FW_RAIDINFO 0x20 /* opcode + raid# */ 167 #define ARC_FW_VOLINFO 0x21 /* opcode + vol# */ 168 #define ARC_FW_DISKINFO 0x22 /* opcode + physdisk# */ 169 #define ARC_FW_SYSINFO 0x23 /* opcode. reply is fw_sysinfo */ 170 #define ARC_FW_CLEAREVENTS 0x24 /* opcode only */ 171 #define ARC_FW_MUTE_ALARM 0x30 /* opcode only */ 172 #define ARC_FW_SET_ALARM 0x31 /* opcode + 1 byte for setting */ 173 #define ARC_FW_SET_ALARM_DISABLE 0x00 174 #define ARC_FW_SET_ALARM_ENABLE 0x01 175 #define ARC_FW_SET_PASS 0x32 /* opcode + 1 byte length + password */ 176 #define ARC_FW_REBUILD_PRIO 0x34 /* Rebuild priority for disks */ 177 #define ARC_FW_REBUILD_PRIO_ULTRALOW (1<<0) 178 #define ARC_FW_REBUILD_PRIO_LOW (1<<1) 179 #define ARC_FW_REBUILD_PRIO_NORMAL (1<<2) 180 #define ARC_FW_REBUILD_PRIO_HIGH (1<<3) 181 #define ARC_FW_SET_MAXATA_MODE 0x35 /* opcode + 1 byte mode */ 182 #define ARC_FW_SET_MAXATA_MODE_133 (1<<0) 183 #define ARC_FW_SET_MAXATA_MODE_100 (1<<1) 184 #define ARC_FW_SET_MAXATA_MODE_66 (1<<2) 185 #define ARC_FW_SET_MAXATA_MODE_33 (1<<3) 186 #define ARC_FW_NOP 0x38 /* opcode only */ 187 188 /* Status codes for the firmware command codes */ 189 #define ARC_FW_CMD_OK 0x41 190 #define ARC_FW_CMD_RAIDINVAL 0x42 191 #define ARC_FW_CMD_VOLINVAL 0x43 192 #define ARC_FW_CMD_NORAID 0x44 193 #define ARC_FW_CMD_NOVOLUME 0x45 194 #define ARC_FW_CMD_NOPHYSDRV 0x46 195 #define ARC_FW_CMD_PARAM_ERR 0x47 196 #define ARC_FW_CMD_UNSUPPORTED 0x48 197 #define ARC_FW_CMD_DISKCFG_CHGD 0x49 198 #define ARC_FW_CMD_PASS_INVAL 0x4a 199 #define ARC_FW_CMD_NODISKSPACE 0x4b 200 #define ARC_FW_CMD_PASS_REQD 0x4d 201 #define ARC_FW_CMD_CHECKSUM_ERR 0x4c 202 203 struct arc_fw_comminfo { 204 uint8_t baud_rate; 205 uint8_t data_bits; 206 uint8_t stop_bits; 207 uint8_t parity; 208 uint8_t flow_control; 209 } __packed; 210 211 struct arc_fw_scsiattr { 212 uint8_t channel; /* channel for SCSI target (0/1) */ 213 uint8_t target; 214 uint8_t lun; 215 uint8_t tagged; 216 uint8_t cache; 217 uint8_t speed; 218 } __packed; 219 220 struct arc_fw_raidinfo { 221 uint8_t set_name[16]; 222 uint32_t capacity; 223 uint32_t capacity2; 224 uint32_t fail_mask; 225 uint8_t device_array[32]; 226 uint8_t member_devices; 227 uint8_t new_member_devices; 228 uint8_t raid_state; 229 uint8_t volumes; 230 uint8_t volume_list[16]; 231 uint8_t reserved1[3]; 232 uint8_t free_segments; 233 uint32_t raw_stripes[8]; 234 uint8_t reserved2[12]; 235 } __packed; 236 237 struct arc_fw_volinfo { 238 uint8_t set_name[16]; 239 uint32_t capacity; 240 uint32_t capacity2; 241 uint32_t fail_mask; 242 uint32_t stripe_size; /* in blocks */ 243 uint32_t new_fail_mask; 244 uint32_t new_stripe_size; 245 uint32_t volume_status; 246 #define ARC_FW_VOL_STATUS_NORMAL 0x00 247 #define ARC_FW_VOL_STATUS_INITTING (1<<0) 248 #define ARC_FW_VOL_STATUS_FAILED (1<<1) 249 #define ARC_FW_VOL_STATUS_MIGRATING (1<<2) 250 #define ARC_FW_VOL_STATUS_REBUILDING (1<<3) 251 #define ARC_FW_VOL_STATUS_NEED_INIT (1<<4) 252 #define ARC_FW_VOL_STATUS_NEED_MIGRATE (1<<5) 253 #define ARC_FW_VOL_STATUS_INIT_FLAG (1<<6) 254 #define ARC_FW_VOL_STATUS_NEED_REGEN (1<<7) 255 #define ARC_FW_VOL_STATUS_CHECKING (1<<8) 256 #define ARC_FW_VOL_STATUS_NEED_CHECK (1<<9) 257 uint32_t progress; 258 struct arc_fw_scsiattr scsi_attr; 259 uint8_t member_disks; 260 uint8_t raid_level; 261 #define ARC_FW_VOL_RAIDLEVEL_0 0x00 262 #define ARC_FW_VOL_RAIDLEVEL_1 0x01 263 #define ARC_FW_VOL_RAIDLEVEL_3 0x02 264 #define ARC_FW_VOL_RAIDLEVEL_5 0x03 265 #define ARC_FW_VOL_RAIDLEVEL_6 0x04 266 #define ARC_FW_VOL_RAIDLEVEL_PASSTHRU 0x05 267 uint8_t new_member_disks; 268 uint8_t new_raid_level; 269 uint8_t raid_set_number; 270 uint8_t reserved[5]; 271 } __packed; 272 273 struct arc_fw_diskinfo { 274 uint8_t model[40]; 275 uint8_t serial[20]; 276 uint8_t firmware_rev[8]; 277 uint32_t capacity; 278 uint32_t capacity2; 279 uint8_t device_state; 280 uint8_t pio_mode; 281 uint8_t current_udma_mode; 282 uint8_t udma_mode; 283 uint8_t drive_select; 284 uint8_t raid_number; /* 0xff unowned */ 285 struct arc_fw_scsiattr scsi_attr; 286 uint8_t reserved[40]; 287 } __packed; 288 289 struct arc_fw_sysinfo { 290 uint8_t vendor_name[40]; 291 uint8_t serial_number[16]; 292 uint8_t firmware_version[16]; 293 uint8_t boot_version[16]; 294 uint8_t mb_version[16]; 295 uint8_t model_name[8]; 296 297 uint8_t local_ip[4]; 298 uint8_t current_ip[4]; 299 300 uint32_t time_tick; 301 uint32_t cpu_speed; 302 uint32_t icache; 303 uint32_t dcache; 304 uint32_t scache; 305 uint32_t memory_size; 306 uint32_t memory_speed; 307 uint32_t events; 308 309 uint8_t gsiMacAddress[6]; 310 uint8_t gsiDhcp; 311 312 uint8_t alarm; 313 uint8_t channel_usage; 314 uint8_t max_ata_mode; 315 uint8_t sdram_ecc; 316 uint8_t rebuild_priority; 317 struct arc_fw_comminfo comm_a; 318 struct arc_fw_comminfo comm_b; 319 uint8_t ide_channels; 320 uint8_t scsi_host_channels; 321 uint8_t ide_host_channels; 322 uint8_t max_volume_set; 323 uint8_t max_raid_set; 324 uint8_t ether_port; 325 uint8_t raid6_engine; 326 uint8_t reserved[75]; 327 } __packed; 328 329 /* 330 * autconf(9) glue. 331 */ 332 struct arc_ccb; 333 TAILQ_HEAD(arc_ccb_list, arc_ccb); 334 335 struct arc_softc { 336 struct device sc_dev; 337 struct scsipi_channel sc_chan; 338 struct scsipi_adapter sc_adapter; 339 340 pci_chipset_tag_t sc_pc; 341 pcitag_t sc_tag; 342 343 bus_space_tag_t sc_iot; 344 bus_space_handle_t sc_ioh; 345 bus_size_t sc_ios; 346 bus_dma_tag_t sc_dmat; 347 348 void *sc_ih; 349 350 void *sc_shutdownhook; 351 352 int sc_req_count; 353 354 struct arc_dmamem *sc_requests; 355 struct arc_ccb *sc_ccbs; 356 struct arc_ccb_list sc_ccb_free; 357 358 struct lwp *sc_lwp; 359 volatile int sc_talking; 360 kmutex_t sc_mutex; 361 kcondvar_t sc_condvar; 362 krwlock_t sc_rwlock; 363 364 struct sysmon_envsys *sc_sme; 365 envsys_data_t *sc_sensors; 366 int sc_nsensors; 367 }; 368 369 /* 370 * interface for scsi midlayer to talk to. 371 */ 372 void arc_scsi_cmd(struct scsipi_channel *, scsipi_adapter_req_t, void *); 373 374 /* 375 * code to deal with getting bits in and out of the bus space. 376 */ 377 uint32_t arc_read(struct arc_softc *, bus_size_t); 378 void arc_read_region(struct arc_softc *, bus_size_t, void *, size_t); 379 void arc_write(struct arc_softc *, bus_size_t, uint32_t); 380 void arc_write_region(struct arc_softc *, bus_size_t, void *, size_t); 381 int arc_wait_eq(struct arc_softc *, bus_size_t, uint32_t, uint32_t); 382 int arc_wait_ne(struct arc_softc *, bus_size_t, uint32_t, uint32_t); 383 int arc_msg0(struct arc_softc *, uint32_t); 384 385 #define arc_push(_s, _r) arc_write((_s), ARC_REG_POST_QUEUE, (_r)) 386 #define arc_pop(_s) arc_read((_s), ARC_REG_REPLY_QUEUE) 387 388 /* 389 * wrap up the bus_dma api. 390 */ 391 struct arc_dmamem { 392 bus_dmamap_t adm_map; 393 bus_dma_segment_t adm_seg; 394 size_t adm_size; 395 void *adm_kva; 396 }; 397 #define ARC_DMA_MAP(_adm) ((_adm)->adm_map) 398 #define ARC_DMA_DVA(_adm) ((_adm)->adm_map->dm_segs[0].ds_addr) 399 #define ARC_DMA_KVA(_adm) ((void *)(_adm)->adm_kva) 400 401 struct arc_dmamem *arc_dmamem_alloc(struct arc_softc *, size_t); 402 void arc_dmamem_free(struct arc_softc *, struct arc_dmamem *); 403 404 /* 405 * stuff to manage a scsi command. 406 */ 407 struct arc_ccb { 408 struct arc_softc *ccb_sc; 409 int ccb_id; 410 411 struct scsipi_xfer *ccb_xs; 412 413 bus_dmamap_t ccb_dmamap; 414 bus_addr_t ccb_offset; 415 struct arc_io_cmd *ccb_cmd; 416 uint32_t ccb_cmd_post; 417 418 TAILQ_ENTRY(arc_ccb) ccb_link; 419 }; 420 421 int arc_alloc_ccbs(struct arc_softc *); 422 struct arc_ccb *arc_get_ccb(struct arc_softc *); 423 void arc_put_ccb(struct arc_softc *, struct arc_ccb *); 424 int arc_load_xs(struct arc_ccb *); 425 int arc_complete(struct arc_softc *, struct arc_ccb *, int); 426 void arc_scsi_cmd_done(struct arc_softc *, struct arc_ccb *, uint32_t); 427 428 /* 429 * real stuff for dealing with the hardware. 430 */ 431 int arc_map_pci_resources(struct arc_softc *, struct pci_attach_args *); 432 void arc_unmap_pci_resources(struct arc_softc *); 433 int arc_query_firmware(struct arc_softc *); 434 435 /* 436 * stuff to do messaging via the doorbells. 437 */ 438 void arc_lock(struct arc_softc *); 439 void arc_unlock(struct arc_softc *); 440 void arc_wait(struct arc_softc *); 441 uint8_t arc_msg_cksum(void *, uint16_t); 442 int arc_msgbuf(struct arc_softc *, void *, size_t, void *, size_t); 443 444 #endif /* ! _PCI_ARCMSRVAR_H_ */ 445
Indexes created Wed Oct 22 13:09:56 GMT 2025