artsata.c revision 1.11
1 /* $NetBSD: artsata.c,v 1.11 2006/06/26 17:55:49 xtraeme Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_pciide.h" 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: artsata.c,v 1.11 2006/06/26 17:55:49 xtraeme Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/malloc.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 #include <dev/pci/pciidereg.h> 51 #include <dev/pci/pciidevar.h> 52 #include <dev/pci/pciide_i31244_reg.h> 53 54 #include <dev/ata/satareg.h> 55 #include <dev/ata/satavar.h> 56 #include <dev/ata/atareg.h> 57 #include <dev/ata/atavar.h> 58 59 static void artisea_chip_map(struct pciide_softc*, struct pci_attach_args *); 60 61 static int artsata_match(struct device *, struct cfdata *, void *); 62 static void artsata_attach(struct device *, struct device *, void *); 63 64 static const struct pciide_product_desc pciide_artsata_products[] = { 65 { PCI_PRODUCT_INTEL_31244, 66 0, 67 "Intel 31244 Serial ATA Controller", 68 artisea_chip_map, 69 }, 70 { 0, 71 0, 72 NULL, 73 NULL 74 } 75 }; 76 77 struct artisea_cmd_map 78 { 79 u_int8_t offset; 80 u_int8_t size; 81 }; 82 83 static const struct artisea_cmd_map artisea_dpa_cmd_map[] = 84 { 85 {ARTISEA_SUPDDR, 4}, /* 0 Data */ 86 {ARTISEA_SUPDER, 1}, /* 1 Error */ 87 {ARTISEA_SUPDCSR, 2}, /* 2 Sector Count */ 88 {ARTISEA_SUPDSNR, 2}, /* 3 Sector Number */ 89 {ARTISEA_SUPDCLR, 2}, /* 4 Cylinder Low */ 90 {ARTISEA_SUPDCHR, 2}, /* 5 Cylinder High */ 91 {ARTISEA_SUPDDHR, 1}, /* 6 Device/Head */ 92 {ARTISEA_SUPDCR, 1}, /* 7 Command */ 93 {ARTISEA_SUPDSR, 1}, /* 8 Status */ 94 {ARTISEA_SUPDFR, 2} /* 9 Feature */ 95 }; 96 97 #define ARTISEA_NUM_CHAN 4 98 99 CFATTACH_DECL(artsata, sizeof(struct pciide_softc), 100 artsata_match, artsata_attach, NULL, NULL); 101 102 static int 103 artsata_match(struct device *parent, struct cfdata *match, void *aux) 104 { 105 struct pci_attach_args *pa = aux; 106 107 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 108 if (pciide_lookup_product(pa->pa_id, pciide_artsata_products)) 109 return (2); 110 } 111 return (0); 112 } 113 114 static void 115 artsata_attach(struct device *parent, struct device *self, void *aux) 116 { 117 struct pci_attach_args *pa = aux; 118 struct pciide_softc *sc = (struct pciide_softc *)self; 119 120 pciide_common_attach(sc, pa, 121 pciide_lookup_product(pa->pa_id, pciide_artsata_products)); 122 123 } 124 125 static void 126 artisea_drv_probe(struct ata_channel *chp) 127 { 128 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 129 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 130 uint32_t scontrol, sstatus; 131 uint16_t scnt, sn, cl, ch; 132 int i, s; 133 134 /* XXX This should be done by other code. */ 135 for (i = 0; i < 2; i++) { 136 chp->ch_drive[i].chnl_softc = chp; 137 chp->ch_drive[i].drive = i; 138 } 139 140 /* 141 * First we have to bring the PHYs online, in case the firmware 142 * has not already done so. The 31244 leaves the disks off-line 143 * on reset to avoid excessive power surges due to multiple spindle 144 * spin up. 145 * 146 * The work-around for errata #1 says that we must write 0 to the 147 * port first to be sure of correctly initializing the device. 148 * 149 * XXX will this try to bring multiple disks on-line too quickly? 150 */ 151 bus_space_write_4 (wdr->cmd_iot, wdr->cmd_baseioh, 152 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, 0); 153 scontrol = SControl_IPM_NONE | SControl_SPD_ANY | SControl_DET_INIT; 154 bus_space_write_4 (wdr->cmd_iot, wdr->cmd_baseioh, 155 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, scontrol); 156 157 scontrol &= ~SControl_DET_INIT; 158 bus_space_write_4 (wdr->cmd_iot, wdr->cmd_baseioh, 159 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, scontrol); 160 161 delay(50 * 1000); 162 sstatus = bus_space_read_4(wdr->cmd_iot, wdr->cmd_baseioh, 163 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSSR); 164 165 switch (sstatus & SStatus_DET_mask) { 166 case SStatus_DET_NODEV: 167 /* No Device; be silent. */ 168 break; 169 170 case SStatus_DET_DEV_NE: 171 aprint_error("%s: port %d: device connected, but " 172 "communication not established\n", 173 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 174 break; 175 176 case SStatus_DET_OFFLINE: 177 aprint_error("%s: port %d: PHY offline\n", 178 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 179 break; 180 181 case SStatus_DET_DEV: 182 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 183 WDSD_IBM); 184 delay(10); /* 400ns delay */ 185 scnt = bus_space_read_2(wdr->cmd_iot, 186 wdr->cmd_iohs[wd_seccnt], 0); 187 sn = bus_space_read_2(wdr->cmd_iot, 188 wdr->cmd_iohs[wd_sector], 0); 189 cl = bus_space_read_2(wdr->cmd_iot, 190 wdr->cmd_iohs[wd_cyl_lo], 0); 191 ch = bus_space_read_2(wdr->cmd_iot, 192 wdr->cmd_iohs[wd_cyl_hi], 0); 193 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 194 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 195 scnt, sn, cl, ch); 196 /* 197 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 198 * cases we get wrong values here, so ignore it. 199 */ 200 s = splbio(); 201 if (cl == 0x14 && ch == 0xeb) 202 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 203 else 204 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 205 splx(s); 206 207 aprint_normal("%s: port %d: device present, speed: %s\n", 208 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 209 sata_speed(sstatus)); 210 break; 211 212 default: 213 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 214 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 215 sstatus); 216 } 217 218 } 219 220 static void 221 artisea_mapregs(struct pci_attach_args *pa, struct pciide_channel *cp, 222 bus_size_t *cmdsizep, bus_size_t *ctlsizep, int (*pci_intr)(void *)) 223 { 224 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 225 struct ata_channel *wdc_cp = &cp->ata_channel; 226 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 227 const char *intrstr; 228 pci_intr_handle_t intrhandle; 229 int i; 230 231 cp->compat = 0; 232 233 if (sc->sc_pci_ih == NULL) { 234 if (pci_intr_map(pa, &intrhandle) != 0) { 235 aprint_error("%s: couldn't map native-PCI interrupt\n", 236 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 237 goto bad; 238 } 239 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 240 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 241 intrhandle, IPL_BIO, pci_intr, sc); 242 if (sc->sc_pci_ih != NULL) { 243 aprint_normal("%s: using %s for native-PCI interrupt\n", 244 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 245 intrstr ? intrstr : "unknown interrupt"); 246 } else { 247 aprint_error( 248 "%s: couldn't establish native-PCI interrupt", 249 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 250 if (intrstr != NULL) 251 aprint_normal(" at %s", intrstr); 252 aprint_normal("\n"); 253 goto bad; 254 } 255 } 256 cp->ih = sc->sc_pci_ih; 257 wdr->cmd_iot = sc->sc_ba5_st; 258 if (bus_space_subregion (sc->sc_ba5_st, sc->sc_ba5_sh, 259 ARTISEA_DPA_PORT_BASE(wdc_cp->ch_channel), 0x200, 260 &wdr->cmd_baseioh) != 0) { 261 aprint_error("%s: couldn't map %s channel cmd regs\n", 262 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 263 goto bad; 264 } 265 266 wdr->ctl_iot = sc->sc_ba5_st; 267 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 268 ARTISEA_SUPDDCTLR, 1, &cp->ctl_baseioh) != 0) { 269 aprint_error("%s: couldn't map %s channel ctl regs\n", 270 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 271 goto bad; 272 } 273 wdr->ctl_ioh = cp->ctl_baseioh; 274 275 for (i = 0; i < WDC_NREG + 2; i++) { 276 277 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 278 artisea_dpa_cmd_map[i].offset, artisea_dpa_cmd_map[i].size, 279 &wdr->cmd_iohs[i]) != 0) { 280 aprint_error("%s: couldn't subregion %s channel " 281 "cmd regs\n", 282 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 283 goto bad; 284 } 285 } 286 wdr->data32iot = wdr->cmd_iot; 287 wdr->data32ioh = wdr->cmd_iohs[0]; 288 289 wdcattach(wdc_cp); 290 return; 291 292 bad: 293 cp->ata_channel.ch_flags |= ATACH_DISABLED; 294 return; 295 } 296 297 static int 298 artisea_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface) 299 { 300 struct pciide_channel *cp = &sc->pciide_channels[channel]; 301 sc->wdc_chanarray[channel] = &cp->ata_channel; 302 cp->name = PCIIDE_CHANNEL_NAME(channel); 303 cp->ata_channel.ch_channel = channel; 304 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 305 cp->ata_channel.ch_queue = 306 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 307 cp->ata_channel.ch_ndrive = 2; 308 if (cp->ata_channel.ch_queue == NULL) { 309 aprint_error("%s %s channel: " 310 "can't allocate memory for command queue", 311 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 312 return 0; 313 } 314 return 1; 315 } 316 317 static void 318 artisea_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 319 { 320 struct pciide_channel *pc; 321 int chan; 322 u_int32_t dma_ctl; 323 u_int32_t cacheline_len; 324 325 aprint_normal("%s: bus-master DMA support present", 326 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 327 328 sc->sc_dma_ok = 1; 329 330 /* 331 * Errata #4 says that if the cacheline length is not set correctly, 332 * we can get corrupt MWI and Memory-Block-Write transactions. 333 */ 334 cacheline_len = PCI_CACHELINE(pci_conf_read (pa->pa_pc, pa->pa_tag, 335 PCI_BHLC_REG)); 336 if (cacheline_len == 0) { 337 aprint_normal(", but unused (cacheline size not set in PCI conf)\n"); 338 sc->sc_dma_ok = 0; 339 return; 340 } 341 342 /* 343 * Final step of the work-around is to force the DMA engine to use 344 * the cache-line length information. 345 */ 346 dma_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR); 347 dma_ctl |= SUDCSCR_DMA_WCAE | SUDCSCR_DMA_RCAE; 348 pci_conf_write(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR, dma_ctl); 349 350 sc->sc_wdcdev.dma_arg = sc; 351 sc->sc_wdcdev.dma_init = pciide_dma_init; 352 sc->sc_wdcdev.dma_start = pciide_dma_start; 353 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 354 sc->sc_dma_iot = sc->sc_ba5_st; 355 sc->sc_dmat = pa->pa_dmat; 356 357 if (device_cfdata(&sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 358 PCIIDE_OPTIONS_NODMA) { 359 aprint_normal( 360 ", but unused (forced off by config file)\n"); 361 sc->sc_dma_ok = 0; 362 return; 363 } 364 365 /* 366 * Set up the default handles for the DMA registers. 367 * Just reserve 32 bits for each handle, unless space 368 * doesn't permit it. 369 */ 370 for (chan = 0; chan < ARTISEA_NUM_CHAN; chan++) { 371 pc = &sc->pciide_channels[chan]; 372 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 373 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDCMDR, 2, 374 &pc->dma_iohs[IDEDMA_CMD]) != 0 || 375 bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 376 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDSR, 1, 377 &pc->dma_iohs[IDEDMA_CTL]) != 0 || 378 bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 379 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDDTPR, 4, 380 &pc->dma_iohs[IDEDMA_TBL]) != 0) { 381 sc->sc_dma_ok = 0; 382 aprint_normal(", but can't subregion registers\n"); 383 return; 384 } 385 } 386 387 aprint_normal("\n"); 388 } 389 390 static void 391 artisea_chip_map_dpa(struct pciide_softc *sc, struct pci_attach_args *pa) 392 { 393 struct pciide_channel *cp; 394 bus_size_t cmdsize, ctlsize; 395 pcireg_t interface; 396 int channel; 397 398 interface = PCI_INTERFACE(pa->pa_class); 399 400 aprint_normal("%s: interface wired in DPA mode\n", 401 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 402 403 if (pci_mapreg_map(pa, ARTISEA_PCI_DPA_BASE, PCI_MAPREG_MEM_TYPE_64BIT, 404 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, NULL) != 0) 405 return; 406 407 artisea_mapreg_dma(sc, pa); 408 409 sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS; 410 411 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 412 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 413 if (sc->sc_dma_ok) { 414 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 415 sc->sc_wdcdev.irqack = pciide_irqack; 416 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 417 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 418 } 419 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 420 421 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 422 sc->sc_wdcdev.sc_atac.atac_nchannels = ARTISEA_NUM_CHAN; 423 sc->sc_wdcdev.sc_atac.atac_probe = artisea_drv_probe; 424 425 wdc_allocate_regs(&sc->sc_wdcdev); 426 427 /* 428 * Perform a quick check to ensure that the device isn't configured 429 * in Spread-spectrum clocking mode. This feature is buggy and has 430 * been removed from the latest documentation. 431 * 432 * Note that although this bit is in the Channel regs, it's the same 433 * for all channels, so we check it just once here. 434 */ 435 if ((bus_space_read_4 (sc->sc_ba5_st, sc->sc_ba5_sh, 436 ARTISEA_DPA_PORT_BASE(0) + ARTISEA_SUPERSET_DPA_OFF + 437 ARTISEA_SUPDPFR) & SUPDPFR_SSCEN) != 0) { 438 aprint_error("%s: Spread-specturm clocking not supported by device\n", 439 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 440 return; 441 } 442 443 /* Clear the LED0-only bit. */ 444 pci_conf_write (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0, 445 pci_conf_read (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0) & 446 ~SUECSR0_LED0_ONLY); 447 448 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 449 channel++) { 450 cp = &sc->pciide_channels[channel]; 451 if (artisea_chansetup(sc, channel, interface) == 0) 452 continue; 453 /* XXX We can probably do interrupts more efficiently. */ 454 artisea_mapregs(pa, cp, &cmdsize, &ctlsize, pciide_pci_intr); 455 } 456 } 457 458 static void 459 artisea_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 460 { 461 struct pciide_channel *cp; 462 bus_size_t cmdsize, ctlsize; 463 pcireg_t interface; 464 int channel; 465 466 if (pciide_chipen(sc, pa) == 0) 467 return; 468 469 interface = PCI_INTERFACE(pa->pa_class); 470 471 if (interface == 0) { 472 artisea_chip_map_dpa (sc, pa); 473 return; 474 } 475 476 aprint_normal("%s: bus-master DMA support present", 477 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 478 #ifdef PCIIDE_I31244_DISABLEDMA 479 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 && 480 PCI_REVISION(pa->pa_class) == 0) { 481 aprint_normal(" but disabled due to rev. 0"); 482 sc->sc_dma_ok = 0; 483 } else 484 #endif 485 pciide_mapreg_dma(sc, pa); 486 aprint_normal("\n"); 487 488 /* 489 * XXX Configure LEDs to show activity. 490 */ 491 492 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 493 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 494 if (sc->sc_dma_ok) { 495 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 496 sc->sc_wdcdev.irqack = pciide_irqack; 497 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 498 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 499 } 500 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 501 502 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 503 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 504 505 wdc_allocate_regs(&sc->sc_wdcdev); 506 507 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 508 channel++) { 509 cp = &sc->pciide_channels[channel]; 510 if (pciide_chansetup(sc, channel, interface) == 0) 511 continue; 512 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 513 pciide_pci_intr); 514 } 515 } 516
Indexes created Wed Sep 24 05:09:52 GMT 2025