artsata.c revision 1.12
1 /* $NetBSD: artsata.c,v 1.12 2006/10/12 01:31:28 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_pciide.h" 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: artsata.c,v 1.12 2006/10/12 01:31:28 christos Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/malloc.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 #include <dev/pci/pciidereg.h> 51 #include <dev/pci/pciidevar.h> 52 #include <dev/pci/pciide_i31244_reg.h> 53 54 #include <dev/ata/satareg.h> 55 #include <dev/ata/satavar.h> 56 #include <dev/ata/atareg.h> 57 #include <dev/ata/atavar.h> 58 59 static void artisea_chip_map(struct pciide_softc*, struct pci_attach_args *); 60 61 static int artsata_match(struct device *, struct cfdata *, void *); 62 static void artsata_attach(struct device *, struct device *, void *); 63 64 static const struct pciide_product_desc pciide_artsata_products[] = { 65 { PCI_PRODUCT_INTEL_31244, 66 0, 67 "Intel 31244 Serial ATA Controller", 68 artisea_chip_map, 69 }, 70 { 0, 71 0, 72 NULL, 73 NULL 74 } 75 }; 76 77 struct artisea_cmd_map 78 { 79 u_int8_t offset; 80 u_int8_t size; 81 }; 82 83 static const struct artisea_cmd_map artisea_dpa_cmd_map[] = 84 { 85 {ARTISEA_SUPDDR, 4}, /* 0 Data */ 86 {ARTISEA_SUPDER, 1}, /* 1 Error */ 87 {ARTISEA_SUPDCSR, 2}, /* 2 Sector Count */ 88 {ARTISEA_SUPDSNR, 2}, /* 3 Sector Number */ 89 {ARTISEA_SUPDCLR, 2}, /* 4 Cylinder Low */ 90 {ARTISEA_SUPDCHR, 2}, /* 5 Cylinder High */ 91 {ARTISEA_SUPDDHR, 1}, /* 6 Device/Head */ 92 {ARTISEA_SUPDCR, 1}, /* 7 Command */ 93 {ARTISEA_SUPDSR, 1}, /* 8 Status */ 94 {ARTISEA_SUPDFR, 2} /* 9 Feature */ 95 }; 96 97 #define ARTISEA_NUM_CHAN 4 98 99 CFATTACH_DECL(artsata, sizeof(struct pciide_softc), 100 artsata_match, artsata_attach, NULL, NULL); 101 102 static int 103 artsata_match(struct device *parent __unused, struct cfdata *match __unused, 104 void *aux) 105 { 106 struct pci_attach_args *pa = aux; 107 108 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 109 if (pciide_lookup_product(pa->pa_id, pciide_artsata_products)) 110 return (2); 111 } 112 return (0); 113 } 114 115 static void 116 artsata_attach(struct device *parent __unused, struct device *self, void *aux) 117 { 118 struct pci_attach_args *pa = aux; 119 struct pciide_softc *sc = (struct pciide_softc *)self; 120 121 pciide_common_attach(sc, pa, 122 pciide_lookup_product(pa->pa_id, pciide_artsata_products)); 123 124 } 125 126 static void 127 artisea_drv_probe(struct ata_channel *chp) 128 { 129 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 130 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 131 uint32_t scontrol, sstatus; 132 uint16_t scnt, sn, cl, ch; 133 int i, s; 134 135 /* XXX This should be done by other code. */ 136 for (i = 0; i < 2; i++) { 137 chp->ch_drive[i].chnl_softc = chp; 138 chp->ch_drive[i].drive = i; 139 } 140 141 /* 142 * First we have to bring the PHYs online, in case the firmware 143 * has not already done so. The 31244 leaves the disks off-line 144 * on reset to avoid excessive power surges due to multiple spindle 145 * spin up. 146 * 147 * The work-around for errata #1 says that we must write 0 to the 148 * port first to be sure of correctly initializing the device. 149 * 150 * XXX will this try to bring multiple disks on-line too quickly? 151 */ 152 bus_space_write_4 (wdr->cmd_iot, wdr->cmd_baseioh, 153 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, 0); 154 scontrol = SControl_IPM_NONE | SControl_SPD_ANY | SControl_DET_INIT; 155 bus_space_write_4 (wdr->cmd_iot, wdr->cmd_baseioh, 156 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, scontrol); 157 158 scontrol &= ~SControl_DET_INIT; 159 bus_space_write_4 (wdr->cmd_iot, wdr->cmd_baseioh, 160 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, scontrol); 161 162 delay(50 * 1000); 163 sstatus = bus_space_read_4(wdr->cmd_iot, wdr->cmd_baseioh, 164 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSSR); 165 166 switch (sstatus & SStatus_DET_mask) { 167 case SStatus_DET_NODEV: 168 /* No Device; be silent. */ 169 break; 170 171 case SStatus_DET_DEV_NE: 172 aprint_error("%s: port %d: device connected, but " 173 "communication not established\n", 174 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 175 break; 176 177 case SStatus_DET_OFFLINE: 178 aprint_error("%s: port %d: PHY offline\n", 179 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 180 break; 181 182 case SStatus_DET_DEV: 183 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 184 WDSD_IBM); 185 delay(10); /* 400ns delay */ 186 scnt = bus_space_read_2(wdr->cmd_iot, 187 wdr->cmd_iohs[wd_seccnt], 0); 188 sn = bus_space_read_2(wdr->cmd_iot, 189 wdr->cmd_iohs[wd_sector], 0); 190 cl = bus_space_read_2(wdr->cmd_iot, 191 wdr->cmd_iohs[wd_cyl_lo], 0); 192 ch = bus_space_read_2(wdr->cmd_iot, 193 wdr->cmd_iohs[wd_cyl_hi], 0); 194 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 195 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 196 scnt, sn, cl, ch); 197 /* 198 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 199 * cases we get wrong values here, so ignore it. 200 */ 201 s = splbio(); 202 if (cl == 0x14 && ch == 0xeb) 203 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 204 else 205 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 206 splx(s); 207 208 aprint_normal("%s: port %d: device present, speed: %s\n", 209 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 210 sata_speed(sstatus)); 211 break; 212 213 default: 214 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 215 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 216 sstatus); 217 } 218 219 } 220 221 static void 222 artisea_mapregs(struct pci_attach_args *pa, struct pciide_channel *cp, 223 bus_size_t *cmdsizep __unused, bus_size_t *ctlsizep __unused, 224 int (*pci_intr)(void *)) 225 { 226 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 227 struct ata_channel *wdc_cp = &cp->ata_channel; 228 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 229 const char *intrstr; 230 pci_intr_handle_t intrhandle; 231 int i; 232 233 cp->compat = 0; 234 235 if (sc->sc_pci_ih == NULL) { 236 if (pci_intr_map(pa, &intrhandle) != 0) { 237 aprint_error("%s: couldn't map native-PCI interrupt\n", 238 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 239 goto bad; 240 } 241 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 242 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 243 intrhandle, IPL_BIO, pci_intr, sc); 244 if (sc->sc_pci_ih != NULL) { 245 aprint_normal("%s: using %s for native-PCI interrupt\n", 246 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 247 intrstr ? intrstr : "unknown interrupt"); 248 } else { 249 aprint_error( 250 "%s: couldn't establish native-PCI interrupt", 251 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 252 if (intrstr != NULL) 253 aprint_normal(" at %s", intrstr); 254 aprint_normal("\n"); 255 goto bad; 256 } 257 } 258 cp->ih = sc->sc_pci_ih; 259 wdr->cmd_iot = sc->sc_ba5_st; 260 if (bus_space_subregion (sc->sc_ba5_st, sc->sc_ba5_sh, 261 ARTISEA_DPA_PORT_BASE(wdc_cp->ch_channel), 0x200, 262 &wdr->cmd_baseioh) != 0) { 263 aprint_error("%s: couldn't map %s channel cmd regs\n", 264 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 265 goto bad; 266 } 267 268 wdr->ctl_iot = sc->sc_ba5_st; 269 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 270 ARTISEA_SUPDDCTLR, 1, &cp->ctl_baseioh) != 0) { 271 aprint_error("%s: couldn't map %s channel ctl regs\n", 272 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 273 goto bad; 274 } 275 wdr->ctl_ioh = cp->ctl_baseioh; 276 277 for (i = 0; i < WDC_NREG + 2; i++) { 278 279 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 280 artisea_dpa_cmd_map[i].offset, artisea_dpa_cmd_map[i].size, 281 &wdr->cmd_iohs[i]) != 0) { 282 aprint_error("%s: couldn't subregion %s channel " 283 "cmd regs\n", 284 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 285 goto bad; 286 } 287 } 288 wdr->data32iot = wdr->cmd_iot; 289 wdr->data32ioh = wdr->cmd_iohs[0]; 290 291 wdcattach(wdc_cp); 292 return; 293 294 bad: 295 cp->ata_channel.ch_flags |= ATACH_DISABLED; 296 return; 297 } 298 299 static int 300 artisea_chansetup(struct pciide_softc *sc, int channel, 301 pcireg_t interface __unused) 302 { 303 struct pciide_channel *cp = &sc->pciide_channels[channel]; 304 sc->wdc_chanarray[channel] = &cp->ata_channel; 305 cp->name = PCIIDE_CHANNEL_NAME(channel); 306 cp->ata_channel.ch_channel = channel; 307 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 308 cp->ata_channel.ch_queue = 309 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 310 cp->ata_channel.ch_ndrive = 2; 311 if (cp->ata_channel.ch_queue == NULL) { 312 aprint_error("%s %s channel: " 313 "can't allocate memory for command queue", 314 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 315 return 0; 316 } 317 return 1; 318 } 319 320 static void 321 artisea_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 322 { 323 struct pciide_channel *pc; 324 int chan; 325 u_int32_t dma_ctl; 326 u_int32_t cacheline_len; 327 328 aprint_normal("%s: bus-master DMA support present", 329 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 330 331 sc->sc_dma_ok = 1; 332 333 /* 334 * Errata #4 says that if the cacheline length is not set correctly, 335 * we can get corrupt MWI and Memory-Block-Write transactions. 336 */ 337 cacheline_len = PCI_CACHELINE(pci_conf_read (pa->pa_pc, pa->pa_tag, 338 PCI_BHLC_REG)); 339 if (cacheline_len == 0) { 340 aprint_normal(", but unused (cacheline size not set in PCI conf)\n"); 341 sc->sc_dma_ok = 0; 342 return; 343 } 344 345 /* 346 * Final step of the work-around is to force the DMA engine to use 347 * the cache-line length information. 348 */ 349 dma_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR); 350 dma_ctl |= SUDCSCR_DMA_WCAE | SUDCSCR_DMA_RCAE; 351 pci_conf_write(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR, dma_ctl); 352 353 sc->sc_wdcdev.dma_arg = sc; 354 sc->sc_wdcdev.dma_init = pciide_dma_init; 355 sc->sc_wdcdev.dma_start = pciide_dma_start; 356 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 357 sc->sc_dma_iot = sc->sc_ba5_st; 358 sc->sc_dmat = pa->pa_dmat; 359 360 if (device_cfdata(&sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 361 PCIIDE_OPTIONS_NODMA) { 362 aprint_normal( 363 ", but unused (forced off by config file)\n"); 364 sc->sc_dma_ok = 0; 365 return; 366 } 367 368 /* 369 * Set up the default handles for the DMA registers. 370 * Just reserve 32 bits for each handle, unless space 371 * doesn't permit it. 372 */ 373 for (chan = 0; chan < ARTISEA_NUM_CHAN; chan++) { 374 pc = &sc->pciide_channels[chan]; 375 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 376 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDCMDR, 2, 377 &pc->dma_iohs[IDEDMA_CMD]) != 0 || 378 bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 379 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDSR, 1, 380 &pc->dma_iohs[IDEDMA_CTL]) != 0 || 381 bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 382 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDDTPR, 4, 383 &pc->dma_iohs[IDEDMA_TBL]) != 0) { 384 sc->sc_dma_ok = 0; 385 aprint_normal(", but can't subregion registers\n"); 386 return; 387 } 388 } 389 390 aprint_normal("\n"); 391 } 392 393 static void 394 artisea_chip_map_dpa(struct pciide_softc *sc, struct pci_attach_args *pa) 395 { 396 struct pciide_channel *cp; 397 bus_size_t cmdsize, ctlsize; 398 pcireg_t interface; 399 int channel; 400 401 interface = PCI_INTERFACE(pa->pa_class); 402 403 aprint_normal("%s: interface wired in DPA mode\n", 404 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 405 406 if (pci_mapreg_map(pa, ARTISEA_PCI_DPA_BASE, PCI_MAPREG_MEM_TYPE_64BIT, 407 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, NULL) != 0) 408 return; 409 410 artisea_mapreg_dma(sc, pa); 411 412 sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS; 413 414 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 415 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 416 if (sc->sc_dma_ok) { 417 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 418 sc->sc_wdcdev.irqack = pciide_irqack; 419 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 420 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 421 } 422 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 423 424 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 425 sc->sc_wdcdev.sc_atac.atac_nchannels = ARTISEA_NUM_CHAN; 426 sc->sc_wdcdev.sc_atac.atac_probe = artisea_drv_probe; 427 428 wdc_allocate_regs(&sc->sc_wdcdev); 429 430 /* 431 * Perform a quick check to ensure that the device isn't configured 432 * in Spread-spectrum clocking mode. This feature is buggy and has 433 * been removed from the latest documentation. 434 * 435 * Note that although this bit is in the Channel regs, it's the same 436 * for all channels, so we check it just once here. 437 */ 438 if ((bus_space_read_4 (sc->sc_ba5_st, sc->sc_ba5_sh, 439 ARTISEA_DPA_PORT_BASE(0) + ARTISEA_SUPERSET_DPA_OFF + 440 ARTISEA_SUPDPFR) & SUPDPFR_SSCEN) != 0) { 441 aprint_error("%s: Spread-specturm clocking not supported by device\n", 442 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 443 return; 444 } 445 446 /* Clear the LED0-only bit. */ 447 pci_conf_write (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0, 448 pci_conf_read (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0) & 449 ~SUECSR0_LED0_ONLY); 450 451 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 452 channel++) { 453 cp = &sc->pciide_channels[channel]; 454 if (artisea_chansetup(sc, channel, interface) == 0) 455 continue; 456 /* XXX We can probably do interrupts more efficiently. */ 457 artisea_mapregs(pa, cp, &cmdsize, &ctlsize, pciide_pci_intr); 458 } 459 } 460 461 static void 462 artisea_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 463 { 464 struct pciide_channel *cp; 465 bus_size_t cmdsize, ctlsize; 466 pcireg_t interface; 467 int channel; 468 469 if (pciide_chipen(sc, pa) == 0) 470 return; 471 472 interface = PCI_INTERFACE(pa->pa_class); 473 474 if (interface == 0) { 475 artisea_chip_map_dpa (sc, pa); 476 return; 477 } 478 479 aprint_normal("%s: bus-master DMA support present", 480 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 481 #ifdef PCIIDE_I31244_DISABLEDMA 482 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 && 483 PCI_REVISION(pa->pa_class) == 0) { 484 aprint_normal(" but disabled due to rev. 0"); 485 sc->sc_dma_ok = 0; 486 } else 487 #endif 488 pciide_mapreg_dma(sc, pa); 489 aprint_normal("\n"); 490 491 /* 492 * XXX Configure LEDs to show activity. 493 */ 494 495 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 496 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 497 if (sc->sc_dma_ok) { 498 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 499 sc->sc_wdcdev.irqack = pciide_irqack; 500 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 501 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 502 } 503 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 504 505 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 506 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 507 508 wdc_allocate_regs(&sc->sc_wdcdev); 509 510 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 511 channel++) { 512 cp = &sc->pciide_channels[channel]; 513 if (pciide_chansetup(sc, channel, interface) == 0) 514 continue; 515 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 516 pciide_pci_intr); 517 } 518 } 519
Indexes created Wed Sep 24 15:09:51 GMT 2025