artsata.c revision 1.15
1 /* $NetBSD: artsata.c,v 1.15 2007/02/09 21:55:27 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_pciide.h" 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: artsata.c,v 1.15 2007/02/09 21:55:27 ad Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/malloc.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 #include <dev/pci/pciidereg.h> 51 #include <dev/pci/pciidevar.h> 52 #include <dev/pci/pciide_i31244_reg.h> 53 54 #include <dev/ata/satareg.h> 55 #include <dev/ata/satavar.h> 56 #include <dev/ata/atareg.h> 57 #include <dev/ata/atavar.h> 58 59 static void artisea_chip_map(struct pciide_softc*, struct pci_attach_args *); 60 61 static int artsata_match(struct device *, struct cfdata *, void *); 62 static void artsata_attach(struct device *, struct device *, void *); 63 64 static const struct pciide_product_desc pciide_artsata_products[] = { 65 { PCI_PRODUCT_INTEL_31244, 66 0, 67 "Intel 31244 Serial ATA Controller", 68 artisea_chip_map, 69 }, 70 { 0, 71 0, 72 NULL, 73 NULL 74 } 75 }; 76 77 struct artisea_cmd_map 78 { 79 u_int8_t offset; 80 u_int8_t size; 81 }; 82 83 static const struct artisea_cmd_map artisea_dpa_cmd_map[] = 84 { 85 {ARTISEA_SUPDDR, 4}, /* 0 Data */ 86 {ARTISEA_SUPDER, 1}, /* 1 Error */ 87 {ARTISEA_SUPDCSR, 2}, /* 2 Sector Count */ 88 {ARTISEA_SUPDSNR, 2}, /* 3 Sector Number */ 89 {ARTISEA_SUPDCLR, 2}, /* 4 Cylinder Low */ 90 {ARTISEA_SUPDCHR, 2}, /* 5 Cylinder High */ 91 {ARTISEA_SUPDDHR, 1}, /* 6 Device/Head */ 92 {ARTISEA_SUPDCR, 1}, /* 7 Command */ 93 {ARTISEA_SUPDSR, 1}, /* 8 Status */ 94 {ARTISEA_SUPDFR, 2} /* 9 Feature */ 95 }; 96 97 #define ARTISEA_NUM_CHAN 4 98 99 CFATTACH_DECL(artsata, sizeof(struct pciide_softc), 100 artsata_match, artsata_attach, NULL, NULL); 101 102 static int 103 artsata_match(struct device *parent, struct cfdata *match, 104 void *aux) 105 { 106 struct pci_attach_args *pa = aux; 107 108 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 109 if (pciide_lookup_product(pa->pa_id, pciide_artsata_products)) 110 return (2); 111 } 112 return (0); 113 } 114 115 static void 116 artsata_attach(struct device *parent, struct device *self, void *aux) 117 { 118 struct pci_attach_args *pa = aux; 119 struct pciide_softc *sc = (struct pciide_softc *)self; 120 121 pciide_common_attach(sc, pa, 122 pciide_lookup_product(pa->pa_id, pciide_artsata_products)); 123 124 } 125 126 static void 127 artisea_mapregs(struct pci_attach_args *pa, struct pciide_channel *cp, 128 bus_size_t *cmdsizep, bus_size_t *ctlsizep, 129 int (*pci_intr)(void *)) 130 { 131 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 132 struct ata_channel *wdc_cp = &cp->ata_channel; 133 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 134 const char *intrstr; 135 pci_intr_handle_t intrhandle; 136 int i; 137 138 cp->compat = 0; 139 140 if (sc->sc_pci_ih == NULL) { 141 if (pci_intr_map(pa, &intrhandle) != 0) { 142 aprint_error("%s: couldn't map native-PCI interrupt\n", 143 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 144 goto bad; 145 } 146 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 147 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 148 intrhandle, IPL_BIO, pci_intr, sc); 149 if (sc->sc_pci_ih != NULL) { 150 aprint_normal("%s: using %s for native-PCI interrupt\n", 151 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 152 intrstr ? intrstr : "unknown interrupt"); 153 } else { 154 aprint_error( 155 "%s: couldn't establish native-PCI interrupt", 156 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 157 if (intrstr != NULL) 158 aprint_normal(" at %s", intrstr); 159 aprint_normal("\n"); 160 goto bad; 161 } 162 } 163 cp->ih = sc->sc_pci_ih; 164 wdr->cmd_iot = sc->sc_ba5_st; 165 if (bus_space_subregion (sc->sc_ba5_st, sc->sc_ba5_sh, 166 ARTISEA_DPA_PORT_BASE(wdc_cp->ch_channel), 0x200, 167 &wdr->cmd_baseioh) != 0) { 168 aprint_error("%s: couldn't map %s channel cmd regs\n", 169 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 170 goto bad; 171 } 172 173 wdr->ctl_iot = sc->sc_ba5_st; 174 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 175 ARTISEA_SUPDDCTLR, 1, &cp->ctl_baseioh) != 0) { 176 aprint_error("%s: couldn't map %s channel ctl regs\n", 177 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 178 goto bad; 179 } 180 wdr->ctl_ioh = cp->ctl_baseioh; 181 182 for (i = 0; i < WDC_NREG + 2; i++) { 183 184 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 185 artisea_dpa_cmd_map[i].offset, artisea_dpa_cmd_map[i].size, 186 &wdr->cmd_iohs[i]) != 0) { 187 aprint_error("%s: couldn't subregion %s channel " 188 "cmd regs\n", 189 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 190 goto bad; 191 } 192 } 193 wdr->data32iot = wdr->cmd_iot; 194 wdr->data32ioh = wdr->cmd_iohs[0]; 195 196 wdr->sata_iot = wdr->cmd_iot; 197 wdr->sata_baseioh = wdr->cmd_baseioh; 198 199 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 200 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSSR, 1, 201 &wdr->sata_status) != 0) { 202 aprint_error("%s: couldn't map channel %d " 203 "sata_status regs\n", 204 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 205 wdc_cp->ch_channel); 206 goto bad; 207 } 208 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 209 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSER, 1, 210 &wdr->sata_error) != 0) { 211 aprint_error("%s: couldn't map channel %d " 212 "sata_error regs\n", 213 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 214 wdc_cp->ch_channel); 215 goto bad; 216 } 217 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 218 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, 1, 219 &wdr->sata_control) != 0) { 220 aprint_error("%s: couldn't map channel %d " 221 "sata_control regs\n", 222 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 223 wdc_cp->ch_channel); 224 goto bad; 225 } 226 227 wdcattach(wdc_cp); 228 return; 229 230 bad: 231 wdc_cp->ch_flags |= ATACH_DISABLED; 232 return; 233 } 234 235 static int 236 artisea_chansetup(struct pciide_softc *sc, int channel, 237 pcireg_t interface) 238 { 239 struct pciide_channel *cp = &sc->pciide_channels[channel]; 240 sc->wdc_chanarray[channel] = &cp->ata_channel; 241 cp->name = PCIIDE_CHANNEL_NAME(channel); 242 cp->ata_channel.ch_channel = channel; 243 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 244 cp->ata_channel.ch_queue = 245 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 246 cp->ata_channel.ch_ndrive = 2; 247 if (cp->ata_channel.ch_queue == NULL) { 248 aprint_error("%s %s channel: " 249 "can't allocate memory for command queue", 250 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 251 return 0; 252 } 253 return 1; 254 } 255 256 static void 257 artisea_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 258 { 259 struct pciide_channel *pc; 260 int chan; 261 u_int32_t dma_ctl; 262 u_int32_t cacheline_len; 263 264 aprint_verbose("%s: bus-master DMA support present", 265 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 266 267 sc->sc_dma_ok = 1; 268 269 /* 270 * Errata #4 says that if the cacheline length is not set correctly, 271 * we can get corrupt MWI and Memory-Block-Write transactions. 272 */ 273 cacheline_len = PCI_CACHELINE(pci_conf_read (pa->pa_pc, pa->pa_tag, 274 PCI_BHLC_REG)); 275 if (cacheline_len == 0) { 276 aprint_verbose(", but unused (cacheline size not set in PCI conf)\n"); 277 sc->sc_dma_ok = 0; 278 return; 279 } 280 281 /* 282 * Final step of the work-around is to force the DMA engine to use 283 * the cache-line length information. 284 */ 285 dma_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR); 286 dma_ctl |= SUDCSCR_DMA_WCAE | SUDCSCR_DMA_RCAE; 287 pci_conf_write(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR, dma_ctl); 288 289 sc->sc_wdcdev.dma_arg = sc; 290 sc->sc_wdcdev.dma_init = pciide_dma_init; 291 sc->sc_wdcdev.dma_start = pciide_dma_start; 292 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 293 sc->sc_dma_iot = sc->sc_ba5_st; 294 sc->sc_dmat = pa->pa_dmat; 295 296 if (device_cfdata(&sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 297 PCIIDE_OPTIONS_NODMA) { 298 aprint_verbose( 299 ", but unused (forced off by config file)\n"); 300 sc->sc_dma_ok = 0; 301 return; 302 } 303 304 /* 305 * Set up the default handles for the DMA registers. 306 * Just reserve 32 bits for each handle, unless space 307 * doesn't permit it. 308 */ 309 for (chan = 0; chan < ARTISEA_NUM_CHAN; chan++) { 310 pc = &sc->pciide_channels[chan]; 311 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 312 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDCMDR, 2, 313 &pc->dma_iohs[IDEDMA_CMD]) != 0 || 314 bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 315 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDSR, 1, 316 &pc->dma_iohs[IDEDMA_CTL]) != 0 || 317 bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 318 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDDTPR, 4, 319 &pc->dma_iohs[IDEDMA_TBL]) != 0) { 320 sc->sc_dma_ok = 0; 321 aprint_verbose(", but can't subregion registers\n"); 322 return; 323 } 324 } 325 326 aprint_verbose("\n"); 327 } 328 329 static void 330 artisea_chip_map_dpa(struct pciide_softc *sc, struct pci_attach_args *pa) 331 { 332 struct pciide_channel *cp; 333 bus_size_t cmdsize, ctlsize; 334 pcireg_t interface; 335 int channel; 336 337 interface = PCI_INTERFACE(pa->pa_class); 338 339 aprint_normal("%s: interface wired in DPA mode\n", 340 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 341 342 if (pci_mapreg_map(pa, ARTISEA_PCI_DPA_BASE, PCI_MAPREG_MEM_TYPE_64BIT, 343 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, NULL) != 0) 344 return; 345 346 artisea_mapreg_dma(sc, pa); 347 348 sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS; 349 350 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 351 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 352 if (sc->sc_dma_ok) { 353 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 354 sc->sc_wdcdev.irqack = pciide_irqack; 355 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 356 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 357 } 358 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 359 360 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 361 sc->sc_wdcdev.sc_atac.atac_nchannels = ARTISEA_NUM_CHAN; 362 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 363 364 wdc_allocate_regs(&sc->sc_wdcdev); 365 366 /* 367 * Perform a quick check to ensure that the device isn't configured 368 * in Spread-spectrum clocking mode. This feature is buggy and has 369 * been removed from the latest documentation. 370 * 371 * Note that although this bit is in the Channel regs, it's the same 372 * for all channels, so we check it just once here. 373 */ 374 if ((bus_space_read_4 (sc->sc_ba5_st, sc->sc_ba5_sh, 375 ARTISEA_DPA_PORT_BASE(0) + ARTISEA_SUPERSET_DPA_OFF + 376 ARTISEA_SUPDPFR) & SUPDPFR_SSCEN) != 0) { 377 aprint_error("%s: Spread-specturm clocking not supported by device\n", 378 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 379 return; 380 } 381 382 /* Clear the LED0-only bit. */ 383 pci_conf_write (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0, 384 pci_conf_read (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0) & 385 ~SUECSR0_LED0_ONLY); 386 387 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 388 channel++) { 389 cp = &sc->pciide_channels[channel]; 390 if (artisea_chansetup(sc, channel, interface) == 0) 391 continue; 392 /* XXX We can probably do interrupts more efficiently. */ 393 artisea_mapregs(pa, cp, &cmdsize, &ctlsize, pciide_pci_intr); 394 } 395 } 396 397 static void 398 artisea_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 399 { 400 struct pciide_channel *cp; 401 bus_size_t cmdsize, ctlsize; 402 pcireg_t interface; 403 int channel; 404 405 if (pciide_chipen(sc, pa) == 0) 406 return; 407 408 interface = PCI_INTERFACE(pa->pa_class); 409 410 if (interface == 0) { 411 artisea_chip_map_dpa (sc, pa); 412 return; 413 } 414 415 aprint_verbose("%s: bus-master DMA support present", 416 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 417 #ifdef PCIIDE_I31244_DISABLEDMA 418 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 && 419 PCI_REVISION(pa->pa_class) == 0) { 420 aprint_verbose(" but disabled due to rev. 0"); 421 sc->sc_dma_ok = 0; 422 } else 423 #endif 424 pciide_mapreg_dma(sc, pa); 425 aprint_verbose("\n"); 426 427 /* 428 * XXX Configure LEDs to show activity. 429 */ 430 431 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 432 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 433 if (sc->sc_dma_ok) { 434 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 435 sc->sc_wdcdev.irqack = pciide_irqack; 436 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 437 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 438 } 439 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 440 441 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 442 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 443 444 wdc_allocate_regs(&sc->sc_wdcdev); 445 446 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 447 channel++) { 448 cp = &sc->pciide_channels[channel]; 449 if (pciide_chansetup(sc, channel, interface) == 0) 450 continue; 451 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 452 pciide_pci_intr); 453 } 454 } 455
Indexes created Tue Sep 23 14:10:03 GMT 2025