artsata.c revision 1.17
1 /* $NetBSD: artsata.c,v 1.17 2008/03/18 20:46:36 cube Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: artsata.c,v 1.17 2008/03/18 20:46:36 cube Exp $"); 41 42 #include "opt_pciide.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/malloc.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 #include <dev/pci/pciidereg.h> 51 #include <dev/pci/pciidevar.h> 52 #include <dev/pci/pciide_i31244_reg.h> 53 54 #include <dev/ata/satareg.h> 55 #include <dev/ata/satavar.h> 56 #include <dev/ata/atareg.h> 57 #include <dev/ata/atavar.h> 58 59 static void artisea_chip_map(struct pciide_softc*, struct pci_attach_args *); 60 61 static int artsata_match(device_t, cfdata_t, void *); 62 static void artsata_attach(device_t, device_t, void *); 63 64 static const struct pciide_product_desc pciide_artsata_products[] = { 65 { PCI_PRODUCT_INTEL_31244, 66 0, 67 "Intel 31244 Serial ATA Controller", 68 artisea_chip_map, 69 }, 70 { 0, 71 0, 72 NULL, 73 NULL 74 } 75 }; 76 77 struct artisea_cmd_map 78 { 79 u_int8_t offset; 80 u_int8_t size; 81 }; 82 83 static const struct artisea_cmd_map artisea_dpa_cmd_map[] = 84 { 85 {ARTISEA_SUPDDR, 4}, /* 0 Data */ 86 {ARTISEA_SUPDER, 1}, /* 1 Error */ 87 {ARTISEA_SUPDCSR, 2}, /* 2 Sector Count */ 88 {ARTISEA_SUPDSNR, 2}, /* 3 Sector Number */ 89 {ARTISEA_SUPDCLR, 2}, /* 4 Cylinder Low */ 90 {ARTISEA_SUPDCHR, 2}, /* 5 Cylinder High */ 91 {ARTISEA_SUPDDHR, 1}, /* 6 Device/Head */ 92 {ARTISEA_SUPDCR, 1}, /* 7 Command */ 93 {ARTISEA_SUPDSR, 1}, /* 8 Status */ 94 {ARTISEA_SUPDFR, 2} /* 9 Feature */ 95 }; 96 97 #define ARTISEA_NUM_CHAN 4 98 99 CFATTACH_DECL_NEW(artsata, sizeof(struct pciide_softc), 100 artsata_match, artsata_attach, NULL, NULL); 101 102 static int 103 artsata_match(device_t parent, cfdata_t match, void *aux) 104 { 105 struct pci_attach_args *pa = aux; 106 107 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 108 if (pciide_lookup_product(pa->pa_id, pciide_artsata_products)) 109 return (2); 110 } 111 return (0); 112 } 113 114 static void 115 artsata_attach(device_t parent, device_t self, void *aux) 116 { 117 struct pci_attach_args *pa = aux; 118 struct pciide_softc *sc = device_private(self); 119 120 sc->sc_wdcdev.sc_atac.atac_dev = self; 121 122 pciide_common_attach(sc, pa, 123 pciide_lookup_product(pa->pa_id, pciide_artsata_products)); 124 125 } 126 127 static void 128 artisea_mapregs(struct pci_attach_args *pa, struct pciide_channel *cp, 129 bus_size_t *cmdsizep, bus_size_t *ctlsizep, 130 int (*pci_intr)(void *)) 131 { 132 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 133 struct ata_channel *wdc_cp = &cp->ata_channel; 134 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 135 const char *intrstr; 136 pci_intr_handle_t intrhandle; 137 int i; 138 139 cp->compat = 0; 140 141 if (sc->sc_pci_ih == NULL) { 142 if (pci_intr_map(pa, &intrhandle) != 0) { 143 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 144 "couldn't map native-PCI interrupt\n"); 145 goto bad; 146 } 147 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 148 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 149 intrhandle, IPL_BIO, pci_intr, sc); 150 if (sc->sc_pci_ih != NULL) { 151 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 152 "using %s for native-PCI interrupt\n", 153 intrstr ? intrstr : "unknown interrupt"); 154 } else { 155 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 156 "couldn't establish native-PCI interrupt"); 157 if (intrstr != NULL) 158 aprint_normal(" at %s", intrstr); 159 aprint_normal("\n"); 160 goto bad; 161 } 162 } 163 cp->ih = sc->sc_pci_ih; 164 wdr->cmd_iot = sc->sc_ba5_st; 165 if (bus_space_subregion (sc->sc_ba5_st, sc->sc_ba5_sh, 166 ARTISEA_DPA_PORT_BASE(wdc_cp->ch_channel), 0x200, 167 &wdr->cmd_baseioh) != 0) { 168 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 169 "couldn't map %s channel cmd regs\n", cp->name); 170 goto bad; 171 } 172 173 wdr->ctl_iot = sc->sc_ba5_st; 174 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 175 ARTISEA_SUPDDCTLR, 1, &cp->ctl_baseioh) != 0) { 176 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 177 "couldn't map %s channel ctl regs\n", cp->name); 178 goto bad; 179 } 180 wdr->ctl_ioh = cp->ctl_baseioh; 181 182 for (i = 0; i < WDC_NREG + 2; i++) { 183 184 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 185 artisea_dpa_cmd_map[i].offset, artisea_dpa_cmd_map[i].size, 186 &wdr->cmd_iohs[i]) != 0) { 187 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 188 "couldn't subregion %s channel cmd regs\n", 189 cp->name); 190 goto bad; 191 } 192 } 193 wdr->data32iot = wdr->cmd_iot; 194 wdr->data32ioh = wdr->cmd_iohs[0]; 195 196 wdr->sata_iot = wdr->cmd_iot; 197 wdr->sata_baseioh = wdr->cmd_baseioh; 198 199 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 200 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSSR, 1, 201 &wdr->sata_status) != 0) { 202 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 203 "couldn't map channel %d sata_status regs\n", 204 wdc_cp->ch_channel); 205 goto bad; 206 } 207 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 208 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSER, 1, 209 &wdr->sata_error) != 0) { 210 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 211 "couldn't map channel %d sata_error regs\n", 212 wdc_cp->ch_channel); 213 goto bad; 214 } 215 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 216 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, 1, 217 &wdr->sata_control) != 0) { 218 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 219 "couldn't map channel %d sata_control regs\n", 220 wdc_cp->ch_channel); 221 goto bad; 222 } 223 224 wdcattach(wdc_cp); 225 return; 226 227 bad: 228 wdc_cp->ch_flags |= ATACH_DISABLED; 229 return; 230 } 231 232 static int 233 artisea_chansetup(struct pciide_softc *sc, int channel, 234 pcireg_t interface) 235 { 236 struct pciide_channel *cp = &sc->pciide_channels[channel]; 237 sc->wdc_chanarray[channel] = &cp->ata_channel; 238 cp->name = PCIIDE_CHANNEL_NAME(channel); 239 cp->ata_channel.ch_channel = channel; 240 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 241 cp->ata_channel.ch_queue = 242 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 243 cp->ata_channel.ch_ndrive = 2; 244 if (cp->ata_channel.ch_queue == NULL) { 245 aprint_error("%s %s channel: " 246 "can't allocate memory for command queue", 247 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 248 return 0; 249 } 250 return 1; 251 } 252 253 static void 254 artisea_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 255 { 256 struct pciide_channel *pc; 257 int chan; 258 u_int32_t dma_ctl; 259 u_int32_t cacheline_len; 260 261 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 262 "bus-master DMA support present"); 263 264 sc->sc_dma_ok = 1; 265 266 /* 267 * Errata #4 says that if the cacheline length is not set correctly, 268 * we can get corrupt MWI and Memory-Block-Write transactions. 269 */ 270 cacheline_len = PCI_CACHELINE(pci_conf_read (pa->pa_pc, pa->pa_tag, 271 PCI_BHLC_REG)); 272 if (cacheline_len == 0) { 273 aprint_verbose(", but unused (cacheline size not set in PCI conf)\n"); 274 sc->sc_dma_ok = 0; 275 return; 276 } 277 278 /* 279 * Final step of the work-around is to force the DMA engine to use 280 * the cache-line length information. 281 */ 282 dma_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR); 283 dma_ctl |= SUDCSCR_DMA_WCAE | SUDCSCR_DMA_RCAE; 284 pci_conf_write(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR, dma_ctl); 285 286 sc->sc_wdcdev.dma_arg = sc; 287 sc->sc_wdcdev.dma_init = pciide_dma_init; 288 sc->sc_wdcdev.dma_start = pciide_dma_start; 289 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 290 sc->sc_dma_iot = sc->sc_ba5_st; 291 sc->sc_dmat = pa->pa_dmat; 292 293 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 294 PCIIDE_OPTIONS_NODMA) { 295 aprint_verbose( 296 ", but unused (forced off by config file)\n"); 297 sc->sc_dma_ok = 0; 298 return; 299 } 300 301 /* 302 * Set up the default handles for the DMA registers. 303 * Just reserve 32 bits for each handle, unless space 304 * doesn't permit it. 305 */ 306 for (chan = 0; chan < ARTISEA_NUM_CHAN; chan++) { 307 pc = &sc->pciide_channels[chan]; 308 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 309 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDCMDR, 2, 310 &pc->dma_iohs[IDEDMA_CMD]) != 0 || 311 bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 312 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDSR, 1, 313 &pc->dma_iohs[IDEDMA_CTL]) != 0 || 314 bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 315 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDDTPR, 4, 316 &pc->dma_iohs[IDEDMA_TBL]) != 0) { 317 sc->sc_dma_ok = 0; 318 aprint_verbose(", but can't subregion registers\n"); 319 return; 320 } 321 } 322 323 aprint_verbose("\n"); 324 } 325 326 static void 327 artisea_chip_map_dpa(struct pciide_softc *sc, struct pci_attach_args *pa) 328 { 329 struct pciide_channel *cp; 330 bus_size_t cmdsize, ctlsize; 331 pcireg_t interface; 332 int channel; 333 334 interface = PCI_INTERFACE(pa->pa_class); 335 336 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 337 "interface wired in DPA mode\n"); 338 339 if (pci_mapreg_map(pa, ARTISEA_PCI_DPA_BASE, PCI_MAPREG_MEM_TYPE_64BIT, 340 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, NULL) != 0) 341 return; 342 343 artisea_mapreg_dma(sc, pa); 344 345 sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS; 346 347 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 348 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 349 if (sc->sc_dma_ok) { 350 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 351 sc->sc_wdcdev.irqack = pciide_irqack; 352 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 353 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 354 } 355 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 356 357 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 358 sc->sc_wdcdev.sc_atac.atac_nchannels = ARTISEA_NUM_CHAN; 359 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 360 361 wdc_allocate_regs(&sc->sc_wdcdev); 362 363 /* 364 * Perform a quick check to ensure that the device isn't configured 365 * in Spread-spectrum clocking mode. This feature is buggy and has 366 * been removed from the latest documentation. 367 * 368 * Note that although this bit is in the Channel regs, it's the same 369 * for all channels, so we check it just once here. 370 */ 371 if ((bus_space_read_4 (sc->sc_ba5_st, sc->sc_ba5_sh, 372 ARTISEA_DPA_PORT_BASE(0) + ARTISEA_SUPERSET_DPA_OFF + 373 ARTISEA_SUPDPFR) & SUPDPFR_SSCEN) != 0) { 374 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 375 "Spread-specturm clocking not supported by device\n"); 376 return; 377 } 378 379 /* Clear the LED0-only bit. */ 380 pci_conf_write (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0, 381 pci_conf_read (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0) & 382 ~SUECSR0_LED0_ONLY); 383 384 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 385 channel++) { 386 cp = &sc->pciide_channels[channel]; 387 if (artisea_chansetup(sc, channel, interface) == 0) 388 continue; 389 /* XXX We can probably do interrupts more efficiently. */ 390 artisea_mapregs(pa, cp, &cmdsize, &ctlsize, pciide_pci_intr); 391 } 392 } 393 394 static void 395 artisea_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 396 { 397 struct pciide_channel *cp; 398 bus_size_t cmdsize, ctlsize; 399 pcireg_t interface; 400 int channel; 401 402 if (pciide_chipen(sc, pa) == 0) 403 return; 404 405 interface = PCI_INTERFACE(pa->pa_class); 406 407 if (interface == 0) { 408 artisea_chip_map_dpa (sc, pa); 409 return; 410 } 411 412 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 413 "bus-master DMA support present"); 414 #ifdef PCIIDE_I31244_DISABLEDMA 415 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 && 416 PCI_REVISION(pa->pa_class) == 0) { 417 aprint_verbose(" but disabled due to rev. 0"); 418 sc->sc_dma_ok = 0; 419 } else 420 #endif 421 pciide_mapreg_dma(sc, pa); 422 aprint_verbose("\n"); 423 424 /* 425 * XXX Configure LEDs to show activity. 426 */ 427 428 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 429 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 430 if (sc->sc_dma_ok) { 431 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 432 sc->sc_wdcdev.irqack = pciide_irqack; 433 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 434 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 435 } 436 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 437 438 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 439 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 440 441 wdc_allocate_regs(&sc->sc_wdcdev); 442 443 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 444 channel++) { 445 cp = &sc->pciide_channels[channel]; 446 if (pciide_chansetup(sc, channel, interface) == 0) 447 continue; 448 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 449 pciide_pci_intr); 450 } 451 } 452
Indexes created Tue Sep 23 23:09:58 GMT 2025