artsata.c revision 1.19.2.1
1 /* $NetBSD: artsata.c,v 1.19.2.1 2010/11/06 08:08:30 uebayasi Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: artsata.c,v 1.19.2.1 2010/11/06 08:08:30 uebayasi Exp $"); 34 35 #include "opt_pciide.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcidevs.h> 43 #include <dev/pci/pciidereg.h> 44 #include <dev/pci/pciidevar.h> 45 #include <dev/pci/pciide_i31244_reg.h> 46 47 #include <dev/ata/satareg.h> 48 #include <dev/ata/satavar.h> 49 #include <dev/ata/atareg.h> 50 #include <dev/ata/atavar.h> 51 52 static void artisea_chip_map(struct pciide_softc*, struct pci_attach_args *); 53 54 static int artsata_match(device_t, cfdata_t, void *); 55 static void artsata_attach(device_t, device_t, void *); 56 57 static const struct pciide_product_desc pciide_artsata_products[] = { 58 { PCI_PRODUCT_INTEL_31244, 59 0, 60 "Intel 31244 Serial ATA Controller", 61 artisea_chip_map, 62 }, 63 { 0, 64 0, 65 NULL, 66 NULL 67 } 68 }; 69 70 struct artisea_cmd_map 71 { 72 u_int8_t offset; 73 u_int8_t size; 74 }; 75 76 static const struct artisea_cmd_map artisea_dpa_cmd_map[] = 77 { 78 {ARTISEA_SUPDDR, 4}, /* 0 Data */ 79 {ARTISEA_SUPDER, 1}, /* 1 Error */ 80 {ARTISEA_SUPDCSR, 2}, /* 2 Sector Count */ 81 {ARTISEA_SUPDSNR, 2}, /* 3 Sector Number */ 82 {ARTISEA_SUPDCLR, 2}, /* 4 Cylinder Low */ 83 {ARTISEA_SUPDCHR, 2}, /* 5 Cylinder High */ 84 {ARTISEA_SUPDDHR, 1}, /* 6 Device/Head */ 85 {ARTISEA_SUPDCR, 1}, /* 7 Command */ 86 {ARTISEA_SUPDSR, 1}, /* 8 Status */ 87 {ARTISEA_SUPDFR, 2} /* 9 Feature */ 88 }; 89 90 #define ARTISEA_NUM_CHAN 4 91 92 CFATTACH_DECL_NEW(artsata, sizeof(struct pciide_softc), 93 artsata_match, artsata_attach, NULL, NULL); 94 95 static int 96 artsata_match(device_t parent, cfdata_t match, void *aux) 97 { 98 struct pci_attach_args *pa = aux; 99 100 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 101 if (pciide_lookup_product(pa->pa_id, pciide_artsata_products)) 102 return (2); 103 } 104 return (0); 105 } 106 107 static void 108 artsata_attach(device_t parent, device_t self, void *aux) 109 { 110 struct pci_attach_args *pa = aux; 111 struct pciide_softc *sc = device_private(self); 112 113 sc->sc_wdcdev.sc_atac.atac_dev = self; 114 115 pciide_common_attach(sc, pa, 116 pciide_lookup_product(pa->pa_id, pciide_artsata_products)); 117 118 } 119 120 static void 121 artisea_mapregs(struct pci_attach_args *pa, struct pciide_channel *cp, 122 int (*pci_intr)(void *)) 123 { 124 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 125 struct ata_channel *wdc_cp = &cp->ata_channel; 126 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 127 const char *intrstr; 128 pci_intr_handle_t intrhandle; 129 int i; 130 131 cp->compat = 0; 132 133 if (sc->sc_pci_ih == NULL) { 134 if (pci_intr_map(pa, &intrhandle) != 0) { 135 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 136 "couldn't map native-PCI interrupt\n"); 137 goto bad; 138 } 139 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 140 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 141 intrhandle, IPL_BIO, pci_intr, sc); 142 if (sc->sc_pci_ih != NULL) { 143 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 144 "using %s for native-PCI interrupt\n", 145 intrstr ? intrstr : "unknown interrupt"); 146 } else { 147 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 148 "couldn't establish native-PCI interrupt"); 149 if (intrstr != NULL) 150 aprint_error(" at %s", intrstr); 151 aprint_error("\n"); 152 goto bad; 153 } 154 } 155 cp->ih = sc->sc_pci_ih; 156 wdr->cmd_iot = sc->sc_ba5_st; 157 if (bus_space_subregion (sc->sc_ba5_st, sc->sc_ba5_sh, 158 ARTISEA_DPA_PORT_BASE(wdc_cp->ch_channel), 0x200, 159 &wdr->cmd_baseioh) != 0) { 160 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 161 "couldn't map %s channel cmd regs\n", cp->name); 162 goto bad; 163 } 164 165 wdr->ctl_iot = sc->sc_ba5_st; 166 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 167 ARTISEA_SUPDDCTLR, 1, &cp->ctl_baseioh) != 0) { 168 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 169 "couldn't map %s channel ctl regs\n", cp->name); 170 goto bad; 171 } 172 wdr->ctl_ioh = cp->ctl_baseioh; 173 174 for (i = 0; i < WDC_NREG + 2; i++) { 175 176 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 177 artisea_dpa_cmd_map[i].offset, artisea_dpa_cmd_map[i].size, 178 &wdr->cmd_iohs[i]) != 0) { 179 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 180 "couldn't subregion %s channel cmd regs\n", 181 cp->name); 182 goto bad; 183 } 184 } 185 wdr->data32iot = wdr->cmd_iot; 186 wdr->data32ioh = wdr->cmd_iohs[0]; 187 188 wdr->sata_iot = wdr->cmd_iot; 189 wdr->sata_baseioh = wdr->cmd_baseioh; 190 191 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 192 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSSR, 1, 193 &wdr->sata_status) != 0) { 194 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 195 "couldn't map channel %d sata_status regs\n", 196 wdc_cp->ch_channel); 197 goto bad; 198 } 199 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 200 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSER, 1, 201 &wdr->sata_error) != 0) { 202 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 203 "couldn't map channel %d sata_error regs\n", 204 wdc_cp->ch_channel); 205 goto bad; 206 } 207 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 208 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, 1, 209 &wdr->sata_control) != 0) { 210 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 211 "couldn't map channel %d sata_control regs\n", 212 wdc_cp->ch_channel); 213 goto bad; 214 } 215 216 wdcattach(wdc_cp); 217 return; 218 219 bad: 220 wdc_cp->ch_flags |= ATACH_DISABLED; 221 return; 222 } 223 224 static int 225 artisea_chansetup(struct pciide_softc *sc, int channel, 226 pcireg_t interface) 227 { 228 struct pciide_channel *cp = &sc->pciide_channels[channel]; 229 sc->wdc_chanarray[channel] = &cp->ata_channel; 230 cp->name = PCIIDE_CHANNEL_NAME(channel); 231 cp->ata_channel.ch_channel = channel; 232 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 233 cp->ata_channel.ch_queue = 234 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 235 cp->ata_channel.ch_ndrive = 2; 236 if (cp->ata_channel.ch_queue == NULL) { 237 aprint_error("%s %s channel: " 238 "can't allocate memory for command queue", 239 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 240 return 0; 241 } 242 return 1; 243 } 244 245 static void 246 artisea_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 247 { 248 struct pciide_channel *pc; 249 int chan; 250 u_int32_t dma_ctl; 251 u_int32_t cacheline_len; 252 253 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 254 "bus-master DMA support present"); 255 256 sc->sc_dma_ok = 1; 257 258 /* 259 * Errata #4 says that if the cacheline length is not set correctly, 260 * we can get corrupt MWI and Memory-Block-Write transactions. 261 */ 262 cacheline_len = PCI_CACHELINE(pci_conf_read (pa->pa_pc, pa->pa_tag, 263 PCI_BHLC_REG)); 264 if (cacheline_len == 0) { 265 aprint_verbose(", but unused (cacheline size not set in PCI conf)\n"); 266 sc->sc_dma_ok = 0; 267 return; 268 } 269 270 /* 271 * Final step of the work-around is to force the DMA engine to use 272 * the cache-line length information. 273 */ 274 dma_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR); 275 dma_ctl |= SUDCSCR_DMA_WCAE | SUDCSCR_DMA_RCAE; 276 pci_conf_write(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR, dma_ctl); 277 278 sc->sc_wdcdev.dma_arg = sc; 279 sc->sc_wdcdev.dma_init = pciide_dma_init; 280 sc->sc_wdcdev.dma_start = pciide_dma_start; 281 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 282 sc->sc_dma_iot = sc->sc_ba5_st; 283 sc->sc_dmat = pa->pa_dmat; 284 285 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 286 PCIIDE_OPTIONS_NODMA) { 287 aprint_verbose( 288 ", but unused (forced off by config file)\n"); 289 sc->sc_dma_ok = 0; 290 return; 291 } 292 293 /* 294 * Set up the default handles for the DMA registers. 295 * Just reserve 32 bits for each handle, unless space 296 * doesn't permit it. 297 */ 298 for (chan = 0; chan < ARTISEA_NUM_CHAN; chan++) { 299 pc = &sc->pciide_channels[chan]; 300 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 301 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDCMDR, 2, 302 &pc->dma_iohs[IDEDMA_CMD]) != 0 || 303 bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 304 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDSR, 1, 305 &pc->dma_iohs[IDEDMA_CTL]) != 0 || 306 bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 307 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDDTPR, 4, 308 &pc->dma_iohs[IDEDMA_TBL]) != 0) { 309 sc->sc_dma_ok = 0; 310 aprint_verbose(", but can't subregion registers\n"); 311 return; 312 } 313 } 314 315 aprint_verbose("\n"); 316 } 317 318 static void 319 artisea_chip_map_dpa(struct pciide_softc *sc, struct pci_attach_args *pa) 320 { 321 struct pciide_channel *cp; 322 pcireg_t interface; 323 int channel; 324 325 interface = PCI_INTERFACE(pa->pa_class); 326 327 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 328 "interface wired in DPA mode\n"); 329 330 if (pci_mapreg_map(pa, ARTISEA_PCI_DPA_BASE, PCI_MAPREG_MEM_TYPE_64BIT, 331 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) 332 return; 333 334 artisea_mapreg_dma(sc, pa); 335 336 sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS; 337 338 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 339 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 340 if (sc->sc_dma_ok) { 341 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 342 sc->sc_wdcdev.irqack = pciide_irqack; 343 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 344 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 345 } 346 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 347 348 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 349 sc->sc_wdcdev.sc_atac.atac_nchannels = ARTISEA_NUM_CHAN; 350 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 351 352 wdc_allocate_regs(&sc->sc_wdcdev); 353 354 /* 355 * Perform a quick check to ensure that the device isn't configured 356 * in Spread-spectrum clocking mode. This feature is buggy and has 357 * been removed from the latest documentation. 358 * 359 * Note that although this bit is in the Channel regs, it's the same 360 * for all channels, so we check it just once here. 361 */ 362 if ((bus_space_read_4 (sc->sc_ba5_st, sc->sc_ba5_sh, 363 ARTISEA_DPA_PORT_BASE(0) + ARTISEA_SUPERSET_DPA_OFF + 364 ARTISEA_SUPDPFR) & SUPDPFR_SSCEN) != 0) { 365 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 366 "Spread-specturm clocking not supported by device\n"); 367 return; 368 } 369 370 /* Clear the LED0-only bit. */ 371 pci_conf_write (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0, 372 pci_conf_read (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0) & 373 ~SUECSR0_LED0_ONLY); 374 375 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 376 channel++) { 377 cp = &sc->pciide_channels[channel]; 378 if (artisea_chansetup(sc, channel, interface) == 0) 379 continue; 380 /* XXX We can probably do interrupts more efficiently. */ 381 artisea_mapregs(pa, cp, pciide_pci_intr); 382 } 383 } 384 385 static void 386 artisea_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 387 { 388 struct pciide_channel *cp; 389 pcireg_t interface; 390 int channel; 391 392 if (pciide_chipen(sc, pa) == 0) 393 return; 394 395 interface = PCI_INTERFACE(pa->pa_class); 396 397 if (interface == 0) { 398 artisea_chip_map_dpa (sc, pa); 399 return; 400 } 401 402 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 403 "bus-master DMA support present"); 404 #ifdef PCIIDE_I31244_DISABLEDMA 405 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 && 406 PCI_REVISION(pa->pa_class) == 0) { 407 aprint_verbose(" but disabled due to rev. 0"); 408 sc->sc_dma_ok = 0; 409 } else 410 #endif 411 pciide_mapreg_dma(sc, pa); 412 aprint_verbose("\n"); 413 414 /* 415 * XXX Configure LEDs to show activity. 416 */ 417 418 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 419 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 420 if (sc->sc_dma_ok) { 421 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 422 sc->sc_wdcdev.irqack = pciide_irqack; 423 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 424 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 425 } 426 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 427 428 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 429 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 430 431 wdc_allocate_regs(&sc->sc_wdcdev); 432 433 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 434 channel++) { 435 cp = &sc->pciide_channels[channel]; 436 if (pciide_chansetup(sc, channel, interface) == 0) 437 continue; 438 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 439 } 440 } 441
Indexes created Sat Oct 18 23:09:54 GMT 2025