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artsata.c revision 1.24 
      1 /*	$NetBSD: artsata.c,v 1.24 2012/07/31 15:50:36 bouyer Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2003 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Jason R. Thorpe of Wasabi Systems, Inc.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <sys/cdefs.h>
     33 __KERNEL_RCSID(0, "$NetBSD: artsata.c,v 1.24 2012/07/31 15:50:36 bouyer Exp $");
     34 
     35 #include "opt_pciide.h"
     36 
     37 #include <sys/param.h>
     38 #include <sys/systm.h>
     39 #include <sys/malloc.h>
     40 
     41 #include <dev/pci/pcivar.h>
     42 #include <dev/pci/pcidevs.h>
     43 #include <dev/pci/pciidereg.h>
     44 #include <dev/pci/pciidevar.h>
     45 #include <dev/pci/pciide_i31244_reg.h>
     46 
     47 #include <dev/ata/satareg.h>
     48 #include <dev/ata/satavar.h>
     49 #include <dev/ata/atareg.h>
     50 #include <dev/ata/atavar.h>
     51 
     52 static void artisea_chip_map(struct pciide_softc*,
     53     const struct pci_attach_args *);
     54 
     55 static int  artsata_match(device_t, cfdata_t, void *);
     56 static void artsata_attach(device_t, device_t, void *);
     57 
     58 static const struct pciide_product_desc pciide_artsata_products[] =  {
     59 	{ PCI_PRODUCT_INTEL_31244,
     60 	  0,
     61 	  "Intel 31244 Serial ATA Controller",
     62 	  artisea_chip_map,
     63 	},
     64 	{ 0,
     65 	  0,
     66 	  NULL,
     67 	  NULL
     68 	}
     69 };
     70 
     71 struct artisea_cmd_map
     72 {
     73 	u_int8_t offset;
     74 	u_int8_t size;
     75 };
     76 
     77 static const struct artisea_cmd_map artisea_dpa_cmd_map[] =
     78 {
     79 	{ARTISEA_SUPDDR, 4},	/* 0 Data */
     80 	{ARTISEA_SUPDER, 1},	/* 1 Error */
     81 	{ARTISEA_SUPDCSR, 2},	/* 2 Sector Count */
     82 	{ARTISEA_SUPDSNR, 2},	/* 3 Sector Number */
     83 	{ARTISEA_SUPDCLR, 2},	/* 4 Cylinder Low */
     84 	{ARTISEA_SUPDCHR, 2},	/* 5 Cylinder High */
     85 	{ARTISEA_SUPDDHR, 1},	/* 6 Device/Head */
     86 	{ARTISEA_SUPDCR, 1},	/* 7 Command */
     87 	{ARTISEA_SUPDSR, 1},	/* 8 Status */
     88 	{ARTISEA_SUPDFR, 2}	/* 9 Feature */
     89 };
     90 
     91 #define ARTISEA_NUM_CHAN 4
     92 
     93 CFATTACH_DECL_NEW(artsata, sizeof(struct pciide_softc),
     94     artsata_match, artsata_attach, NULL, NULL);
     95 
     96 static int
     97 artsata_match(device_t parent, cfdata_t match, void *aux)
     98 {
     99 	struct pci_attach_args *pa = aux;
    100 
    101 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) {
    102 		if (pciide_lookup_product(pa->pa_id, pciide_artsata_products))
    103 			return (2);
    104 	}
    105 	return (0);
    106 }
    107 
    108 static void
    109 artsata_attach(device_t parent, device_t self, void *aux)
    110 {
    111 	struct pci_attach_args *pa = aux;
    112 	struct pciide_softc *sc = device_private(self);
    113 
    114 	sc->sc_wdcdev.sc_atac.atac_dev = self;
    115 
    116 	pciide_common_attach(sc, pa,
    117 	    pciide_lookup_product(pa->pa_id, pciide_artsata_products));
    118 
    119 }
    120 
    121 static void
    122 artisea_mapregs(const struct pci_attach_args *pa, struct pciide_channel *cp,
    123     int (*pci_intr)(void *))
    124 {
    125 	struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
    126 	struct ata_channel *wdc_cp = &cp->ata_channel;
    127 	struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp);
    128 	const char *intrstr;
    129 	pci_intr_handle_t intrhandle;
    130 	int i;
    131 
    132 	cp->compat = 0;
    133 
    134 	if (sc->sc_pci_ih == NULL) {
    135 		if (pci_intr_map(pa, &intrhandle) != 0) {
    136 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    137 			    "couldn't map native-PCI interrupt\n");
    138 			goto bad;
    139 		}
    140 		intrstr = pci_intr_string(pa->pa_pc, intrhandle);
    141 		sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
    142 		    intrhandle, IPL_BIO, pci_intr, sc);
    143 		if (sc->sc_pci_ih != NULL) {
    144 			aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    145 			    "using %s for native-PCI interrupt\n",
    146 			    intrstr ? intrstr : "unknown interrupt");
    147 		} else {
    148 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    149 			    "couldn't establish native-PCI interrupt");
    150 			if (intrstr != NULL)
    151 				aprint_error(" at %s", intrstr);
    152 			aprint_error("\n");
    153 			goto bad;
    154 		}
    155 	}
    156 	cp->ih = sc->sc_pci_ih;
    157 	wdr->cmd_iot = sc->sc_ba5_st;
    158 	if (bus_space_subregion (sc->sc_ba5_st, sc->sc_ba5_sh,
    159 	    ARTISEA_DPA_PORT_BASE(wdc_cp->ch_channel), 0x200,
    160 	    &wdr->cmd_baseioh) != 0) {
    161 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    162 		    "couldn't map %s channel cmd regs\n", cp->name);
    163 		goto bad;
    164 	}
    165 
    166 	wdr->ctl_iot = sc->sc_ba5_st;
    167 	if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
    168 	    ARTISEA_SUPDDCTLR, 1, &cp->ctl_baseioh) != 0) {
    169 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    170 		    "couldn't map %s channel ctl regs\n", cp->name);
    171 		goto bad;
    172 	}
    173 	wdr->ctl_ioh = cp->ctl_baseioh;
    174 
    175 	for (i = 0; i < WDC_NREG + 2; i++) {
    176 
    177 		if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
    178 		    artisea_dpa_cmd_map[i].offset, artisea_dpa_cmd_map[i].size,
    179 		    &wdr->cmd_iohs[i]) != 0) {
    180 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    181 			    "couldn't subregion %s channel cmd regs\n",
    182 			    cp->name);
    183 			goto bad;
    184 		}
    185 	}
    186 	wdr->data32iot = wdr->cmd_iot;
    187 	wdr->data32ioh = wdr->cmd_iohs[0];
    188 
    189 	wdr->sata_iot = wdr->cmd_iot;
    190 	wdr->sata_baseioh = wdr->cmd_baseioh;
    191 
    192 	if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    193 	    ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSSR, 1,
    194 	    &wdr->sata_status) != 0) {
    195 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    196 		    "couldn't map channel %d sata_status regs\n",
    197 		    wdc_cp->ch_channel);
    198 		goto bad;
    199 	}
    200 	if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    201 	    ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSER, 1,
    202 	    &wdr->sata_error) != 0) {
    203 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    204 		    "couldn't map channel %d sata_error regs\n",
    205 		    wdc_cp->ch_channel);
    206 		goto bad;
    207 	}
    208 	if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    209 	    ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, 1,
    210 	    &wdr->sata_control) != 0) {
    211 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    212 		    "couldn't map channel %d sata_control regs\n",
    213 		    wdc_cp->ch_channel);
    214 		goto bad;
    215 	}
    216 
    217 	wdcattach(wdc_cp);
    218 	return;
    219 
    220 bad:
    221 	wdc_cp->ch_flags |= ATACH_DISABLED;
    222 	return;
    223 }
    224 
    225 static int
    226 artisea_chansetup(struct pciide_softc *sc, int channel,
    227     pcireg_t interface)
    228 {
    229 	struct pciide_channel *cp = &sc->pciide_channels[channel];
    230 	sc->wdc_chanarray[channel] = &cp->ata_channel;
    231 	cp->name = PCIIDE_CHANNEL_NAME(channel);
    232 	cp->ata_channel.ch_channel = channel;
    233 	cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
    234 	cp->ata_channel.ch_queue =
    235 	    malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT);
    236 	if (cp->ata_channel.ch_queue == NULL) {
    237 		aprint_error("%s %s channel: "
    238 		    "can't allocate memory for command queue",
    239 		device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name);
    240 		return 0;
    241 	}
    242 	return 1;
    243 }
    244 
    245 static void
    246 artisea_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa)
    247 {
    248 	struct pciide_channel *pc;
    249 	int chan;
    250 	u_int32_t dma_ctl;
    251 	u_int32_t cacheline_len;
    252 
    253 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    254 	    "bus-master DMA support present");
    255 
    256 	sc->sc_dma_ok = 1;
    257 
    258 	/*
    259 	 * Errata #4 says that if the cacheline length is not set correctly,
    260 	 * we can get corrupt MWI and Memory-Block-Write transactions.
    261 	 */
    262 	cacheline_len = PCI_CACHELINE(pci_conf_read (pa->pa_pc, pa->pa_tag,
    263 	    PCI_BHLC_REG));
    264 	if (cacheline_len == 0) {
    265 		aprint_verbose(", but unused (cacheline size not set in PCI conf)\n");
    266 		sc->sc_dma_ok = 0;
    267 		return;
    268 	}
    269 
    270 	/*
    271 	 * Final step of the work-around is to force the DMA engine to use
    272 	 * the cache-line length information.
    273 	 */
    274 	dma_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR);
    275 	dma_ctl |= SUDCSCR_DMA_WCAE | SUDCSCR_DMA_RCAE;
    276 	pci_conf_write(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR, dma_ctl);
    277 
    278 	sc->sc_wdcdev.dma_arg = sc;
    279 	sc->sc_wdcdev.dma_init = pciide_dma_init;
    280 	sc->sc_wdcdev.dma_start = pciide_dma_start;
    281 	sc->sc_wdcdev.dma_finish = pciide_dma_finish;
    282 	sc->sc_dma_iot = sc->sc_ba5_st;
    283 	sc->sc_dmat = pa->pa_dmat;
    284 
    285 	if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
    286 	    PCIIDE_OPTIONS_NODMA) {
    287 		aprint_verbose(
    288 		    ", but unused (forced off by config file)\n");
    289 		sc->sc_dma_ok = 0;
    290 		return;
    291 	}
    292 
    293 	/*
    294 	 * Set up the default handles for the DMA registers.
    295 	 * Just reserve 32 bits for each handle, unless space
    296 	 * doesn't permit it.
    297 	 */
    298 	for (chan = 0; chan < ARTISEA_NUM_CHAN; chan++) {
    299 		pc = &sc->pciide_channels[chan];
    300 		if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
    301 		    ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDCMDR, 2,
    302 		    &pc->dma_iohs[IDEDMA_CMD]) != 0 ||
    303 		    bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
    304 		    ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDSR, 1,
    305 		    &pc->dma_iohs[IDEDMA_CTL]) != 0 ||
    306 		    bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
    307 		    ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDDTPR, 4,
    308 		    &pc->dma_iohs[IDEDMA_TBL]) != 0) {
    309 			sc->sc_dma_ok = 0;
    310 			aprint_verbose(", but can't subregion registers\n");
    311 			return;
    312 		}
    313 	}
    314 
    315 	aprint_verbose("\n");
    316 }
    317 
    318 static void
    319 artisea_chip_map_dpa(struct pciide_softc *sc, const struct pci_attach_args *pa)
    320 {
    321 	struct pciide_channel *cp;
    322 	pcireg_t interface;
    323 	int channel;
    324 
    325 	interface = PCI_INTERFACE(pa->pa_class);
    326 
    327 	aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    328 	    "interface wired in DPA mode\n");
    329 
    330 	if (pci_mapreg_map(pa, ARTISEA_PCI_DPA_BASE, PCI_MAPREG_MEM_TYPE_64BIT,
    331 	    0, &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0)
    332 		return;
    333 
    334 	artisea_mapreg_dma(sc, pa);
    335 
    336 	sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS;
    337 
    338 	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
    339 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
    340 	if (sc->sc_dma_ok) {
    341 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
    342 		sc->sc_wdcdev.irqack = pciide_irqack;
    343 		sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
    344 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    345 	}
    346 	sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
    347 
    348 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
    349 	sc->sc_wdcdev.sc_atac.atac_nchannels = ARTISEA_NUM_CHAN;
    350 	sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
    351 	sc->sc_wdcdev.wdc_maxdrives = 1;
    352 
    353 	wdc_allocate_regs(&sc->sc_wdcdev);
    354 
    355 	/*
    356 	 * Perform a quick check to ensure that the device isn't configured
    357 	 * in Spread-spectrum clocking mode.  This feature is buggy and has
    358 	 * been removed from the latest documentation.
    359 	 *
    360 	 * Note that although this bit is in the Channel regs, it's the same
    361 	 * for all channels, so we check it just once here.
    362 	 */
    363 	if ((bus_space_read_4 (sc->sc_ba5_st, sc->sc_ba5_sh,
    364 	    ARTISEA_DPA_PORT_BASE(0) + ARTISEA_SUPERSET_DPA_OFF +
    365 	    ARTISEA_SUPDPFR) & SUPDPFR_SSCEN) != 0) {
    366 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    367 		    "Spread-specturm clocking not supported by device\n");
    368 		return;
    369 	}
    370 
    371 	/* Clear the LED0-only bit.  */
    372 	pci_conf_write (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0,
    373 	    pci_conf_read (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0) &
    374 	    ~SUECSR0_LED0_ONLY);
    375 
    376 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
    377 	     channel++) {
    378 		cp = &sc->pciide_channels[channel];
    379 		if (artisea_chansetup(sc, channel, interface) == 0)
    380 			continue;
    381 		/* XXX We can probably do interrupts more efficiently.  */
    382 		artisea_mapregs(pa, cp, pciide_pci_intr);
    383 	}
    384 }
    385 
    386 static void
    387 artisea_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
    388 {
    389 	struct pciide_channel *cp;
    390 	pcireg_t interface;
    391 	int channel;
    392 
    393 	if (pciide_chipen(sc, pa) == 0)
    394 		return;
    395 
    396 	interface = PCI_INTERFACE(pa->pa_class);
    397 
    398 	if (interface == 0) {
    399 		artisea_chip_map_dpa (sc, pa);
    400 		return;
    401 	}
    402 
    403 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    404 	    "bus-master DMA support present");
    405 #ifdef PCIIDE_I31244_DISABLEDMA
    406 	if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 &&
    407 	    PCI_REVISION(pa->pa_class) == 0) {
    408 		aprint_verbose(" but disabled due to rev. 0");
    409 		sc->sc_dma_ok = 0;
    410 	} else
    411 #endif
    412 		pciide_mapreg_dma(sc, pa);
    413 	aprint_verbose("\n");
    414 
    415 	/*
    416 	 * XXX Configure LEDs to show activity.
    417 	 */
    418 
    419 	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
    420 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
    421 	if (sc->sc_dma_ok) {
    422 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
    423 		sc->sc_wdcdev.irqack = pciide_irqack;
    424 		sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
    425 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    426 	}
    427 	sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
    428 
    429 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
    430 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
    431 
    432 	wdc_allocate_regs(&sc->sc_wdcdev);
    433 
    434 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
    435 	     channel++) {
    436 		cp = &sc->pciide_channels[channel];
    437 		if (pciide_chansetup(sc, channel, interface) == 0)
    438 			continue;
    439 		pciide_mapchan(pa, cp, interface, pciide_pci_intr);
    440 	}
    441 }
    442