artsata.c revision 1.24.2.1
1 /* $NetBSD: artsata.c,v 1.24.2.1 2012/10/09 13:36:05 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: artsata.c,v 1.24.2.1 2012/10/09 13:36:05 bouyer Exp $"); 34 35 #include "opt_pciide.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcidevs.h> 43 #include <dev/pci/pciidereg.h> 44 #include <dev/pci/pciidevar.h> 45 #include <dev/pci/pciide_i31244_reg.h> 46 47 #include <dev/ata/satareg.h> 48 #include <dev/ata/satavar.h> 49 #include <dev/ata/atareg.h> 50 #include <dev/ata/atavar.h> 51 52 static void artisea_chip_map(struct pciide_softc*, 53 const struct pci_attach_args *); 54 55 static int artsata_match(device_t, cfdata_t, void *); 56 static void artsata_attach(device_t, device_t, void *); 57 58 static const struct pciide_product_desc pciide_artsata_products[] = { 59 { PCI_PRODUCT_INTEL_31244, 60 0, 61 "Intel 31244 Serial ATA Controller", 62 artisea_chip_map, 63 }, 64 { 0, 65 0, 66 NULL, 67 NULL 68 } 69 }; 70 71 struct artisea_cmd_map 72 { 73 u_int8_t offset; 74 u_int8_t size; 75 }; 76 77 static const struct artisea_cmd_map artisea_dpa_cmd_map[] = 78 { 79 {ARTISEA_SUPDDR, 4}, /* 0 Data */ 80 {ARTISEA_SUPDER, 1}, /* 1 Error */ 81 {ARTISEA_SUPDCSR, 2}, /* 2 Sector Count */ 82 {ARTISEA_SUPDSNR, 2}, /* 3 Sector Number */ 83 {ARTISEA_SUPDCLR, 2}, /* 4 Cylinder Low */ 84 {ARTISEA_SUPDCHR, 2}, /* 5 Cylinder High */ 85 {ARTISEA_SUPDDHR, 1}, /* 6 Device/Head */ 86 {ARTISEA_SUPDCR, 1}, /* 7 Command */ 87 {ARTISEA_SUPDSR, 1}, /* 8 Status */ 88 {ARTISEA_SUPDFR, 2} /* 9 Feature */ 89 }; 90 91 #define ARTISEA_NUM_CHAN 4 92 93 CFATTACH_DECL_NEW(artsata, sizeof(struct pciide_softc), 94 artsata_match, artsata_attach, NULL, NULL); 95 96 static int 97 artsata_match(device_t parent, cfdata_t match, void *aux) 98 { 99 struct pci_attach_args *pa = aux; 100 101 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 102 if (pciide_lookup_product(pa->pa_id, pciide_artsata_products)) 103 return (2); 104 } 105 return (0); 106 } 107 108 static void 109 artsata_attach(device_t parent, device_t self, void *aux) 110 { 111 struct pci_attach_args *pa = aux; 112 struct pciide_softc *sc = device_private(self); 113 114 self->dv_maxphys = MIN(parent->dv_maxphys, MACHINE_MAXPHYS); 115 116 sc->sc_wdcdev.sc_atac.atac_dev = self; 117 118 pciide_common_attach(sc, pa, 119 pciide_lookup_product(pa->pa_id, pciide_artsata_products)); 120 121 } 122 123 static void 124 artisea_mapregs(const struct pci_attach_args *pa, struct pciide_channel *cp, 125 int (*pci_intr)(void *)) 126 { 127 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 128 struct ata_channel *wdc_cp = &cp->ata_channel; 129 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 130 const char *intrstr; 131 pci_intr_handle_t intrhandle; 132 int i; 133 134 cp->compat = 0; 135 136 if (sc->sc_pci_ih == NULL) { 137 if (pci_intr_map(pa, &intrhandle) != 0) { 138 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 139 "couldn't map native-PCI interrupt\n"); 140 goto bad; 141 } 142 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 143 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 144 intrhandle, IPL_BIO, pci_intr, sc); 145 if (sc->sc_pci_ih != NULL) { 146 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 147 "using %s for native-PCI interrupt\n", 148 intrstr ? intrstr : "unknown interrupt"); 149 } else { 150 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 151 "couldn't establish native-PCI interrupt"); 152 if (intrstr != NULL) 153 aprint_error(" at %s", intrstr); 154 aprint_error("\n"); 155 goto bad; 156 } 157 } 158 cp->ih = sc->sc_pci_ih; 159 wdr->cmd_iot = sc->sc_ba5_st; 160 if (bus_space_subregion (sc->sc_ba5_st, sc->sc_ba5_sh, 161 ARTISEA_DPA_PORT_BASE(wdc_cp->ch_channel), 0x200, 162 &wdr->cmd_baseioh) != 0) { 163 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 164 "couldn't map %s channel cmd regs\n", cp->name); 165 goto bad; 166 } 167 168 wdr->ctl_iot = sc->sc_ba5_st; 169 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 170 ARTISEA_SUPDDCTLR, 1, &cp->ctl_baseioh) != 0) { 171 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 172 "couldn't map %s channel ctl regs\n", cp->name); 173 goto bad; 174 } 175 wdr->ctl_ioh = cp->ctl_baseioh; 176 177 for (i = 0; i < WDC_NREG + 2; i++) { 178 179 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 180 artisea_dpa_cmd_map[i].offset, artisea_dpa_cmd_map[i].size, 181 &wdr->cmd_iohs[i]) != 0) { 182 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 183 "couldn't subregion %s channel cmd regs\n", 184 cp->name); 185 goto bad; 186 } 187 } 188 wdr->data32iot = wdr->cmd_iot; 189 wdr->data32ioh = wdr->cmd_iohs[0]; 190 191 wdr->sata_iot = wdr->cmd_iot; 192 wdr->sata_baseioh = wdr->cmd_baseioh; 193 194 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 195 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSSR, 1, 196 &wdr->sata_status) != 0) { 197 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 198 "couldn't map channel %d sata_status regs\n", 199 wdc_cp->ch_channel); 200 goto bad; 201 } 202 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 203 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSER, 1, 204 &wdr->sata_error) != 0) { 205 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 206 "couldn't map channel %d sata_error regs\n", 207 wdc_cp->ch_channel); 208 goto bad; 209 } 210 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 211 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, 1, 212 &wdr->sata_control) != 0) { 213 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 214 "couldn't map channel %d sata_control regs\n", 215 wdc_cp->ch_channel); 216 goto bad; 217 } 218 219 wdcattach(wdc_cp); 220 return; 221 222 bad: 223 wdc_cp->ch_flags |= ATACH_DISABLED; 224 return; 225 } 226 227 static int 228 artisea_chansetup(struct pciide_softc *sc, int channel, 229 pcireg_t interface) 230 { 231 struct pciide_channel *cp = &sc->pciide_channels[channel]; 232 sc->wdc_chanarray[channel] = &cp->ata_channel; 233 cp->name = PCIIDE_CHANNEL_NAME(channel); 234 cp->ata_channel.ch_channel = channel; 235 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 236 cp->ata_channel.ch_queue = 237 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 238 if (cp->ata_channel.ch_queue == NULL) { 239 aprint_error("%s %s channel: " 240 "can't allocate memory for command queue", 241 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 242 return 0; 243 } 244 return 1; 245 } 246 247 static void 248 artisea_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 249 { 250 struct pciide_channel *pc; 251 int chan; 252 u_int32_t dma_ctl; 253 u_int32_t cacheline_len; 254 255 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 256 "bus-master DMA support present"); 257 258 sc->sc_dma_ok = 1; 259 260 /* 261 * Errata #4 says that if the cacheline length is not set correctly, 262 * we can get corrupt MWI and Memory-Block-Write transactions. 263 */ 264 cacheline_len = PCI_CACHELINE(pci_conf_read (pa->pa_pc, pa->pa_tag, 265 PCI_BHLC_REG)); 266 if (cacheline_len == 0) { 267 aprint_verbose(", but unused (cacheline size not set in PCI conf)\n"); 268 sc->sc_dma_ok = 0; 269 return; 270 } 271 272 /* 273 * Final step of the work-around is to force the DMA engine to use 274 * the cache-line length information. 275 */ 276 dma_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR); 277 dma_ctl |= SUDCSCR_DMA_WCAE | SUDCSCR_DMA_RCAE; 278 pci_conf_write(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR, dma_ctl); 279 280 sc->sc_wdcdev.dma_arg = sc; 281 sc->sc_wdcdev.dma_init = pciide_dma_init; 282 sc->sc_wdcdev.dma_start = pciide_dma_start; 283 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 284 sc->sc_dma_iot = sc->sc_ba5_st; 285 sc->sc_dmat = pa->pa_dmat; 286 287 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 288 PCIIDE_OPTIONS_NODMA) { 289 aprint_verbose( 290 ", but unused (forced off by config file)\n"); 291 sc->sc_dma_ok = 0; 292 return; 293 } 294 295 /* 296 * Set up the default handles for the DMA registers. 297 * Just reserve 32 bits for each handle, unless space 298 * doesn't permit it. 299 */ 300 for (chan = 0; chan < ARTISEA_NUM_CHAN; chan++) { 301 pc = &sc->pciide_channels[chan]; 302 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 303 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDCMDR, 2, 304 &pc->dma_iohs[IDEDMA_CMD]) != 0 || 305 bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 306 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDSR, 1, 307 &pc->dma_iohs[IDEDMA_CTL]) != 0 || 308 bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 309 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDDTPR, 4, 310 &pc->dma_iohs[IDEDMA_TBL]) != 0) { 311 sc->sc_dma_ok = 0; 312 aprint_verbose(", but can't subregion registers\n"); 313 return; 314 } 315 } 316 317 aprint_verbose("\n"); 318 } 319 320 static void 321 artisea_chip_map_dpa(struct pciide_softc *sc, const struct pci_attach_args *pa) 322 { 323 struct pciide_channel *cp; 324 pcireg_t interface; 325 int channel; 326 327 interface = PCI_INTERFACE(pa->pa_class); 328 329 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 330 "interface wired in DPA mode\n"); 331 332 if (pci_mapreg_map(pa, ARTISEA_PCI_DPA_BASE, PCI_MAPREG_MEM_TYPE_64BIT, 333 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) 334 return; 335 336 artisea_mapreg_dma(sc, pa); 337 338 sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS; 339 340 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 341 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 342 if (sc->sc_dma_ok) { 343 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 344 sc->sc_wdcdev.irqack = pciide_irqack; 345 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 346 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 347 } 348 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 349 350 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 351 sc->sc_wdcdev.sc_atac.atac_nchannels = ARTISEA_NUM_CHAN; 352 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 353 sc->sc_wdcdev.wdc_maxdrives = 1; 354 355 wdc_allocate_regs(&sc->sc_wdcdev); 356 357 /* 358 * Perform a quick check to ensure that the device isn't configured 359 * in Spread-spectrum clocking mode. This feature is buggy and has 360 * been removed from the latest documentation. 361 * 362 * Note that although this bit is in the Channel regs, it's the same 363 * for all channels, so we check it just once here. 364 */ 365 if ((bus_space_read_4 (sc->sc_ba5_st, sc->sc_ba5_sh, 366 ARTISEA_DPA_PORT_BASE(0) + ARTISEA_SUPERSET_DPA_OFF + 367 ARTISEA_SUPDPFR) & SUPDPFR_SSCEN) != 0) { 368 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 369 "Spread-specturm clocking not supported by device\n"); 370 return; 371 } 372 373 /* Clear the LED0-only bit. */ 374 pci_conf_write (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0, 375 pci_conf_read (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0) & 376 ~SUECSR0_LED0_ONLY); 377 378 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 379 channel++) { 380 cp = &sc->pciide_channels[channel]; 381 if (artisea_chansetup(sc, channel, interface) == 0) 382 continue; 383 /* XXX We can probably do interrupts more efficiently. */ 384 artisea_mapregs(pa, cp, pciide_pci_intr); 385 } 386 } 387 388 static void 389 artisea_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 390 { 391 struct pciide_channel *cp; 392 pcireg_t interface; 393 int channel; 394 395 if (pciide_chipen(sc, pa) == 0) 396 return; 397 398 interface = PCI_INTERFACE(pa->pa_class); 399 400 if (interface == 0) { 401 artisea_chip_map_dpa (sc, pa); 402 return; 403 } 404 405 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 406 "bus-master DMA support present"); 407 #ifdef PCIIDE_I31244_DISABLEDMA 408 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 && 409 PCI_REVISION(pa->pa_class) == 0) { 410 aprint_verbose(" but disabled due to rev. 0"); 411 sc->sc_dma_ok = 0; 412 } else 413 #endif 414 pciide_mapreg_dma(sc, pa); 415 aprint_verbose("\n"); 416 417 /* 418 * XXX Configure LEDs to show activity. 419 */ 420 421 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 422 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 423 if (sc->sc_dma_ok) { 424 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 425 sc->sc_wdcdev.irqack = pciide_irqack; 426 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 427 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 428 } 429 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 430 431 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 432 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 433 434 wdc_allocate_regs(&sc->sc_wdcdev); 435 436 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 437 channel++) { 438 cp = &sc->pciide_channels[channel]; 439 if (pciide_chansetup(sc, channel, interface) == 0) 440 continue; 441 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 442 } 443 } 444
Indexes created Fri Oct 17 09:09:57 GMT 2025