artsata.c revision 1.24.2.3
1 /* $NetBSD: artsata.c,v 1.24.2.3 2017/12/03 11:37:07 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: artsata.c,v 1.24.2.3 2017/12/03 11:37:07 jdolecek Exp $"); 34 35 #include "opt_pciide.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pcidevs.h> 42 #include <dev/pci/pciidereg.h> 43 #include <dev/pci/pciidevar.h> 44 #include <dev/pci/pciide_i31244_reg.h> 45 46 #include <dev/ata/satareg.h> 47 #include <dev/ata/satavar.h> 48 #include <dev/ata/atareg.h> 49 #include <dev/ata/atavar.h> 50 51 static void artisea_chip_map(struct pciide_softc*, 52 const struct pci_attach_args *); 53 54 static int artsata_match(device_t, cfdata_t, void *); 55 static void artsata_attach(device_t, device_t, void *); 56 57 static const struct pciide_product_desc pciide_artsata_products[] = { 58 { PCI_PRODUCT_INTEL_31244, 59 0, 60 "Intel 31244 Serial ATA Controller", 61 artisea_chip_map, 62 }, 63 { 0, 64 0, 65 NULL, 66 NULL 67 } 68 }; 69 70 struct artisea_cmd_map 71 { 72 u_int8_t offset; 73 u_int8_t size; 74 }; 75 76 static const struct artisea_cmd_map artisea_dpa_cmd_map[] = 77 { 78 {ARTISEA_SUPDDR, 4}, /* 0 Data */ 79 {ARTISEA_SUPDER, 1}, /* 1 Error */ 80 {ARTISEA_SUPDCSR, 2}, /* 2 Sector Count */ 81 {ARTISEA_SUPDSNR, 2}, /* 3 Sector Number */ 82 {ARTISEA_SUPDCLR, 2}, /* 4 Cylinder Low */ 83 {ARTISEA_SUPDCHR, 2}, /* 5 Cylinder High */ 84 {ARTISEA_SUPDDHR, 1}, /* 6 Device/Head */ 85 {ARTISEA_SUPDCR, 1}, /* 7 Command */ 86 {ARTISEA_SUPDSR, 1}, /* 8 Status */ 87 {ARTISEA_SUPDFR, 2} /* 9 Feature */ 88 }; 89 90 #define ARTISEA_NUM_CHAN 4 91 92 CFATTACH_DECL_NEW(artsata, sizeof(struct pciide_softc), 93 artsata_match, artsata_attach, pciide_detach, NULL); 94 95 static int 96 artsata_match(device_t parent, cfdata_t match, void *aux) 97 { 98 struct pci_attach_args *pa = aux; 99 100 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 101 if (pciide_lookup_product(pa->pa_id, pciide_artsata_products)) 102 return (2); 103 } 104 return (0); 105 } 106 107 static void 108 artsata_attach(device_t parent, device_t self, void *aux) 109 { 110 struct pci_attach_args *pa = aux; 111 struct pciide_softc *sc = device_private(self); 112 113 self->dv_maxphys = MIN(parent->dv_maxphys, MACHINE_MAXPHYS); 114 115 sc->sc_wdcdev.sc_atac.atac_dev = self; 116 117 pciide_common_attach(sc, pa, 118 pciide_lookup_product(pa->pa_id, pciide_artsata_products)); 119 120 } 121 122 static void 123 artisea_mapregs(const struct pci_attach_args *pa, struct pciide_channel *cp, 124 int (*pci_intr)(void *)) 125 { 126 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 127 struct ata_channel *wdc_cp = &cp->ata_channel; 128 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 129 const char *intrstr; 130 pci_intr_handle_t intrhandle; 131 int i; 132 char intrbuf[PCI_INTRSTR_LEN]; 133 134 cp->compat = 0; 135 136 if (sc->sc_pci_ih == NULL) { 137 if (pci_intr_map(pa, &intrhandle) != 0) { 138 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 139 "couldn't map native-PCI interrupt\n"); 140 goto bad; 141 } 142 intrstr = pci_intr_string(pa->pa_pc, intrhandle, 143 intrbuf, sizeof(intrbuf)); 144 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 145 intrhandle, IPL_BIO, pci_intr, sc); 146 if (sc->sc_pci_ih != NULL) { 147 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 148 "using %s for native-PCI interrupt\n", intrstr); 149 } else { 150 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 151 "couldn't establish native-PCI interrupt"); 152 if (intrstr != NULL) 153 aprint_error(" at %s", intrstr); 154 aprint_error("\n"); 155 goto bad; 156 } 157 } 158 cp->ih = sc->sc_pci_ih; 159 wdr->cmd_iot = sc->sc_ba5_st; 160 if (bus_space_subregion (sc->sc_ba5_st, sc->sc_ba5_sh, 161 ARTISEA_DPA_PORT_BASE(wdc_cp->ch_channel), 0x200, 162 &wdr->cmd_baseioh) != 0) { 163 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 164 "couldn't map %s channel cmd regs\n", cp->name); 165 goto bad; 166 } 167 168 wdr->ctl_iot = sc->sc_ba5_st; 169 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 170 ARTISEA_SUPDDCTLR, 1, &cp->ctl_baseioh) != 0) { 171 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 172 "couldn't map %s channel ctl regs\n", cp->name); 173 goto bad; 174 } 175 wdr->ctl_ioh = cp->ctl_baseioh; 176 177 for (i = 0; i < WDC_NREG + 2; i++) { 178 179 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 180 artisea_dpa_cmd_map[i].offset, artisea_dpa_cmd_map[i].size, 181 &wdr->cmd_iohs[i]) != 0) { 182 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 183 "couldn't subregion %s channel cmd regs\n", 184 cp->name); 185 goto bad; 186 } 187 } 188 wdr->data32iot = wdr->cmd_iot; 189 wdr->data32ioh = wdr->cmd_iohs[0]; 190 191 wdr->sata_iot = wdr->cmd_iot; 192 wdr->sata_baseioh = wdr->cmd_baseioh; 193 194 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 195 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSSR, 1, 196 &wdr->sata_status) != 0) { 197 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 198 "couldn't map channel %d sata_status regs\n", 199 wdc_cp->ch_channel); 200 goto bad; 201 } 202 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 203 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSER, 1, 204 &wdr->sata_error) != 0) { 205 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 206 "couldn't map channel %d sata_error regs\n", 207 wdc_cp->ch_channel); 208 goto bad; 209 } 210 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 211 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, 1, 212 &wdr->sata_control) != 0) { 213 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 214 "couldn't map channel %d sata_control regs\n", 215 wdc_cp->ch_channel); 216 goto bad; 217 } 218 219 wdcattach(wdc_cp); 220 return; 221 222 bad: 223 wdc_cp->ch_flags |= ATACH_DISABLED; 224 return; 225 } 226 227 static int 228 artisea_chansetup(struct pciide_softc *sc, int channel, 229 pcireg_t interface) 230 { 231 struct pciide_channel *cp = &sc->pciide_channels[channel]; 232 sc->wdc_chanarray[channel] = &cp->ata_channel; 233 cp->name = PCIIDE_CHANNEL_NAME(channel); 234 cp->ata_channel.ch_channel = channel; 235 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 236 237 return 1; 238 } 239 240 static void 241 artisea_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 242 { 243 struct pciide_channel *pc; 244 int chan; 245 u_int32_t dma_ctl; 246 u_int32_t cacheline_len; 247 248 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 249 "bus-master DMA support present"); 250 251 sc->sc_dma_ok = 1; 252 253 /* 254 * Errata #4 says that if the cacheline length is not set correctly, 255 * we can get corrupt MWI and Memory-Block-Write transactions. 256 */ 257 cacheline_len = PCI_CACHELINE(pci_conf_read (pa->pa_pc, pa->pa_tag, 258 PCI_BHLC_REG)); 259 if (cacheline_len == 0) { 260 aprint_verbose(", but unused (cacheline size not set in PCI conf)\n"); 261 sc->sc_dma_ok = 0; 262 return; 263 } 264 265 /* 266 * Final step of the work-around is to force the DMA engine to use 267 * the cache-line length information. 268 */ 269 dma_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR); 270 dma_ctl |= SUDCSCR_DMA_WCAE | SUDCSCR_DMA_RCAE; 271 pci_conf_write(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR, dma_ctl); 272 273 sc->sc_wdcdev.dma_arg = sc; 274 sc->sc_wdcdev.dma_init = pciide_dma_init; 275 sc->sc_wdcdev.dma_start = pciide_dma_start; 276 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 277 sc->sc_dma_iot = sc->sc_ba5_st; 278 sc->sc_dmat = pa->pa_dmat; 279 280 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 281 PCIIDE_OPTIONS_NODMA) { 282 aprint_verbose( 283 ", but unused (forced off by config file)\n"); 284 sc->sc_dma_ok = 0; 285 return; 286 } 287 288 /* 289 * Set up the default handles for the DMA registers. 290 * Just reserve 32 bits for each handle, unless space 291 * doesn't permit it. 292 */ 293 for (chan = 0; chan < ARTISEA_NUM_CHAN; chan++) { 294 pc = &sc->pciide_channels[chan]; 295 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 296 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDCMDR, 2, 297 &pc->dma_iohs[IDEDMA_CMD]) != 0 || 298 bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 299 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDSR, 1, 300 &pc->dma_iohs[IDEDMA_CTL]) != 0 || 301 bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 302 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDDTPR, 4, 303 &pc->dma_iohs[IDEDMA_TBL]) != 0) { 304 sc->sc_dma_ok = 0; 305 aprint_verbose(", but can't subregion registers\n"); 306 return; 307 } 308 } 309 310 aprint_verbose("\n"); 311 } 312 313 static void 314 artisea_chip_map_dpa(struct pciide_softc *sc, const struct pci_attach_args *pa) 315 { 316 struct pciide_channel *cp; 317 pcireg_t interface; 318 int channel; 319 320 interface = PCI_INTERFACE(pa->pa_class); 321 322 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 323 "interface wired in DPA mode\n"); 324 325 if (pci_mapreg_map(pa, ARTISEA_PCI_DPA_BASE, PCI_MAPREG_MEM_TYPE_64BIT, 326 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) 327 return; 328 329 artisea_mapreg_dma(sc, pa); 330 331 sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS; 332 333 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 334 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 335 if (sc->sc_dma_ok) { 336 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 337 sc->sc_wdcdev.irqack = pciide_irqack; 338 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 339 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 340 } 341 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 342 343 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 344 sc->sc_wdcdev.sc_atac.atac_nchannels = ARTISEA_NUM_CHAN; 345 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 346 sc->sc_wdcdev.wdc_maxdrives = 1; 347 348 wdc_allocate_regs(&sc->sc_wdcdev); 349 350 /* 351 * Perform a quick check to ensure that the device isn't configured 352 * in Spread-spectrum clocking mode. This feature is buggy and has 353 * been removed from the latest documentation. 354 * 355 * Note that although this bit is in the Channel regs, it's the same 356 * for all channels, so we check it just once here. 357 */ 358 if ((bus_space_read_4 (sc->sc_ba5_st, sc->sc_ba5_sh, 359 ARTISEA_DPA_PORT_BASE(0) + ARTISEA_SUPERSET_DPA_OFF + 360 ARTISEA_SUPDPFR) & SUPDPFR_SSCEN) != 0) { 361 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 362 "Spread-specturm clocking not supported by device\n"); 363 return; 364 } 365 366 /* Clear the LED0-only bit. */ 367 pci_conf_write (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0, 368 pci_conf_read (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0) & 369 ~SUECSR0_LED0_ONLY); 370 371 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 372 channel++) { 373 cp = &sc->pciide_channels[channel]; 374 if (artisea_chansetup(sc, channel, interface) == 0) 375 continue; 376 /* XXX We can probably do interrupts more efficiently. */ 377 artisea_mapregs(pa, cp, pciide_pci_intr); 378 } 379 } 380 381 static void 382 artisea_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 383 { 384 struct pciide_channel *cp; 385 pcireg_t interface; 386 int channel; 387 388 if (pciide_chipen(sc, pa) == 0) 389 return; 390 391 interface = PCI_INTERFACE(pa->pa_class); 392 393 if (interface == 0) { 394 artisea_chip_map_dpa (sc, pa); 395 return; 396 } 397 398 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 399 "bus-master DMA support present"); 400 #ifdef PCIIDE_I31244_DISABLEDMA 401 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 && 402 PCI_REVISION(pa->pa_class) == 0) { 403 aprint_verbose(" but disabled due to rev. 0"); 404 sc->sc_dma_ok = 0; 405 } else 406 #endif 407 pciide_mapreg_dma(sc, pa); 408 aprint_verbose("\n"); 409 410 /* 411 * XXX Configure LEDs to show activity. 412 */ 413 414 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 415 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 416 if (sc->sc_dma_ok) { 417 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 418 sc->sc_wdcdev.irqack = pciide_irqack; 419 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 420 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 421 } 422 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 423 424 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 425 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 426 427 wdc_allocate_regs(&sc->sc_wdcdev); 428 429 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 430 channel++) { 431 cp = &sc->pciide_channels[channel]; 432 if (pciide_chansetup(sc, channel, interface) == 0) 433 continue; 434 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 435 } 436 } 437
Indexes created Mon Oct 20 01:09:56 GMT 2025