artsata.c revision 1.4.6.1
1 /* $NetBSD: artsata.c,v 1.4.6.1 2005/02/12 18:17:47 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_pciide.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/malloc.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/pciidereg.h> 48 #include <dev/pci/pciidevar.h> 49 #include <dev/pci/pciide_i31244_reg.h> 50 51 #include <dev/ata/satareg.h> 52 #include <dev/ata/satavar.h> 53 #include <dev/ata/atareg.h> 54 #include <dev/ata/atavar.h> 55 56 static void artisea_chip_map(struct pciide_softc*, struct pci_attach_args *); 57 58 static int artsata_match(struct device *, struct cfdata *, void *); 59 static void artsata_attach(struct device *, struct device *, void *); 60 61 static const struct pciide_product_desc pciide_artsata_products[] = { 62 { PCI_PRODUCT_INTEL_31244, 63 0, 64 "Intel 31244 Serial ATA Controller", 65 artisea_chip_map, 66 }, 67 { 0, 68 0, 69 NULL, 70 NULL 71 } 72 }; 73 74 struct artisea_cmd_map 75 { 76 u_int8_t offset; 77 u_int8_t size; 78 }; 79 80 static const struct artisea_cmd_map artisea_dpa_cmd_map[] = 81 { 82 {ARTISEA_SUPDDR, 4}, /* 0 Data */ 83 {ARTISEA_SUPDER, 1}, /* 1 Error */ 84 {ARTISEA_SUPDCSR, 2}, /* 2 Sector Count */ 85 {ARTISEA_SUPDSNR, 2}, /* 3 Sector Number */ 86 {ARTISEA_SUPDCLR, 2}, /* 4 Cylinder Low */ 87 {ARTISEA_SUPDCHR, 2}, /* 5 Cylinder High */ 88 {ARTISEA_SUPDDHR, 1}, /* 6 Device/Head */ 89 {ARTISEA_SUPDCR, 1}, /* 7 Command */ 90 {ARTISEA_SUPDSR, 1}, /* 8 Status */ 91 {ARTISEA_SUPDFR, 2} /* 9 Feature */ 92 }; 93 94 #define ARTISEA_NUM_CHAN 4 95 96 CFATTACH_DECL(artsata, sizeof(struct pciide_softc), 97 artsata_match, artsata_attach, NULL, NULL); 98 99 static int 100 artsata_match(struct device *parent, struct cfdata *match, void *aux) 101 { 102 struct pci_attach_args *pa = aux; 103 104 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 105 if (pciide_lookup_product(pa->pa_id, pciide_artsata_products)) 106 return (2); 107 } 108 return (0); 109 } 110 111 static void 112 artsata_attach(struct device *parent, struct device *self, void *aux) 113 { 114 struct pci_attach_args *pa = aux; 115 struct pciide_softc *sc = (struct pciide_softc *)self; 116 117 pciide_common_attach(sc, pa, 118 pciide_lookup_product(pa->pa_id, pciide_artsata_products)); 119 120 } 121 122 static void 123 artisea_drv_probe(struct ata_channel *chp) 124 { 125 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 126 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 127 uint32_t scontrol, sstatus; 128 uint16_t scnt, sn, cl, ch; 129 int i, s; 130 131 /* XXX This should be done by other code. */ 132 for (i = 0; i < 2; i++) { 133 chp->ch_drive[i].chnl_softc = chp; 134 chp->ch_drive[i].drive = i; 135 } 136 137 /* 138 * First we have to bring the PHYs online, in case the firmware 139 * has not already done so. The 31244 leaves the disks off-line 140 * on reset to avoid excessive power surges due to multiple spindle 141 * spin up. 142 * 143 * The work-around for errata #1 says that we must write 0 to the 144 * port first to be sure of correctly initializing the device. 145 * 146 * XXX will this try to bring multiple disks on-line too quickly? 147 */ 148 bus_space_write_4 (wdr->cmd_iot, wdr->cmd_baseioh, 149 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, 0); 150 scontrol = SControl_IPM_NONE | SControl_SPD_ANY | SControl_DET_INIT; 151 bus_space_write_4 (wdr->cmd_iot, wdr->cmd_baseioh, 152 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, scontrol); 153 154 scontrol &= ~SControl_DET_INIT; 155 bus_space_write_4 (wdr->cmd_iot, wdr->cmd_baseioh, 156 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, scontrol); 157 158 delay(50 * 1000); 159 sstatus = bus_space_read_4(wdr->cmd_iot, wdr->cmd_baseioh, 160 ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSSR); 161 162 switch (sstatus & SStatus_DET_mask) { 163 case SStatus_DET_NODEV: 164 /* No Device; be silent. */ 165 break; 166 167 case SStatus_DET_DEV_NE: 168 aprint_error("%s: port %d: device connected, but " 169 "communication not established\n", 170 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 171 break; 172 173 case SStatus_DET_OFFLINE: 174 aprint_error("%s: port %d: PHY offline\n", 175 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 176 break; 177 178 case SStatus_DET_DEV: 179 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 180 WDSD_IBM); 181 delay(10); /* 400ns delay */ 182 scnt = bus_space_read_2(wdr->cmd_iot, 183 wdr->cmd_iohs[wd_seccnt], 0); 184 sn = bus_space_read_2(wdr->cmd_iot, 185 wdr->cmd_iohs[wd_sector], 0); 186 cl = bus_space_read_2(wdr->cmd_iot, 187 wdr->cmd_iohs[wd_cyl_lo], 0); 188 ch = bus_space_read_2(wdr->cmd_iot, 189 wdr->cmd_iohs[wd_cyl_hi], 0); 190 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 191 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 192 scnt, sn, cl, ch); 193 /* 194 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 195 * cases we get wrong values here, so ignore it. 196 */ 197 s = splbio(); 198 if (cl == 0x14 && ch == 0xeb) 199 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 200 else 201 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 202 splx(s); 203 204 aprint_normal("%s: port %d: device present, speed: %s\n", 205 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 206 sata_speed(sstatus)); 207 break; 208 209 default: 210 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 211 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 212 sstatus); 213 } 214 215 } 216 217 static void 218 artisea_mapregs(struct pci_attach_args *pa, struct pciide_channel *cp, 219 bus_size_t *cmdsizep, bus_size_t *ctlsizep, int (*pci_intr)(void *)) 220 { 221 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 222 struct ata_channel *wdc_cp = &cp->ata_channel; 223 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 224 const char *intrstr; 225 pci_intr_handle_t intrhandle; 226 int i; 227 228 cp->compat = 0; 229 230 if (sc->sc_pci_ih == NULL) { 231 if (pci_intr_map(pa, &intrhandle) != 0) { 232 aprint_error("%s: couldn't map native-PCI interrupt\n", 233 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 234 goto bad; 235 } 236 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 237 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 238 intrhandle, IPL_BIO, pci_intr, sc); 239 if (sc->sc_pci_ih != NULL) { 240 aprint_normal("%s: using %s for native-PCI interrupt\n", 241 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 242 intrstr ? intrstr : "unknown interrupt"); 243 } else { 244 aprint_error( 245 "%s: couldn't establish native-PCI interrupt", 246 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 247 if (intrstr != NULL) 248 aprint_normal(" at %s", intrstr); 249 aprint_normal("\n"); 250 goto bad; 251 } 252 } 253 cp->ih = sc->sc_pci_ih; 254 wdr->cmd_iot = sc->sc_ba5_st; 255 if (bus_space_subregion (sc->sc_ba5_st, sc->sc_ba5_sh, 256 ARTISEA_DPA_PORT_BASE(wdc_cp->ch_channel), 0x200, 257 &wdr->cmd_baseioh) != 0) { 258 aprint_error("%s: couldn't map %s channel cmd regs\n", 259 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 260 goto bad; 261 } 262 263 wdr->ctl_iot = sc->sc_ba5_st; 264 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 265 ARTISEA_SUPDDCTLR, 1, &cp->ctl_baseioh) != 0) { 266 aprint_error("%s: couldn't map %s channel ctl regs\n", 267 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 268 goto bad; 269 } 270 wdr->ctl_ioh = cp->ctl_baseioh; 271 272 for (i = 0; i < WDC_NREG + 2; i++) { 273 274 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 275 artisea_dpa_cmd_map[i].offset, artisea_dpa_cmd_map[i].size, 276 &wdr->cmd_iohs[i]) != 0) { 277 aprint_error("%s: couldn't subregion %s channel " 278 "cmd regs\n", 279 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 280 goto bad; 281 } 282 } 283 wdr->data32iot = wdr->cmd_iot; 284 wdr->data32ioh = wdr->cmd_iohs[0]; 285 286 wdcattach(wdc_cp); 287 return; 288 289 bad: 290 cp->ata_channel.ch_flags |= ATACH_DISABLED; 291 return; 292 } 293 294 static int 295 artisea_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface) 296 { 297 struct pciide_channel *cp = &sc->pciide_channels[channel]; 298 sc->wdc_chanarray[channel] = &cp->ata_channel; 299 cp->name = PCIIDE_CHANNEL_NAME(channel); 300 cp->ata_channel.ch_channel = channel; 301 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 302 cp->ata_channel.ch_queue = 303 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 304 if (cp->ata_channel.ch_queue == NULL) { 305 aprint_error("%s %s channel: " 306 "can't allocate memory for command queue", 307 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 308 return 0; 309 } 310 return 1; 311 } 312 313 static void 314 artisea_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 315 { 316 struct pciide_channel *pc; 317 int chan; 318 u_int32_t dma_ctl; 319 u_int32_t cacheline_len; 320 321 aprint_normal("%s: bus-master DMA support present", 322 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 323 324 sc->sc_dma_ok = 1; 325 326 /* 327 * Errata #4 says that if the cacheline length is not set correctly, 328 * we can get corrupt MWI and Memory-Block-Write transactions. 329 */ 330 cacheline_len = PCI_CACHELINE(pci_conf_read (pa->pa_pc, pa->pa_tag, 331 PCI_BHLC_REG)); 332 if (cacheline_len == 0) { 333 aprint_normal(", but unused (cacheline size not set in PCI conf)\n"); 334 sc->sc_dma_ok = 0; 335 return; 336 } 337 338 /* 339 * Final step of the work-around is to force the DMA engine to use 340 * the cache-line length information. 341 */ 342 dma_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR); 343 dma_ctl |= SUDCSCR_DMA_WCAE | SUDCSCR_DMA_RCAE; 344 pci_conf_write(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR, dma_ctl); 345 346 sc->sc_wdcdev.dma_arg = sc; 347 sc->sc_wdcdev.dma_init = pciide_dma_init; 348 sc->sc_wdcdev.dma_start = pciide_dma_start; 349 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 350 sc->sc_dma_iot = sc->sc_ba5_st; 351 sc->sc_dmat = pa->pa_dmat; 352 353 if (sc->sc_wdcdev.sc_atac.atac_dev.dv_cfdata->cf_flags & 354 PCIIDE_OPTIONS_NODMA) { 355 aprint_normal( 356 ", but unused (forced off by config file)\n"); 357 sc->sc_dma_ok = 0; 358 return; 359 } 360 361 /* 362 * Set up the default handles for the DMA registers. 363 * Just reserve 32 bits for each handle, unless space 364 * doesn't permit it. 365 */ 366 for (chan = 0; chan < ARTISEA_NUM_CHAN; chan++) { 367 pc = &sc->pciide_channels[chan]; 368 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 369 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDCMDR, 2, 370 &pc->dma_iohs[IDEDMA_CMD]) != 0 || 371 bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 372 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDSR, 1, 373 &pc->dma_iohs[IDEDMA_CTL]) != 0 || 374 bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 375 ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDDTPR, 4, 376 &pc->dma_iohs[IDEDMA_TBL]) != 0) { 377 sc->sc_dma_ok = 0; 378 aprint_normal(", but can't subregion registers\n"); 379 return; 380 } 381 } 382 383 aprint_normal("\n"); 384 } 385 386 static void 387 artisea_chip_map_dpa(struct pciide_softc *sc, struct pci_attach_args *pa) 388 { 389 struct pciide_channel *cp; 390 bus_size_t cmdsize, ctlsize; 391 pcireg_t interface; 392 int channel; 393 394 interface = PCI_INTERFACE(pa->pa_class); 395 396 aprint_normal("%s: interface wired in DPA mode\n", 397 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 398 399 if (pci_mapreg_map(pa, ARTISEA_PCI_DPA_BASE, PCI_MAPREG_MEM_TYPE_64BIT, 400 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, NULL) != 0) 401 return; 402 403 artisea_mapreg_dma(sc, pa); 404 405 sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS; 406 407 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 408 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 409 if (sc->sc_dma_ok) { 410 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 411 sc->sc_wdcdev.irqack = pciide_irqack; 412 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 413 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 414 } 415 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 416 417 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 418 sc->sc_wdcdev.sc_atac.atac_nchannels = ARTISEA_NUM_CHAN; 419 sc->sc_wdcdev.sc_atac.atac_probe = artisea_drv_probe; 420 421 wdc_allocate_regs(&sc->sc_wdcdev); 422 423 /* 424 * Perform a quick check to ensure that the device isn't configured 425 * in Spread-spectrum clocking mode. This feature is buggy and has 426 * been removed from the latest documentation. 427 * 428 * Note that although this bit is in the Channel regs, it's the same 429 * for all channels, so we check it just once here. 430 */ 431 if ((bus_space_read_4 (sc->sc_ba5_st, sc->sc_ba5_sh, 432 ARTISEA_DPA_PORT_BASE(0) + ARTISEA_SUPERSET_DPA_OFF + 433 ARTISEA_SUPDPFR) & SUPDPFR_SSCEN) != 0) { 434 aprint_error("%s: Spread-specturm clocking not supported by device\n", 435 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 436 return; 437 } 438 439 /* Clear the LED0-only bit. */ 440 pci_conf_write (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0, 441 pci_conf_read (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0) & 442 ~SUECSR0_LED0_ONLY); 443 444 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 445 channel++) { 446 cp = &sc->pciide_channels[channel]; 447 if (artisea_chansetup(sc, channel, interface) == 0) 448 continue; 449 /* XXX We can probably do interrupts more efficiently. */ 450 artisea_mapregs(pa, cp, &cmdsize, &ctlsize, pciide_pci_intr); 451 } 452 } 453 454 static void 455 artisea_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 456 { 457 struct pciide_channel *cp; 458 bus_size_t cmdsize, ctlsize; 459 pcireg_t interface; 460 int channel; 461 462 if (pciide_chipen(sc, pa) == 0) 463 return; 464 465 interface = PCI_INTERFACE(pa->pa_class); 466 467 if (interface == 0) { 468 artisea_chip_map_dpa (sc, pa); 469 return; 470 } 471 472 aprint_normal("%s: bus-master DMA support present", 473 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 474 #ifdef PCIIDE_I31244_DISABLEDMA 475 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 && 476 PCI_REVISION(pa->pa_class) == 0) { 477 aprint_normal(" but disabled due to rev. 0"); 478 sc->sc_dma_ok = 0; 479 } else 480 #endif 481 pciide_mapreg_dma(sc, pa); 482 aprint_normal("\n"); 483 484 /* 485 * XXX Configure LEDs to show activity. 486 */ 487 488 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 489 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 490 if (sc->sc_dma_ok) { 491 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 492 sc->sc_wdcdev.irqack = pciide_irqack; 493 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 494 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 495 } 496 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 497 498 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 499 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 500 501 wdc_allocate_regs(&sc->sc_wdcdev); 502 503 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 504 channel++) { 505 cp = &sc->pciide_channels[channel]; 506 if (pciide_chansetup(sc, channel, interface) == 0) 507 continue; 508 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 509 pciide_pci_intr); 510 } 511 } 512
Indexes created Fri Oct 17 09:09:57 GMT 2025