auacer.c revision 1.1.2.7
1 1.1.2.7 skrll /* $NetBSD: auacer.c,v 1.1.2.7 2005/11/10 14:06:00 skrll Exp $ */ 2 1.1.2.2 skrll 3 1.1.2.2 skrll /*- 4 1.1.2.2 skrll * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 1.1.2.2 skrll * All rights reserved. 6 1.1.2.2 skrll * 7 1.1.2.2 skrll * This code is derived from software contributed to The NetBSD Foundation 8 1.1.2.2 skrll * by Lennart Augustsson. 9 1.1.2.2 skrll * 10 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 11 1.1.2.2 skrll * modification, are permitted provided that the following conditions 12 1.1.2.2 skrll * are met: 13 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 14 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 15 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 16 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 17 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 18 1.1.2.2 skrll * 3. All advertising materials mentioning features or use of this software 19 1.1.2.2 skrll * must display the following acknowledgement: 20 1.1.2.2 skrll * This product includes software developed by the NetBSD 21 1.1.2.2 skrll * Foundation, Inc. and its contributors. 22 1.1.2.2 skrll * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.1.2.2 skrll * contributors may be used to endorse or promote products derived 24 1.1.2.2 skrll * from this software without specific prior written permission. 25 1.1.2.2 skrll * 26 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.1.2.2 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.1.2.2 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.1.2.2 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.1.2.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.1.2.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.1.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.1.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.1.2.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.1.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.1.2.2 skrll * POSSIBILITY OF SUCH DAMAGE. 37 1.1.2.2 skrll */ 38 1.1.2.2 skrll 39 1.1.2.2 skrll /* 40 1.1.2.2 skrll * Acer Labs M5455 audio driver 41 1.1.2.2 skrll * 42 1.1.2.4 skrll * Acer provides data sheets after signing an NDA, so this is guess work. 43 1.1.2.2 skrll * The chip behaves somewhat like the Intel i8x0, so this driver 44 1.1.2.2 skrll * is loosely based on the auich driver. Additional information taken from 45 1.1.2.2 skrll * the ALSA intel8x0.c driver (which handles M5455 as well). 46 1.1.2.2 skrll * 47 1.1.2.2 skrll * As an historical note one can observe that the auich driver borrows 48 1.1.2.2 skrll * lot from the first NetBSD PCI audio driver, the eap driver. But this 49 1.1.2.2 skrll * is not attributed anywhere. 50 1.1.2.2 skrll */ 51 1.1.2.2 skrll 52 1.1.2.2 skrll 53 1.1.2.2 skrll #include <sys/cdefs.h> 54 1.1.2.7 skrll __KERNEL_RCSID(0, "$NetBSD: auacer.c,v 1.1.2.7 2005/11/10 14:06:00 skrll Exp $"); 55 1.1.2.2 skrll 56 1.1.2.2 skrll #include <sys/param.h> 57 1.1.2.2 skrll #include <sys/systm.h> 58 1.1.2.2 skrll #include <sys/kernel.h> 59 1.1.2.2 skrll #include <sys/malloc.h> 60 1.1.2.2 skrll #include <sys/device.h> 61 1.1.2.2 skrll #include <sys/fcntl.h> 62 1.1.2.2 skrll #include <sys/proc.h> 63 1.1.2.2 skrll 64 1.1.2.2 skrll #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 65 1.1.2.2 skrll 66 1.1.2.2 skrll #include <dev/pci/pcidevs.h> 67 1.1.2.2 skrll #include <dev/pci/pcivar.h> 68 1.1.2.2 skrll #include <dev/pci/auacerreg.h> 69 1.1.2.2 skrll 70 1.1.2.2 skrll #include <sys/audioio.h> 71 1.1.2.2 skrll #include <dev/audio_if.h> 72 1.1.2.2 skrll #include <dev/mulaw.h> 73 1.1.2.2 skrll #include <dev/auconv.h> 74 1.1.2.2 skrll 75 1.1.2.2 skrll #include <machine/bus.h> 76 1.1.2.2 skrll 77 1.1.2.2 skrll #include <dev/ic/ac97reg.h> 78 1.1.2.2 skrll #include <dev/ic/ac97var.h> 79 1.1.2.2 skrll 80 1.1.2.2 skrll struct auacer_dma { 81 1.1.2.2 skrll bus_dmamap_t map; 82 1.1.2.2 skrll caddr_t addr; 83 1.1.2.2 skrll bus_dma_segment_t segs[1]; 84 1.1.2.2 skrll int nsegs; 85 1.1.2.2 skrll size_t size; 86 1.1.2.2 skrll struct auacer_dma *next; 87 1.1.2.2 skrll }; 88 1.1.2.2 skrll 89 1.1.2.2 skrll #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 90 1.1.2.2 skrll #define KERNADDR(p) ((void *)((p)->addr)) 91 1.1.2.2 skrll 92 1.1.2.2 skrll struct auacer_cdata { 93 1.1.2.2 skrll struct auacer_dmalist ic_dmalist_pcmo[ALI_DMALIST_MAX]; 94 1.1.2.2 skrll }; 95 1.1.2.2 skrll 96 1.1.2.2 skrll struct auacer_chan { 97 1.1.2.2 skrll uint32_t ptr; 98 1.1.2.2 skrll uint32_t start, p, end; 99 1.1.2.2 skrll uint32_t blksize, fifoe; 100 1.1.2.2 skrll uint32_t ack; 101 1.1.2.2 skrll uint32_t port; 102 1.1.2.2 skrll struct auacer_dmalist *dmalist; 103 1.1.2.2 skrll void (*intr)(void *); 104 1.1.2.2 skrll void *arg; 105 1.1.2.2 skrll }; 106 1.1.2.2 skrll 107 1.1.2.2 skrll struct auacer_softc { 108 1.1.2.2 skrll struct device sc_dev; 109 1.1.2.2 skrll void *sc_ih; 110 1.1.2.2 skrll 111 1.1.2.2 skrll audio_device_t sc_audev; 112 1.1.2.2 skrll 113 1.1.2.2 skrll bus_space_tag_t iot; 114 1.1.2.2 skrll bus_space_handle_t mix_ioh; 115 1.1.2.2 skrll bus_space_handle_t aud_ioh; 116 1.1.2.2 skrll bus_dma_tag_t dmat; 117 1.1.2.2 skrll 118 1.1.2.2 skrll struct ac97_codec_if *codec_if; 119 1.1.2.2 skrll struct ac97_host_if host_if; 120 1.1.2.2 skrll 121 1.1.2.2 skrll /* DMA scatter-gather lists. */ 122 1.1.2.2 skrll bus_dmamap_t sc_cddmamap; 123 1.1.2.2 skrll #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 124 1.1.2.2 skrll 125 1.1.2.2 skrll struct auacer_cdata *sc_cdata; 126 1.1.2.2 skrll 127 1.1.2.2 skrll struct auacer_chan sc_pcmo; 128 1.1.2.2 skrll 129 1.1.2.2 skrll struct auacer_dma *sc_dmas; 130 1.1.2.2 skrll 131 1.1.2.2 skrll pci_chipset_tag_t sc_pc; 132 1.1.2.2 skrll pcitag_t sc_pt; 133 1.1.2.2 skrll 134 1.1.2.2 skrll int sc_dmamap_flags; 135 1.1.2.2 skrll 136 1.1.2.2 skrll /* Power Management */ 137 1.1.2.2 skrll void *sc_powerhook; 138 1.1.2.2 skrll int sc_suspend; 139 1.1.2.4 skrll 140 1.1.2.4 skrll #define AUACER_NFORMATS 3 141 1.1.2.4 skrll struct audio_format sc_formats[AUACER_NFORMATS]; 142 1.1.2.4 skrll struct audio_encoding_set *sc_encodings; 143 1.1.2.2 skrll }; 144 1.1.2.2 skrll 145 1.1.2.2 skrll #define READ1(sc, a) bus_space_read_1(sc->iot, sc->aud_ioh, a) 146 1.1.2.2 skrll #define READ2(sc, a) bus_space_read_2(sc->iot, sc->aud_ioh, a) 147 1.1.2.2 skrll #define READ4(sc, a) bus_space_read_4(sc->iot, sc->aud_ioh, a) 148 1.1.2.2 skrll #define WRITE1(sc, a, v) bus_space_write_1(sc->iot, sc->aud_ioh, a, v) 149 1.1.2.2 skrll #define WRITE2(sc, a, v) bus_space_write_2(sc->iot, sc->aud_ioh, a, v) 150 1.1.2.2 skrll #define WRITE4(sc, a, v) bus_space_write_4(sc->iot, sc->aud_ioh, a, v) 151 1.1.2.2 skrll 152 1.1.2.2 skrll /* Debug */ 153 1.1.2.2 skrll #ifdef AUACER_DEBUG 154 1.1.2.2 skrll #define DPRINTF(l,x) do { if (auacer_debug & (l)) printf x; } while(0) 155 1.1.2.2 skrll int auacer_debug = 0; 156 1.1.2.2 skrll #define ALI_DEBUG_CODECIO 0x0001 157 1.1.2.2 skrll #define ALI_DEBUG_DMA 0x0002 158 1.1.2.2 skrll #define ALI_DEBUG_INTR 0x0004 159 1.1.2.2 skrll #define ALI_DEBUG_API 0x0008 160 1.1.2.2 skrll #define ALI_DEBUG_MIXERAPI 0x0010 161 1.1.2.2 skrll #else 162 1.1.2.2 skrll #define DPRINTF(x,y) /* nothing */ 163 1.1.2.2 skrll #endif 164 1.1.2.2 skrll 165 1.1.2.7 skrll static int auacer_intr(void *); 166 1.1.2.2 skrll 167 1.1.2.7 skrll static int auacer_query_encoding(void *, struct audio_encoding *); 168 1.1.2.7 skrll static int auacer_set_params(void *, int, int, audio_params_t *, 169 1.1.2.7 skrll audio_params_t *, stream_filter_list_t *, 170 1.1.2.7 skrll stream_filter_list_t *); 171 1.1.2.7 skrll static int auacer_round_blocksize(void *, int, int, 172 1.1.2.7 skrll const audio_params_t *); 173 1.1.2.7 skrll static int auacer_halt_output(void *); 174 1.1.2.7 skrll static int auacer_halt_input(void *); 175 1.1.2.7 skrll static int auacer_getdev(void *, struct audio_device *); 176 1.1.2.7 skrll static int auacer_set_port(void *, mixer_ctrl_t *); 177 1.1.2.7 skrll static int auacer_get_port(void *, mixer_ctrl_t *); 178 1.1.2.7 skrll static int auacer_query_devinfo(void *, mixer_devinfo_t *); 179 1.1.2.7 skrll static void *auacer_allocm(void *, int, size_t, struct malloc_type *, int); 180 1.1.2.7 skrll static void auacer_freem(void *, void *, struct malloc_type *); 181 1.1.2.7 skrll static size_t auacer_round_buffersize(void *, int, size_t); 182 1.1.2.7 skrll static paddr_t auacer_mappage(void *, void *, off_t, int); 183 1.1.2.7 skrll static int auacer_get_props(void *); 184 1.1.2.7 skrll static int auacer_trigger_output(void *, void *, void *, int, 185 1.1.2.7 skrll void (*)(void *), void *, 186 1.1.2.7 skrll const audio_params_t *); 187 1.1.2.7 skrll static int auacer_trigger_input(void *, void *, void *, int, 188 1.1.2.7 skrll void (*)(void *), void *, 189 1.1.2.7 skrll const audio_params_t *); 190 1.1.2.7 skrll 191 1.1.2.7 skrll static int auacer_alloc_cdata(struct auacer_softc *); 192 1.1.2.7 skrll 193 1.1.2.7 skrll static int auacer_allocmem(struct auacer_softc *, size_t, size_t, 194 1.1.2.7 skrll struct auacer_dma *); 195 1.1.2.7 skrll static int auacer_freemem(struct auacer_softc *, struct auacer_dma *); 196 1.1.2.2 skrll 197 1.1.2.7 skrll static void auacer_powerhook(int, void *); 198 1.1.2.7 skrll static int auacer_set_rate(struct auacer_softc *, int, u_int); 199 1.1.2.2 skrll 200 1.1.2.2 skrll static void auacer_reset(struct auacer_softc *sc); 201 1.1.2.2 skrll 202 1.1.2.7 skrll static struct audio_hw_if auacer_hw_if = { 203 1.1.2.5 skrll NULL, /* open */ 204 1.1.2.5 skrll NULL, /* close */ 205 1.1.2.2 skrll NULL, /* drain */ 206 1.1.2.2 skrll auacer_query_encoding, 207 1.1.2.2 skrll auacer_set_params, 208 1.1.2.2 skrll auacer_round_blocksize, 209 1.1.2.2 skrll NULL, /* commit_setting */ 210 1.1.2.2 skrll NULL, /* init_output */ 211 1.1.2.2 skrll NULL, /* init_input */ 212 1.1.2.2 skrll NULL, /* start_output */ 213 1.1.2.2 skrll NULL, /* start_input */ 214 1.1.2.2 skrll auacer_halt_output, 215 1.1.2.2 skrll auacer_halt_input, 216 1.1.2.2 skrll NULL, /* speaker_ctl */ 217 1.1.2.2 skrll auacer_getdev, 218 1.1.2.2 skrll NULL, /* getfd */ 219 1.1.2.2 skrll auacer_set_port, 220 1.1.2.2 skrll auacer_get_port, 221 1.1.2.2 skrll auacer_query_devinfo, 222 1.1.2.2 skrll auacer_allocm, 223 1.1.2.2 skrll auacer_freem, 224 1.1.2.2 skrll auacer_round_buffersize, 225 1.1.2.2 skrll auacer_mappage, 226 1.1.2.2 skrll auacer_get_props, 227 1.1.2.2 skrll auacer_trigger_output, 228 1.1.2.2 skrll auacer_trigger_input, 229 1.1.2.2 skrll NULL, /* dev_ioctl */ 230 1.1.2.2 skrll }; 231 1.1.2.2 skrll 232 1.1.2.4 skrll #define AUACER_FORMATS_4CH 1 233 1.1.2.4 skrll #define AUACER_FORMATS_6CH 2 234 1.1.2.4 skrll static const struct audio_format auacer_formats[AUACER_NFORMATS] = { 235 1.1.2.4 skrll {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 236 1.1.2.4 skrll 2, AUFMT_STEREO, 0, {8000, 48000}}, 237 1.1.2.4 skrll {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 238 1.1.2.4 skrll 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 239 1.1.2.4 skrll {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 240 1.1.2.4 skrll 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 241 1.1.2.4 skrll }; 242 1.1.2.4 skrll 243 1.1.2.7 skrll static int auacer_attach_codec(void *, struct ac97_codec_if *); 244 1.1.2.7 skrll static int auacer_read_codec(void *, uint8_t, uint16_t *); 245 1.1.2.7 skrll static int auacer_write_codec(void *, uint8_t, uint16_t); 246 1.1.2.7 skrll static int auacer_reset_codec(void *); 247 1.1.2.2 skrll 248 1.1.2.7 skrll static int 249 1.1.2.2 skrll auacer_match(struct device *parent, struct cfdata *match, void *aux) 250 1.1.2.2 skrll { 251 1.1.2.5 skrll struct pci_attach_args *pa; 252 1.1.2.2 skrll 253 1.1.2.5 skrll pa = (struct pci_attach_args *)aux; 254 1.1.2.2 skrll if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 255 1.1.2.2 skrll PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M5455) 256 1.1.2.2 skrll return 1; 257 1.1.2.2 skrll return 0; 258 1.1.2.2 skrll } 259 1.1.2.2 skrll 260 1.1.2.7 skrll static void 261 1.1.2.2 skrll auacer_attach(struct device *parent, struct device *self, void *aux) 262 1.1.2.2 skrll { 263 1.1.2.5 skrll struct auacer_softc *sc; 264 1.1.2.5 skrll struct pci_attach_args *pa; 265 1.1.2.2 skrll pci_intr_handle_t ih; 266 1.1.2.2 skrll bus_size_t aud_size; 267 1.1.2.2 skrll pcireg_t v; 268 1.1.2.2 skrll const char *intrstr; 269 1.1.2.4 skrll int i; 270 1.1.2.2 skrll 271 1.1.2.5 skrll sc = (struct auacer_softc *)self; 272 1.1.2.5 skrll pa = aux; 273 1.1.2.2 skrll aprint_normal(": Acer Labs M5455 Audio controller\n"); 274 1.1.2.2 skrll 275 1.1.2.2 skrll if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, &sc->iot, 276 1.1.2.2 skrll &sc->aud_ioh, NULL, &aud_size)) { 277 1.1.2.2 skrll aprint_error(": can't map i/o space\n"); 278 1.1.2.2 skrll return; 279 1.1.2.2 skrll } 280 1.1.2.2 skrll 281 1.1.2.2 skrll sc->sc_pc = pa->pa_pc; 282 1.1.2.2 skrll sc->sc_pt = pa->pa_tag; 283 1.1.2.2 skrll sc->dmat = pa->pa_dmat; 284 1.1.2.2 skrll 285 1.1.2.2 skrll sc->sc_dmamap_flags = BUS_DMA_COHERENT; /* XXX remove */ 286 1.1.2.2 skrll 287 1.1.2.2 skrll /* enable bus mastering */ 288 1.1.2.2 skrll v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 289 1.1.2.2 skrll pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 290 1.1.2.2 skrll v | PCI_COMMAND_MASTER_ENABLE); 291 1.1.2.2 skrll 292 1.1.2.2 skrll /* Map and establish the interrupt. */ 293 1.1.2.2 skrll if (pci_intr_map(pa, &ih)) { 294 1.1.2.2 skrll aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 295 1.1.2.2 skrll return; 296 1.1.2.2 skrll } 297 1.1.2.2 skrll intrstr = pci_intr_string(pa->pa_pc, ih); 298 1.1.2.2 skrll sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 299 1.1.2.2 skrll auacer_intr, sc); 300 1.1.2.2 skrll if (sc->sc_ih == NULL) { 301 1.1.2.2 skrll aprint_error("%s: can't establish interrupt", 302 1.1.2.2 skrll sc->sc_dev.dv_xname); 303 1.1.2.2 skrll if (intrstr != NULL) 304 1.1.2.2 skrll aprint_normal(" at %s", intrstr); 305 1.1.2.2 skrll aprint_normal("\n"); 306 1.1.2.2 skrll return; 307 1.1.2.2 skrll } 308 1.1.2.2 skrll aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 309 1.1.2.2 skrll 310 1.1.2.2 skrll strlcpy(sc->sc_audev.name, "M5455 AC97", MAX_AUDIO_DEV_LEN); 311 1.1.2.2 skrll snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 312 1.1.2.2 skrll "0x%02x", PCI_REVISION(pa->pa_class)); 313 1.1.2.2 skrll strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 314 1.1.2.2 skrll 315 1.1.2.2 skrll /* Set up DMA lists. */ 316 1.1.2.2 skrll auacer_alloc_cdata(sc); 317 1.1.2.2 skrll sc->sc_pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 318 1.1.2.2 skrll sc->sc_pcmo.ptr = 0; 319 1.1.2.2 skrll sc->sc_pcmo.port = ALI_BASE_PO; 320 1.1.2.2 skrll 321 1.1.2.2 skrll DPRINTF(ALI_DEBUG_DMA, ("auacer_attach: lists %p\n", 322 1.1.2.2 skrll sc->sc_pcmo.dmalist)); 323 1.1.2.2 skrll 324 1.1.2.2 skrll sc->host_if.arg = sc; 325 1.1.2.2 skrll sc->host_if.attach = auacer_attach_codec; 326 1.1.2.2 skrll sc->host_if.read = auacer_read_codec; 327 1.1.2.2 skrll sc->host_if.write = auacer_write_codec; 328 1.1.2.2 skrll sc->host_if.reset = auacer_reset_codec; 329 1.1.2.2 skrll 330 1.1.2.5 skrll if (ac97_attach(&sc->host_if, self) != 0) 331 1.1.2.2 skrll return; 332 1.1.2.2 skrll 333 1.1.2.4 skrll /* setup audio_format */ 334 1.1.2.4 skrll memcpy(sc->sc_formats, auacer_formats, sizeof(auacer_formats)); 335 1.1.2.4 skrll if (!AC97_IS_4CH(sc->codec_if)) 336 1.1.2.4 skrll AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_4CH]); 337 1.1.2.4 skrll if (!AC97_IS_6CH(sc->codec_if)) 338 1.1.2.4 skrll AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_6CH]); 339 1.1.2.4 skrll if (AC97_IS_FIXED_RATE(sc->codec_if)) { 340 1.1.2.4 skrll for (i = 0; i < AUACER_NFORMATS; i++) { 341 1.1.2.4 skrll sc->sc_formats[i].frequency_type = 1; 342 1.1.2.4 skrll sc->sc_formats[i].frequency[0] = 48000; 343 1.1.2.4 skrll } 344 1.1.2.4 skrll } 345 1.1.2.4 skrll 346 1.1.2.4 skrll if (0 != auconv_create_encodings(sc->sc_formats, AUACER_NFORMATS, 347 1.1.2.4 skrll &sc->sc_encodings)) { 348 1.1.2.4 skrll return; 349 1.1.2.4 skrll } 350 1.1.2.4 skrll 351 1.1.2.2 skrll /* Watch for power change */ 352 1.1.2.2 skrll sc->sc_suspend = PWR_RESUME; 353 1.1.2.2 skrll sc->sc_powerhook = powerhook_establish(auacer_powerhook, sc); 354 1.1.2.2 skrll 355 1.1.2.2 skrll audio_attach_mi(&auacer_hw_if, sc, &sc->sc_dev); 356 1.1.2.2 skrll 357 1.1.2.2 skrll auacer_reset(sc); 358 1.1.2.2 skrll } 359 1.1.2.2 skrll 360 1.1.2.7 skrll CFATTACH_DECL(auacer, sizeof(struct auacer_softc), 361 1.1.2.7 skrll auacer_match, auacer_attach, NULL, NULL); 362 1.1.2.7 skrll 363 1.1.2.2 skrll static int 364 1.1.2.2 skrll auacer_ready_codec(struct auacer_softc *sc, int mask) 365 1.1.2.2 skrll { 366 1.1.2.5 skrll int count; 367 1.1.2.2 skrll 368 1.1.2.2 skrll for (count = 0; count < 0x7f; count++) { 369 1.1.2.2 skrll int val = READ1(sc, ALI_CSPSR); 370 1.1.2.2 skrll if (val & mask) 371 1.1.2.2 skrll return 0; 372 1.1.2.2 skrll } 373 1.1.2.2 skrll 374 1.1.2.2 skrll aprint_normal("auacer_ready_codec: AC97 codec ready timeout.\n"); 375 1.1.2.2 skrll return EBUSY; 376 1.1.2.2 skrll } 377 1.1.2.2 skrll 378 1.1.2.2 skrll static int 379 1.1.2.2 skrll auacer_sema_codec(struct auacer_softc *sc) 380 1.1.2.2 skrll { 381 1.1.2.7 skrll int ttime; 382 1.1.2.2 skrll 383 1.1.2.7 skrll ttime = 100; 384 1.1.2.7 skrll while (ttime-- && (READ4(sc, ALI_CAS) & ALI_CAS_SEM_BUSY)) 385 1.1.2.2 skrll delay(1); 386 1.1.2.7 skrll if (!ttime) 387 1.1.2.2 skrll aprint_normal("auacer_sema_codec: timeout\n"); 388 1.1.2.2 skrll return auacer_ready_codec(sc, ALI_CSPSR_CODEC_READY); 389 1.1.2.2 skrll } 390 1.1.2.2 skrll 391 1.1.2.7 skrll static int 392 1.1.2.5 skrll auacer_read_codec(void *v, uint8_t reg, uint16_t *val) 393 1.1.2.2 skrll { 394 1.1.2.5 skrll struct auacer_softc *sc; 395 1.1.2.2 skrll 396 1.1.2.5 skrll sc = v; 397 1.1.2.2 skrll if (auacer_sema_codec(sc)) 398 1.1.2.2 skrll return EIO; 399 1.1.2.2 skrll 400 1.1.2.2 skrll reg |= ALI_CPR_ADDR_READ; 401 1.1.2.2 skrll #if 0 402 1.1.2.2 skrll if (ac97->num) 403 1.1.2.2 skrll reg |= ALI_CPR_ADDR_SECONDARY; 404 1.1.2.2 skrll #endif 405 1.1.2.2 skrll WRITE2(sc, ALI_CPR_ADDR, reg); 406 1.1.2.2 skrll if (auacer_ready_codec(sc, ALI_CSPSR_READ_OK)) 407 1.1.2.2 skrll return EIO; 408 1.1.2.2 skrll *val = READ2(sc, ALI_SPR); 409 1.1.2.2 skrll 410 1.1.2.2 skrll DPRINTF(ALI_DEBUG_CODECIO, ("auacer_read_codec: reg=0x%x val=0x%x\n", 411 1.1.2.2 skrll reg, *val)); 412 1.1.2.2 skrll 413 1.1.2.2 skrll return 0; 414 1.1.2.2 skrll } 415 1.1.2.2 skrll 416 1.1.2.2 skrll int 417 1.1.2.5 skrll auacer_write_codec(void *v, uint8_t reg, uint16_t val) 418 1.1.2.2 skrll { 419 1.1.2.5 skrll struct auacer_softc *sc; 420 1.1.2.2 skrll 421 1.1.2.2 skrll DPRINTF(ALI_DEBUG_CODECIO, ("auacer_write_codec: reg=0x%x val=0x%x\n", 422 1.1.2.2 skrll reg, val)); 423 1.1.2.5 skrll sc = v; 424 1.1.2.2 skrll if (auacer_sema_codec(sc)) 425 1.1.2.2 skrll return EIO; 426 1.1.2.2 skrll WRITE2(sc, ALI_CPR, val); 427 1.1.2.2 skrll #if 0 428 1.1.2.2 skrll if (ac97->num) 429 1.1.2.2 skrll reg |= ALI_CPR_ADDR_SECONDARY; 430 1.1.2.2 skrll #endif 431 1.1.2.2 skrll WRITE2(sc, ALI_CPR_ADDR, reg); 432 1.1.2.2 skrll auacer_ready_codec(sc, ALI_CSPSR_WRITE_OK); 433 1.1.2.2 skrll return 0; 434 1.1.2.2 skrll } 435 1.1.2.2 skrll 436 1.1.2.7 skrll static int 437 1.1.2.2 skrll auacer_attach_codec(void *v, struct ac97_codec_if *cif) 438 1.1.2.2 skrll { 439 1.1.2.5 skrll struct auacer_softc *sc; 440 1.1.2.2 skrll 441 1.1.2.5 skrll sc = v; 442 1.1.2.2 skrll sc->codec_if = cif; 443 1.1.2.2 skrll return 0; 444 1.1.2.2 skrll } 445 1.1.2.2 skrll 446 1.1.2.7 skrll static int 447 1.1.2.2 skrll auacer_reset_codec(void *v) 448 1.1.2.2 skrll { 449 1.1.2.5 skrll struct auacer_softc *sc; 450 1.1.2.5 skrll uint32_t reg; 451 1.1.2.5 skrll int i; 452 1.1.2.2 skrll 453 1.1.2.5 skrll sc = v; 454 1.1.2.5 skrll i = 0; 455 1.1.2.2 skrll reg = READ4(sc, ALI_SCR); 456 1.1.2.2 skrll if ((reg & 2) == 0) /* Cold required */ 457 1.1.2.2 skrll reg |= 2; 458 1.1.2.2 skrll else 459 1.1.2.2 skrll reg |= 1; /* Warm */ 460 1.1.2.2 skrll reg &= ~0x80000000; /* ACLink on */ 461 1.1.2.2 skrll WRITE4(sc, ALI_SCR, reg); 462 1.1.2.2 skrll 463 1.1.2.2 skrll while (i < 10) { 464 1.1.2.2 skrll if ((READ4(sc, ALI_INTERRUPTSR) & ALI_INT_GPIO) == 0) 465 1.1.2.2 skrll break; 466 1.1.2.2 skrll delay(50000); /* XXX */ 467 1.1.2.2 skrll i++; 468 1.1.2.2 skrll } 469 1.1.2.2 skrll if (i == 10) { 470 1.1.2.2 skrll return EIO; 471 1.1.2.2 skrll } 472 1.1.2.2 skrll 473 1.1.2.2 skrll for (i = 0; i < 10; i++) { 474 1.1.2.2 skrll reg = READ4(sc, ALI_RTSR); 475 1.1.2.2 skrll if (reg & 0x80) /* primary codec */ 476 1.1.2.2 skrll break; 477 1.1.2.2 skrll WRITE4(sc, ALI_RTSR, reg | 0x80); 478 1.1.2.2 skrll delay(50000); /* XXX */ 479 1.1.2.2 skrll } 480 1.1.2.2 skrll 481 1.1.2.2 skrll return 0; 482 1.1.2.2 skrll } 483 1.1.2.2 skrll 484 1.1.2.2 skrll static void 485 1.1.2.2 skrll auacer_reset(struct auacer_softc *sc) 486 1.1.2.2 skrll { 487 1.1.2.2 skrll WRITE4(sc, ALI_SCR, ALI_SCR_RESET); 488 1.1.2.2 skrll WRITE4(sc, ALI_FIFOCR1, 0x83838383); 489 1.1.2.2 skrll WRITE4(sc, ALI_FIFOCR2, 0x83838383); 490 1.1.2.2 skrll WRITE4(sc, ALI_FIFOCR3, 0x83838383); 491 1.1.2.2 skrll WRITE4(sc, ALI_INTERFACECR, ALI_IF_PO); /* XXX pcm out only */ 492 1.1.2.2 skrll WRITE4(sc, ALI_INTERRUPTCR, 0x00000000); 493 1.1.2.2 skrll WRITE4(sc, ALI_INTERRUPTSR, 0x00000000); 494 1.1.2.2 skrll } 495 1.1.2.2 skrll 496 1.1.2.7 skrll static int 497 1.1.2.2 skrll auacer_query_encoding(void *v, struct audio_encoding *aep) 498 1.1.2.2 skrll { 499 1.1.2.4 skrll struct auacer_softc *sc; 500 1.1.2.2 skrll 501 1.1.2.4 skrll DPRINTF(ALI_DEBUG_API, ("auacer_query_encoding\n")); 502 1.1.2.4 skrll sc = v; 503 1.1.2.4 skrll return auconv_query_encoding(sc->sc_encodings, aep); 504 1.1.2.2 skrll } 505 1.1.2.2 skrll 506 1.1.2.7 skrll static int 507 1.1.2.5 skrll auacer_set_rate(struct auacer_softc *sc, int mode, u_int srate) 508 1.1.2.2 skrll { 509 1.1.2.2 skrll int ret; 510 1.1.2.5 skrll u_int ratetmp; 511 1.1.2.2 skrll 512 1.1.2.6 skrll DPRINTF(ALI_DEBUG_API, ("auacer_set_rate: srate=%u\n", srate)); 513 1.1.2.2 skrll 514 1.1.2.2 skrll ratetmp = srate; 515 1.1.2.2 skrll if (mode == AUMODE_RECORD) 516 1.1.2.2 skrll return sc->codec_if->vtbl->set_rate(sc->codec_if, 517 1.1.2.2 skrll AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 518 1.1.2.2 skrll ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 519 1.1.2.2 skrll AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 520 1.1.2.2 skrll if (ret) 521 1.1.2.2 skrll return ret; 522 1.1.2.2 skrll ratetmp = srate; 523 1.1.2.2 skrll ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 524 1.1.2.2 skrll AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 525 1.1.2.2 skrll if (ret) 526 1.1.2.2 skrll return ret; 527 1.1.2.2 skrll ratetmp = srate; 528 1.1.2.2 skrll ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 529 1.1.2.2 skrll AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 530 1.1.2.2 skrll return ret; 531 1.1.2.2 skrll } 532 1.1.2.2 skrll 533 1.1.2.7 skrll static int 534 1.1.2.5 skrll auacer_set_params(void *v, int setmode, int usemode, audio_params_t *play, 535 1.1.2.5 skrll audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 536 1.1.2.2 skrll { 537 1.1.2.5 skrll struct auacer_softc *sc; 538 1.1.2.2 skrll struct audio_params *p; 539 1.1.2.5 skrll stream_filter_list_t *fil; 540 1.1.2.2 skrll uint32_t control; 541 1.1.2.4 skrll int mode, index; 542 1.1.2.2 skrll 543 1.1.2.2 skrll DPRINTF(ALI_DEBUG_API, ("auacer_set_params\n")); 544 1.1.2.5 skrll sc = v; 545 1.1.2.2 skrll for (mode = AUMODE_RECORD; mode != -1; 546 1.1.2.2 skrll mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 547 1.1.2.2 skrll if ((setmode & mode) == 0) 548 1.1.2.2 skrll continue; 549 1.1.2.2 skrll 550 1.1.2.2 skrll p = mode == AUMODE_PLAY ? play : rec; 551 1.1.2.2 skrll if (p == NULL) 552 1.1.2.2 skrll continue; 553 1.1.2.2 skrll 554 1.1.2.2 skrll if ((p->sample_rate != 8000) && 555 1.1.2.2 skrll (p->sample_rate != 11025) && 556 1.1.2.2 skrll (p->sample_rate != 12000) && 557 1.1.2.2 skrll (p->sample_rate != 16000) && 558 1.1.2.2 skrll (p->sample_rate != 22050) && 559 1.1.2.2 skrll (p->sample_rate != 24000) && 560 1.1.2.2 skrll (p->sample_rate != 32000) && 561 1.1.2.2 skrll (p->sample_rate != 44100) && 562 1.1.2.2 skrll (p->sample_rate != 48000)) 563 1.1.2.2 skrll return (EINVAL); 564 1.1.2.2 skrll 565 1.1.2.5 skrll fil = mode == AUMODE_PLAY ? pfil : rfil; 566 1.1.2.4 skrll index = auconv_set_converter(sc->sc_formats, AUACER_NFORMATS, 567 1.1.2.5 skrll mode, p, TRUE, fil); 568 1.1.2.4 skrll if (index < 0) 569 1.1.2.4 skrll return EINVAL; 570 1.1.2.5 skrll if (fil->req_size > 0) 571 1.1.2.5 skrll p = &fil->filters[0].param; 572 1.1.2.5 skrll /* p points HW encoding */ 573 1.1.2.4 skrll if (sc->sc_formats[index].frequency_type != 1 574 1.1.2.5 skrll && auacer_set_rate(sc, mode, p->sample_rate)) 575 1.1.2.4 skrll return EINVAL; 576 1.1.2.2 skrll if (mode == AUMODE_PLAY) { 577 1.1.2.2 skrll control = READ4(sc, ALI_SCR); 578 1.1.2.2 skrll control &= ~ALI_SCR_PCM_246_MASK; 579 1.1.2.2 skrll if (p->channels == 4) 580 1.1.2.2 skrll control |= ALI_SCR_PCM_4; 581 1.1.2.2 skrll else if (p->channels == 6) 582 1.1.2.2 skrll control |= ALI_SCR_PCM_6; 583 1.1.2.2 skrll WRITE4(sc, ALI_SCR, control); 584 1.1.2.2 skrll } 585 1.1.2.2 skrll } 586 1.1.2.2 skrll 587 1.1.2.2 skrll return (0); 588 1.1.2.2 skrll } 589 1.1.2.2 skrll 590 1.1.2.7 skrll static int 591 1.1.2.5 skrll auacer_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 592 1.1.2.2 skrll { 593 1.1.2.2 skrll 594 1.1.2.5 skrll return blk & ~0x3f; /* keep good alignment */ 595 1.1.2.2 skrll } 596 1.1.2.2 skrll 597 1.1.2.2 skrll static void 598 1.1.2.2 skrll auacer_halt(struct auacer_softc *sc, struct auacer_chan *chan) 599 1.1.2.2 skrll { 600 1.1.2.2 skrll uint32_t val; 601 1.1.2.5 skrll uint8_t port; 602 1.1.2.2 skrll uint32_t slot; 603 1.1.2.2 skrll 604 1.1.2.5 skrll port = chan->port; 605 1.1.2.2 skrll DPRINTF(ALI_DEBUG_API, ("auacer_halt: port=0x%x\n", port)); 606 1.1.2.2 skrll chan->intr = 0; 607 1.1.2.2 skrll 608 1.1.2.2 skrll slot = ALI_PORT2SLOT(port); 609 1.1.2.2 skrll 610 1.1.2.2 skrll val = READ4(sc, ALI_DMACR); 611 1.1.2.2 skrll val |= 1 << (slot+16); /* pause */ 612 1.1.2.2 skrll val &= ~(1 << slot); /* no start */ 613 1.1.2.2 skrll WRITE4(sc, ALI_DMACR, val); 614 1.1.2.2 skrll WRITE1(sc, port + ALI_OFF_CR, 0); 615 1.1.2.2 skrll while (READ1(sc, port + ALI_OFF_CR)) 616 1.1.2.2 skrll ; 617 1.1.2.2 skrll /* reset whole DMA things */ 618 1.1.2.2 skrll WRITE1(sc, port + ALI_OFF_CR, ALI_CR_RR); 619 1.1.2.2 skrll /* clear interrupts */ 620 1.1.2.2 skrll WRITE1(sc, port + ALI_OFF_SR, READ1(sc, port+ALI_OFF_SR) | ALI_SR_W1TC); 621 1.1.2.2 skrll WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(port)); 622 1.1.2.2 skrll } 623 1.1.2.2 skrll 624 1.1.2.7 skrll static int 625 1.1.2.2 skrll auacer_halt_output(void *v) 626 1.1.2.2 skrll { 627 1.1.2.5 skrll struct auacer_softc *sc; 628 1.1.2.2 skrll 629 1.1.2.2 skrll DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_output\n")); 630 1.1.2.5 skrll sc = v; 631 1.1.2.2 skrll auacer_halt(sc, &sc->sc_pcmo); 632 1.1.2.2 skrll 633 1.1.2.5 skrll return 0; 634 1.1.2.2 skrll } 635 1.1.2.2 skrll 636 1.1.2.7 skrll static int 637 1.1.2.2 skrll auacer_halt_input(void *v) 638 1.1.2.2 skrll { 639 1.1.2.2 skrll /*struct auacer_softc *sc = v;*/ 640 1.1.2.2 skrll 641 1.1.2.2 skrll DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_input\n")); 642 1.1.2.2 skrll 643 1.1.2.5 skrll return 0; 644 1.1.2.2 skrll } 645 1.1.2.2 skrll 646 1.1.2.7 skrll static int 647 1.1.2.2 skrll auacer_getdev(void *v, struct audio_device *adp) 648 1.1.2.2 skrll { 649 1.1.2.5 skrll struct auacer_softc *sc; 650 1.1.2.2 skrll 651 1.1.2.2 skrll DPRINTF(ALI_DEBUG_API, ("auacer_getdev\n")); 652 1.1.2.5 skrll sc = v; 653 1.1.2.2 skrll *adp = sc->sc_audev; 654 1.1.2.5 skrll return 0; 655 1.1.2.2 skrll } 656 1.1.2.2 skrll 657 1.1.2.7 skrll static int 658 1.1.2.2 skrll auacer_set_port(void *v, mixer_ctrl_t *cp) 659 1.1.2.2 skrll { 660 1.1.2.5 skrll struct auacer_softc *sc; 661 1.1.2.2 skrll 662 1.1.2.2 skrll DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_set_port\n")); 663 1.1.2.5 skrll sc = v; 664 1.1.2.5 skrll return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 665 1.1.2.2 skrll } 666 1.1.2.2 skrll 667 1.1.2.7 skrll static int 668 1.1.2.2 skrll auacer_get_port(void *v, mixer_ctrl_t *cp) 669 1.1.2.2 skrll { 670 1.1.2.5 skrll struct auacer_softc *sc; 671 1.1.2.2 skrll 672 1.1.2.2 skrll DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_get_port\n")); 673 1.1.2.5 skrll sc = v; 674 1.1.2.5 skrll return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 675 1.1.2.2 skrll } 676 1.1.2.2 skrll 677 1.1.2.7 skrll static int 678 1.1.2.2 skrll auacer_query_devinfo(void *v, mixer_devinfo_t *dp) 679 1.1.2.2 skrll { 680 1.1.2.5 skrll struct auacer_softc *sc; 681 1.1.2.2 skrll 682 1.1.2.2 skrll DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_query_devinfo\n")); 683 1.1.2.5 skrll sc = v; 684 1.1.2.5 skrll return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 685 1.1.2.2 skrll } 686 1.1.2.2 skrll 687 1.1.2.7 skrll static void * 688 1.1.2.2 skrll auacer_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 689 1.1.2.2 skrll int flags) 690 1.1.2.2 skrll { 691 1.1.2.5 skrll struct auacer_softc *sc; 692 1.1.2.2 skrll struct auacer_dma *p; 693 1.1.2.2 skrll int error; 694 1.1.2.2 skrll 695 1.1.2.2 skrll if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX)) 696 1.1.2.5 skrll return NULL; 697 1.1.2.2 skrll 698 1.1.2.2 skrll p = malloc(sizeof(*p), pool, flags | M_ZERO); 699 1.1.2.2 skrll if (p == NULL) 700 1.1.2.5 skrll return NULL; 701 1.1.2.5 skrll sc = v; 702 1.1.2.2 skrll error = auacer_allocmem(sc, size, 0, p); 703 1.1.2.2 skrll if (error) { 704 1.1.2.2 skrll free(p, pool); 705 1.1.2.5 skrll return NULL; 706 1.1.2.2 skrll } 707 1.1.2.2 skrll 708 1.1.2.2 skrll p->next = sc->sc_dmas; 709 1.1.2.2 skrll sc->sc_dmas = p; 710 1.1.2.2 skrll 711 1.1.2.5 skrll return KERNADDR(p); 712 1.1.2.2 skrll } 713 1.1.2.2 skrll 714 1.1.2.7 skrll static void 715 1.1.2.2 skrll auacer_freem(void *v, void *ptr, struct malloc_type *pool) 716 1.1.2.2 skrll { 717 1.1.2.5 skrll struct auacer_softc *sc; 718 1.1.2.2 skrll struct auacer_dma *p, **pp; 719 1.1.2.2 skrll 720 1.1.2.5 skrll sc = v; 721 1.1.2.2 skrll for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 722 1.1.2.2 skrll if (KERNADDR(p) == ptr) { 723 1.1.2.2 skrll auacer_freemem(sc, p); 724 1.1.2.2 skrll *pp = p->next; 725 1.1.2.2 skrll free(p, pool); 726 1.1.2.2 skrll return; 727 1.1.2.2 skrll } 728 1.1.2.2 skrll } 729 1.1.2.2 skrll } 730 1.1.2.2 skrll 731 1.1.2.7 skrll static size_t 732 1.1.2.2 skrll auacer_round_buffersize(void *v, int direction, size_t size) 733 1.1.2.2 skrll { 734 1.1.2.2 skrll 735 1.1.2.2 skrll if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX)) 736 1.1.2.2 skrll size = ALI_DMALIST_MAX * ALI_DMASEG_MAX; 737 1.1.2.2 skrll 738 1.1.2.2 skrll return size; 739 1.1.2.2 skrll } 740 1.1.2.2 skrll 741 1.1.2.7 skrll static paddr_t 742 1.1.2.2 skrll auacer_mappage(void *v, void *mem, off_t off, int prot) 743 1.1.2.2 skrll { 744 1.1.2.5 skrll struct auacer_softc *sc; 745 1.1.2.2 skrll struct auacer_dma *p; 746 1.1.2.2 skrll 747 1.1.2.2 skrll if (off < 0) 748 1.1.2.5 skrll return -1; 749 1.1.2.5 skrll sc = v; 750 1.1.2.2 skrll for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 751 1.1.2.5 skrll continue; 752 1.1.2.5 skrll if (p == NULL) 753 1.1.2.5 skrll return -1; 754 1.1.2.5 skrll return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 755 1.1.2.5 skrll off, prot, BUS_DMA_WAITOK); 756 1.1.2.2 skrll } 757 1.1.2.2 skrll 758 1.1.2.7 skrll static int 759 1.1.2.2 skrll auacer_get_props(void *v) 760 1.1.2.2 skrll { 761 1.1.2.5 skrll struct auacer_softc *sc; 762 1.1.2.2 skrll int props; 763 1.1.2.2 skrll 764 1.1.2.5 skrll sc = v; 765 1.1.2.2 skrll props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 766 1.1.2.2 skrll /* 767 1.1.2.2 skrll * Even if the codec is fixed-rate, set_param() succeeds for any sample 768 1.1.2.2 skrll * rate because of aurateconv. Applications can't know what rate the 769 1.1.2.2 skrll * device can process in the case of mmap(). 770 1.1.2.2 skrll */ 771 1.1.2.3 skrll if (!AC97_IS_FIXED_RATE(sc->codec_if)) 772 1.1.2.2 skrll props |= AUDIO_PROP_MMAP; 773 1.1.2.2 skrll return props; 774 1.1.2.2 skrll } 775 1.1.2.2 skrll 776 1.1.2.2 skrll static void 777 1.1.2.2 skrll auacer_add_entry(struct auacer_chan *chan) 778 1.1.2.2 skrll { 779 1.1.2.2 skrll struct auacer_dmalist *q; 780 1.1.2.2 skrll 781 1.1.2.2 skrll q = &chan->dmalist[chan->ptr]; 782 1.1.2.2 skrll 783 1.1.2.2 skrll DPRINTF(ALI_DEBUG_INTR, 784 1.1.2.2 skrll ("auacer_add_entry: %p = %x @ 0x%x\n", 785 1.1.2.2 skrll q, chan->blksize / 2, chan->p)); 786 1.1.2.2 skrll 787 1.1.2.2 skrll q->base = htole32(chan->p); 788 1.1.2.2 skrll q->len = htole32((chan->blksize / ALI_SAMPLE_SIZE) | ALI_DMAF_IOC); 789 1.1.2.2 skrll chan->p += chan->blksize; 790 1.1.2.2 skrll if (chan->p >= chan->end) 791 1.1.2.2 skrll chan->p = chan->start; 792 1.1.2.5 skrll 793 1.1.2.2 skrll if (++chan->ptr >= ALI_DMALIST_MAX) 794 1.1.2.2 skrll chan->ptr = 0; 795 1.1.2.2 skrll } 796 1.1.2.2 skrll 797 1.1.2.2 skrll static void 798 1.1.2.2 skrll auacer_upd_chan(struct auacer_softc *sc, struct auacer_chan *chan) 799 1.1.2.2 skrll { 800 1.1.2.2 skrll uint32_t sts; 801 1.1.2.2 skrll uint32_t civ; 802 1.1.2.2 skrll 803 1.1.2.2 skrll sts = READ2(sc, chan->port + ALI_OFF_SR); 804 1.1.2.2 skrll /* intr ack */ 805 1.1.2.2 skrll WRITE2(sc, chan->port + ALI_OFF_SR, sts & ALI_SR_W1TC); 806 1.1.2.2 skrll WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(chan->port)); 807 1.1.2.2 skrll 808 1.1.2.2 skrll DPRINTF(ALI_DEBUG_INTR, ("auacer_upd_chan: sts=0x%x\n", sts)); 809 1.1.2.2 skrll 810 1.1.2.2 skrll if (sts & ALI_SR_DMA_INT_FIFO) { 811 1.1.2.2 skrll printf("%s: fifo underrun # %u\n", 812 1.1.2.2 skrll sc->sc_dev.dv_xname, ++chan->fifoe); 813 1.1.2.2 skrll } 814 1.1.2.2 skrll 815 1.1.2.2 skrll civ = READ1(sc, chan->port + ALI_OFF_CIV); 816 1.1.2.5 skrll 817 1.1.2.2 skrll DPRINTF(ALI_DEBUG_INTR,("auacer_intr: civ=%u ptr=%u\n",civ,chan->ptr)); 818 1.1.2.5 skrll 819 1.1.2.2 skrll /* XXX */ 820 1.1.2.2 skrll while (chan->ptr != civ) { 821 1.1.2.2 skrll auacer_add_entry(chan); 822 1.1.2.2 skrll } 823 1.1.2.2 skrll 824 1.1.2.2 skrll WRITE1(sc, chan->port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK); 825 1.1.2.2 skrll 826 1.1.2.2 skrll while (chan->ack != civ) { 827 1.1.2.2 skrll if (chan->intr) { 828 1.1.2.2 skrll DPRINTF(ALI_DEBUG_INTR,("auacer_upd_chan: callback\n")); 829 1.1.2.2 skrll chan->intr(chan->arg); 830 1.1.2.2 skrll } 831 1.1.2.2 skrll chan->ack++; 832 1.1.2.2 skrll if (chan->ack >= ALI_DMALIST_MAX) 833 1.1.2.2 skrll chan->ack = 0; 834 1.1.2.2 skrll } 835 1.1.2.2 skrll } 836 1.1.2.2 skrll 837 1.1.2.7 skrll static int 838 1.1.2.2 skrll auacer_intr(void *v) 839 1.1.2.2 skrll { 840 1.1.2.5 skrll struct auacer_softc *sc; 841 1.1.2.2 skrll int ret, intrs; 842 1.1.2.2 skrll 843 1.1.2.5 skrll sc = v; 844 1.1.2.2 skrll intrs = READ4(sc, ALI_INTERRUPTSR); 845 1.1.2.2 skrll DPRINTF(ALI_DEBUG_INTR, ("auacer_intr: intrs=0x%x\n", intrs)); 846 1.1.2.2 skrll 847 1.1.2.2 skrll ret = 0; 848 1.1.2.2 skrll if (intrs & ALI_INT_PCMOUT) { 849 1.1.2.2 skrll auacer_upd_chan(sc, &sc->sc_pcmo); 850 1.1.2.2 skrll ret++; 851 1.1.2.2 skrll } 852 1.1.2.2 skrll 853 1.1.2.2 skrll return ret != 0; 854 1.1.2.2 skrll } 855 1.1.2.2 skrll 856 1.1.2.2 skrll static void 857 1.1.2.2 skrll auacer_setup_chan(struct auacer_softc *sc, struct auacer_chan *chan, 858 1.1.2.2 skrll uint32_t start, uint32_t size, uint32_t blksize, 859 1.1.2.2 skrll void (*intr)(void *), void *arg) 860 1.1.2.2 skrll { 861 1.1.2.2 skrll uint32_t port, slot; 862 1.1.2.2 skrll uint32_t offs, val; 863 1.1.2.2 skrll 864 1.1.2.2 skrll chan->start = start; 865 1.1.2.2 skrll chan->ptr = 0; 866 1.1.2.2 skrll chan->p = chan->start; 867 1.1.2.2 skrll chan->end = chan->start + size; 868 1.1.2.2 skrll chan->blksize = blksize; 869 1.1.2.2 skrll chan->ack = 0; 870 1.1.2.2 skrll chan->intr = intr; 871 1.1.2.2 skrll chan->arg = arg; 872 1.1.2.2 skrll 873 1.1.2.2 skrll auacer_add_entry(chan); 874 1.1.2.2 skrll auacer_add_entry(chan); 875 1.1.2.2 skrll 876 1.1.2.2 skrll port = chan->port; 877 1.1.2.2 skrll slot = ALI_PORT2SLOT(port); 878 1.1.2.2 skrll 879 1.1.2.2 skrll WRITE1(sc, port + ALI_OFF_CIV, 0); 880 1.1.2.2 skrll WRITE1(sc, port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK); 881 1.1.2.2 skrll offs = (char *)chan->dmalist - (char *)sc->sc_cdata; 882 1.1.2.2 skrll WRITE4(sc, port + ALI_OFF_BDBAR, sc->sc_cddma + offs); 883 1.1.2.2 skrll WRITE1(sc, port + ALI_OFF_CR, 884 1.1.2.2 skrll ALI_CR_IOCE | ALI_CR_FEIE | ALI_CR_LVBIE | ALI_CR_RPBM); 885 1.1.2.2 skrll val = READ4(sc, ALI_DMACR); 886 1.1.2.2 skrll val &= ~(1 << (slot+16)); /* no pause */ 887 1.1.2.2 skrll val |= 1 << slot; /* start */ 888 1.1.2.2 skrll WRITE4(sc, ALI_DMACR, val); 889 1.1.2.2 skrll } 890 1.1.2.2 skrll 891 1.1.2.7 skrll static int 892 1.1.2.2 skrll auacer_trigger_output(void *v, void *start, void *end, int blksize, 893 1.1.2.5 skrll void (*intr)(void *), void *arg, const audio_params_t *param) 894 1.1.2.2 skrll { 895 1.1.2.5 skrll struct auacer_softc *sc; 896 1.1.2.2 skrll struct auacer_dma *p; 897 1.1.2.2 skrll uint32_t size; 898 1.1.2.2 skrll 899 1.1.2.2 skrll DPRINTF(ALI_DEBUG_DMA, 900 1.1.2.2 skrll ("auacer_trigger_output(%p, %p, %d, %p, %p, %p)\n", 901 1.1.2.2 skrll start, end, blksize, intr, arg, param)); 902 1.1.2.5 skrll sc = v; 903 1.1.2.2 skrll for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 904 1.1.2.5 skrll continue; 905 1.1.2.2 skrll if (!p) { 906 1.1.2.2 skrll printf("auacer_trigger_output: bad addr %p\n", start); 907 1.1.2.2 skrll return (EINVAL); 908 1.1.2.2 skrll } 909 1.1.2.2 skrll 910 1.1.2.2 skrll size = (char *)end - (char *)start; 911 1.1.2.2 skrll auacer_setup_chan(sc, &sc->sc_pcmo, DMAADDR(p), size, blksize, 912 1.1.2.2 skrll intr, arg); 913 1.1.2.2 skrll 914 1.1.2.2 skrll return 0; 915 1.1.2.2 skrll } 916 1.1.2.2 skrll 917 1.1.2.7 skrll static int 918 1.1.2.2 skrll auacer_trigger_input(void *v, void *start, void *end, int blksize, 919 1.1.2.2 skrll void (*intr)(void *), void *arg, 920 1.1.2.5 skrll const audio_params_t *param) 921 1.1.2.2 skrll { 922 1.1.2.5 skrll return EINVAL; 923 1.1.2.2 skrll } 924 1.1.2.2 skrll 925 1.1.2.7 skrll static int 926 1.1.2.2 skrll auacer_allocmem(struct auacer_softc *sc, size_t size, size_t align, 927 1.1.2.2 skrll struct auacer_dma *p) 928 1.1.2.2 skrll { 929 1.1.2.2 skrll int error; 930 1.1.2.2 skrll 931 1.1.2.2 skrll p->size = size; 932 1.1.2.2 skrll error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 933 1.1.2.2 skrll p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 934 1.1.2.2 skrll &p->nsegs, BUS_DMA_NOWAIT); 935 1.1.2.2 skrll if (error) 936 1.1.2.5 skrll return error; 937 1.1.2.2 skrll 938 1.1.2.2 skrll error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 939 1.1.2.2 skrll &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 940 1.1.2.2 skrll if (error) 941 1.1.2.2 skrll goto free; 942 1.1.2.2 skrll 943 1.1.2.2 skrll error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 944 1.1.2.2 skrll 0, BUS_DMA_NOWAIT, &p->map); 945 1.1.2.2 skrll if (error) 946 1.1.2.2 skrll goto unmap; 947 1.1.2.2 skrll 948 1.1.2.2 skrll error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 949 1.1.2.2 skrll BUS_DMA_NOWAIT); 950 1.1.2.2 skrll if (error) 951 1.1.2.2 skrll goto destroy; 952 1.1.2.2 skrll return (0); 953 1.1.2.2 skrll 954 1.1.2.2 skrll destroy: 955 1.1.2.2 skrll bus_dmamap_destroy(sc->dmat, p->map); 956 1.1.2.2 skrll unmap: 957 1.1.2.2 skrll bus_dmamem_unmap(sc->dmat, p->addr, p->size); 958 1.1.2.2 skrll free: 959 1.1.2.2 skrll bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 960 1.1.2.5 skrll return error; 961 1.1.2.2 skrll } 962 1.1.2.2 skrll 963 1.1.2.7 skrll static int 964 1.1.2.2 skrll auacer_freemem(struct auacer_softc *sc, struct auacer_dma *p) 965 1.1.2.2 skrll { 966 1.1.2.2 skrll 967 1.1.2.2 skrll bus_dmamap_unload(sc->dmat, p->map); 968 1.1.2.2 skrll bus_dmamap_destroy(sc->dmat, p->map); 969 1.1.2.2 skrll bus_dmamem_unmap(sc->dmat, p->addr, p->size); 970 1.1.2.2 skrll bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 971 1.1.2.5 skrll return 0; 972 1.1.2.2 skrll } 973 1.1.2.2 skrll 974 1.1.2.7 skrll static int 975 1.1.2.2 skrll auacer_alloc_cdata(struct auacer_softc *sc) 976 1.1.2.2 skrll { 977 1.1.2.2 skrll bus_dma_segment_t seg; 978 1.1.2.2 skrll int error, rseg; 979 1.1.2.2 skrll 980 1.1.2.2 skrll /* 981 1.1.2.2 skrll * Allocate the control data structure, and create and load the 982 1.1.2.2 skrll * DMA map for it. 983 1.1.2.2 skrll */ 984 1.1.2.2 skrll if ((error = bus_dmamem_alloc(sc->dmat, 985 1.1.2.2 skrll sizeof(struct auacer_cdata), 986 1.1.2.2 skrll PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 987 1.1.2.2 skrll printf("%s: unable to allocate control data, error = %d\n", 988 1.1.2.2 skrll sc->sc_dev.dv_xname, error); 989 1.1.2.2 skrll goto fail_0; 990 1.1.2.2 skrll } 991 1.1.2.2 skrll 992 1.1.2.2 skrll if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 993 1.1.2.2 skrll sizeof(struct auacer_cdata), 994 1.1.2.2 skrll (caddr_t *) &sc->sc_cdata, 995 1.1.2.2 skrll sc->sc_dmamap_flags)) != 0) { 996 1.1.2.2 skrll printf("%s: unable to map control data, error = %d\n", 997 1.1.2.2 skrll sc->sc_dev.dv_xname, error); 998 1.1.2.2 skrll goto fail_1; 999 1.1.2.2 skrll } 1000 1.1.2.2 skrll 1001 1.1.2.2 skrll if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auacer_cdata), 1, 1002 1.1.2.2 skrll sizeof(struct auacer_cdata), 0, 0, 1003 1.1.2.2 skrll &sc->sc_cddmamap)) != 0) { 1004 1.1.2.2 skrll printf("%s: unable to create control data DMA map, " 1005 1.1.2.2 skrll "error = %d\n", sc->sc_dev.dv_xname, error); 1006 1.1.2.2 skrll goto fail_2; 1007 1.1.2.2 skrll } 1008 1.1.2.2 skrll 1009 1.1.2.2 skrll if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1010 1.1.2.2 skrll sc->sc_cdata, sizeof(struct auacer_cdata), 1011 1.1.2.2 skrll NULL, 0)) != 0) { 1012 1.1.2.4 skrll printf("%s: unable to load control data DMA map, " 1013 1.1.2.2 skrll "error = %d\n", sc->sc_dev.dv_xname, error); 1014 1.1.2.2 skrll goto fail_3; 1015 1.1.2.2 skrll } 1016 1.1.2.2 skrll 1017 1.1.2.5 skrll return 0; 1018 1.1.2.2 skrll 1019 1.1.2.2 skrll fail_3: 1020 1.1.2.2 skrll bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1021 1.1.2.2 skrll fail_2: 1022 1.1.2.2 skrll bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1023 1.1.2.2 skrll sizeof(struct auacer_cdata)); 1024 1.1.2.2 skrll fail_1: 1025 1.1.2.2 skrll bus_dmamem_free(sc->dmat, &seg, rseg); 1026 1.1.2.2 skrll fail_0: 1027 1.1.2.5 skrll return error; 1028 1.1.2.2 skrll } 1029 1.1.2.2 skrll 1030 1.1.2.7 skrll static void 1031 1.1.2.2 skrll auacer_powerhook(int why, void *addr) 1032 1.1.2.2 skrll { 1033 1.1.2.5 skrll struct auacer_softc *sc; 1034 1.1.2.2 skrll 1035 1.1.2.5 skrll sc = (struct auacer_softc *)addr; 1036 1.1.2.2 skrll switch (why) { 1037 1.1.2.2 skrll case PWR_SUSPEND: 1038 1.1.2.2 skrll case PWR_STANDBY: 1039 1.1.2.2 skrll /* Power down */ 1040 1.1.2.2 skrll DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1041 1.1.2.2 skrll sc->sc_suspend = why; 1042 1.1.2.2 skrll break; 1043 1.1.2.2 skrll 1044 1.1.2.2 skrll case PWR_RESUME: 1045 1.1.2.2 skrll /* Wake up */ 1046 1.1.2.2 skrll DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1047 1.1.2.2 skrll if (sc->sc_suspend == PWR_RESUME) { 1048 1.1.2.2 skrll printf("%s: resume without suspend.\n", 1049 1.1.2.2 skrll sc->sc_dev.dv_xname); 1050 1.1.2.2 skrll sc->sc_suspend = why; 1051 1.1.2.2 skrll return; 1052 1.1.2.2 skrll } 1053 1.1.2.2 skrll sc->sc_suspend = why; 1054 1.1.2.2 skrll auacer_reset_codec(sc); 1055 1.1.2.2 skrll delay(1000); 1056 1.1.2.2 skrll sc->codec_if->vtbl->restore_ports(sc->codec_if); 1057 1.1.2.2 skrll break; 1058 1.1.2.2 skrll 1059 1.1.2.2 skrll case PWR_SOFTSUSPEND: 1060 1.1.2.2 skrll case PWR_SOFTSTANDBY: 1061 1.1.2.2 skrll case PWR_SOFTRESUME: 1062 1.1.2.2 skrll break; 1063 1.1.2.2 skrll } 1064 1.1.2.2 skrll } 1065
Indexes created Sat Nov 01 05:10:12 GMT 2025