auacer.c revision 1.30 1 1.30 mrg /* $NetBSD: auacer.c,v 1.30 2011/11/24 03:35:58 mrg Exp $ */
2 1.1 augustss
3 1.1 augustss /*-
4 1.29 jmcneill * Copyright (c) 2004, 2008 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.1 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.1 augustss * by Lennart Augustsson.
9 1.1 augustss *
10 1.1 augustss * Redistribution and use in source and binary forms, with or without
11 1.1 augustss * modification, are permitted provided that the following conditions
12 1.1 augustss * are met:
13 1.1 augustss * 1. Redistributions of source code must retain the above copyright
14 1.1 augustss * notice, this list of conditions and the following disclaimer.
15 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 augustss * notice, this list of conditions and the following disclaimer in the
17 1.1 augustss * documentation and/or other materials provided with the distribution.
18 1.1 augustss *
19 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
30 1.1 augustss */
31 1.1 augustss
32 1.1 augustss /*
33 1.1 augustss * Acer Labs M5455 audio driver
34 1.1 augustss *
35 1.5 augustss * Acer provides data sheets after signing an NDA, so this is guess work.
36 1.1 augustss * The chip behaves somewhat like the Intel i8x0, so this driver
37 1.1 augustss * is loosely based on the auich driver. Additional information taken from
38 1.1 augustss * the ALSA intel8x0.c driver (which handles M5455 as well).
39 1.1 augustss *
40 1.1 augustss * As an historical note one can observe that the auich driver borrows
41 1.1 augustss * lot from the first NetBSD PCI audio driver, the eap driver. But this
42 1.1 augustss * is not attributed anywhere.
43 1.1 augustss */
44 1.1 augustss
45 1.1 augustss
46 1.1 augustss #include <sys/cdefs.h>
47 1.30 mrg __KERNEL_RCSID(0, "$NetBSD: auacer.c,v 1.30 2011/11/24 03:35:58 mrg Exp $");
48 1.1 augustss
49 1.1 augustss #include <sys/param.h>
50 1.1 augustss #include <sys/systm.h>
51 1.1 augustss #include <sys/kernel.h>
52 1.29 jmcneill #include <sys/kmem.h>
53 1.1 augustss #include <sys/device.h>
54 1.1 augustss #include <sys/fcntl.h>
55 1.1 augustss #include <sys/proc.h>
56 1.1 augustss
57 1.1 augustss #include <dev/pci/pcidevs.h>
58 1.1 augustss #include <dev/pci/pcivar.h>
59 1.1 augustss #include <dev/pci/auacerreg.h>
60 1.1 augustss
61 1.1 augustss #include <sys/audioio.h>
62 1.1 augustss #include <dev/audio_if.h>
63 1.1 augustss #include <dev/mulaw.h>
64 1.1 augustss #include <dev/auconv.h>
65 1.1 augustss
66 1.17 ad #include <sys/bus.h>
67 1.1 augustss
68 1.1 augustss #include <dev/ic/ac97reg.h>
69 1.1 augustss #include <dev/ic/ac97var.h>
70 1.1 augustss
71 1.1 augustss struct auacer_dma {
72 1.1 augustss bus_dmamap_t map;
73 1.16 christos void *addr;
74 1.1 augustss bus_dma_segment_t segs[1];
75 1.1 augustss int nsegs;
76 1.1 augustss size_t size;
77 1.1 augustss struct auacer_dma *next;
78 1.1 augustss };
79 1.1 augustss
80 1.1 augustss #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr)
81 1.1 augustss #define KERNADDR(p) ((void *)((p)->addr))
82 1.1 augustss
83 1.1 augustss struct auacer_cdata {
84 1.1 augustss struct auacer_dmalist ic_dmalist_pcmo[ALI_DMALIST_MAX];
85 1.1 augustss };
86 1.1 augustss
87 1.1 augustss struct auacer_chan {
88 1.1 augustss uint32_t ptr;
89 1.1 augustss uint32_t start, p, end;
90 1.1 augustss uint32_t blksize, fifoe;
91 1.1 augustss uint32_t ack;
92 1.1 augustss uint32_t port;
93 1.1 augustss struct auacer_dmalist *dmalist;
94 1.1 augustss void (*intr)(void *);
95 1.1 augustss void *arg;
96 1.1 augustss };
97 1.1 augustss
98 1.1 augustss struct auacer_softc {
99 1.1 augustss struct device sc_dev;
100 1.1 augustss void *sc_ih;
101 1.29 jmcneill kmutex_t sc_lock;
102 1.29 jmcneill kmutex_t sc_intr_lock;
103 1.1 augustss
104 1.1 augustss audio_device_t sc_audev;
105 1.1 augustss
106 1.1 augustss bus_space_tag_t iot;
107 1.1 augustss bus_space_handle_t mix_ioh;
108 1.1 augustss bus_space_handle_t aud_ioh;
109 1.1 augustss bus_dma_tag_t dmat;
110 1.1 augustss
111 1.1 augustss struct ac97_codec_if *codec_if;
112 1.1 augustss struct ac97_host_if host_if;
113 1.1 augustss
114 1.1 augustss /* DMA scatter-gather lists. */
115 1.1 augustss bus_dmamap_t sc_cddmamap;
116 1.1 augustss #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
117 1.1 augustss
118 1.1 augustss struct auacer_cdata *sc_cdata;
119 1.1 augustss
120 1.1 augustss struct auacer_chan sc_pcmo;
121 1.1 augustss
122 1.1 augustss struct auacer_dma *sc_dmas;
123 1.1 augustss
124 1.1 augustss pci_chipset_tag_t sc_pc;
125 1.1 augustss pcitag_t sc_pt;
126 1.1 augustss
127 1.1 augustss int sc_dmamap_flags;
128 1.1 augustss
129 1.4 kent #define AUACER_NFORMATS 3
130 1.4 kent struct audio_format sc_formats[AUACER_NFORMATS];
131 1.4 kent struct audio_encoding_set *sc_encodings;
132 1.1 augustss };
133 1.1 augustss
134 1.1 augustss #define READ1(sc, a) bus_space_read_1(sc->iot, sc->aud_ioh, a)
135 1.1 augustss #define READ2(sc, a) bus_space_read_2(sc->iot, sc->aud_ioh, a)
136 1.1 augustss #define READ4(sc, a) bus_space_read_4(sc->iot, sc->aud_ioh, a)
137 1.1 augustss #define WRITE1(sc, a, v) bus_space_write_1(sc->iot, sc->aud_ioh, a, v)
138 1.1 augustss #define WRITE2(sc, a, v) bus_space_write_2(sc->iot, sc->aud_ioh, a, v)
139 1.1 augustss #define WRITE4(sc, a, v) bus_space_write_4(sc->iot, sc->aud_ioh, a, v)
140 1.1 augustss
141 1.1 augustss /* Debug */
142 1.1 augustss #ifdef AUACER_DEBUG
143 1.1 augustss #define DPRINTF(l,x) do { if (auacer_debug & (l)) printf x; } while(0)
144 1.1 augustss int auacer_debug = 0;
145 1.1 augustss #define ALI_DEBUG_CODECIO 0x0001
146 1.1 augustss #define ALI_DEBUG_DMA 0x0002
147 1.1 augustss #define ALI_DEBUG_INTR 0x0004
148 1.1 augustss #define ALI_DEBUG_API 0x0008
149 1.1 augustss #define ALI_DEBUG_MIXERAPI 0x0010
150 1.1 augustss #else
151 1.1 augustss #define DPRINTF(x,y) /* nothing */
152 1.1 augustss #endif
153 1.1 augustss
154 1.10 thorpej static int auacer_intr(void *);
155 1.1 augustss
156 1.10 thorpej static int auacer_query_encoding(void *, struct audio_encoding *);
157 1.10 thorpej static int auacer_set_params(void *, int, int, audio_params_t *,
158 1.10 thorpej audio_params_t *, stream_filter_list_t *,
159 1.10 thorpej stream_filter_list_t *);
160 1.10 thorpej static int auacer_round_blocksize(void *, int, int,
161 1.10 thorpej const audio_params_t *);
162 1.10 thorpej static int auacer_halt_output(void *);
163 1.10 thorpej static int auacer_halt_input(void *);
164 1.10 thorpej static int auacer_getdev(void *, struct audio_device *);
165 1.10 thorpej static int auacer_set_port(void *, mixer_ctrl_t *);
166 1.10 thorpej static int auacer_get_port(void *, mixer_ctrl_t *);
167 1.10 thorpej static int auacer_query_devinfo(void *, mixer_devinfo_t *);
168 1.29 jmcneill static void *auacer_allocm(void *, int, size_t);
169 1.29 jmcneill static void auacer_freem(void *, void *, size_t);
170 1.10 thorpej static size_t auacer_round_buffersize(void *, int, size_t);
171 1.10 thorpej static paddr_t auacer_mappage(void *, void *, off_t, int);
172 1.10 thorpej static int auacer_get_props(void *);
173 1.10 thorpej static int auacer_trigger_output(void *, void *, void *, int,
174 1.10 thorpej void (*)(void *), void *,
175 1.10 thorpej const audio_params_t *);
176 1.10 thorpej static int auacer_trigger_input(void *, void *, void *, int,
177 1.10 thorpej void (*)(void *), void *,
178 1.10 thorpej const audio_params_t *);
179 1.10 thorpej
180 1.10 thorpej static int auacer_alloc_cdata(struct auacer_softc *);
181 1.10 thorpej
182 1.10 thorpej static int auacer_allocmem(struct auacer_softc *, size_t, size_t,
183 1.10 thorpej struct auacer_dma *);
184 1.10 thorpej static int auacer_freemem(struct auacer_softc *, struct auacer_dma *);
185 1.29 jmcneill static void auacer_get_locks(void *, kmutex_t **, kmutex_t **);
186 1.1 augustss
187 1.27 dyoung static bool auacer_resume(device_t, const pmf_qual_t *);
188 1.10 thorpej static int auacer_set_rate(struct auacer_softc *, int, u_int);
189 1.1 augustss
190 1.1 augustss static void auacer_reset(struct auacer_softc *sc);
191 1.1 augustss
192 1.10 thorpej static struct audio_hw_if auacer_hw_if = {
193 1.6 kent NULL, /* open */
194 1.6 kent NULL, /* close */
195 1.1 augustss NULL, /* drain */
196 1.1 augustss auacer_query_encoding,
197 1.1 augustss auacer_set_params,
198 1.1 augustss auacer_round_blocksize,
199 1.1 augustss NULL, /* commit_setting */
200 1.1 augustss NULL, /* init_output */
201 1.1 augustss NULL, /* init_input */
202 1.1 augustss NULL, /* start_output */
203 1.1 augustss NULL, /* start_input */
204 1.1 augustss auacer_halt_output,
205 1.1 augustss auacer_halt_input,
206 1.1 augustss NULL, /* speaker_ctl */
207 1.1 augustss auacer_getdev,
208 1.1 augustss NULL, /* getfd */
209 1.1 augustss auacer_set_port,
210 1.1 augustss auacer_get_port,
211 1.1 augustss auacer_query_devinfo,
212 1.1 augustss auacer_allocm,
213 1.1 augustss auacer_freem,
214 1.1 augustss auacer_round_buffersize,
215 1.1 augustss auacer_mappage,
216 1.1 augustss auacer_get_props,
217 1.1 augustss auacer_trigger_output,
218 1.1 augustss auacer_trigger_input,
219 1.1 augustss NULL, /* dev_ioctl */
220 1.29 jmcneill auacer_get_locks,
221 1.1 augustss };
222 1.1 augustss
223 1.4 kent #define AUACER_FORMATS_4CH 1
224 1.4 kent #define AUACER_FORMATS_6CH 2
225 1.4 kent static const struct audio_format auacer_formats[AUACER_NFORMATS] = {
226 1.5 augustss {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
227 1.4 kent 2, AUFMT_STEREO, 0, {8000, 48000}},
228 1.4 kent {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
229 1.4 kent 4, AUFMT_SURROUND4, 0, {8000, 48000}},
230 1.4 kent {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
231 1.4 kent 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}},
232 1.4 kent };
233 1.4 kent
234 1.10 thorpej static int auacer_attach_codec(void *, struct ac97_codec_if *);
235 1.10 thorpej static int auacer_read_codec(void *, uint8_t, uint16_t *);
236 1.10 thorpej static int auacer_write_codec(void *, uint8_t, uint16_t);
237 1.10 thorpej static int auacer_reset_codec(void *);
238 1.1 augustss
239 1.10 thorpej static int
240 1.23 cegger auacer_match(device_t parent, cfdata_t match, void *aux)
241 1.1 augustss {
242 1.7 kent struct pci_attach_args *pa;
243 1.1 augustss
244 1.7 kent pa = (struct pci_attach_args *)aux;
245 1.1 augustss if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI &&
246 1.1 augustss PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M5455)
247 1.1 augustss return 1;
248 1.1 augustss return 0;
249 1.1 augustss }
250 1.1 augustss
251 1.10 thorpej static void
252 1.23 cegger auacer_attach(device_t parent, device_t self, void *aux)
253 1.1 augustss {
254 1.7 kent struct auacer_softc *sc;
255 1.7 kent struct pci_attach_args *pa;
256 1.1 augustss pci_intr_handle_t ih;
257 1.1 augustss bus_size_t aud_size;
258 1.1 augustss pcireg_t v;
259 1.1 augustss const char *intrstr;
260 1.4 kent int i;
261 1.1 augustss
262 1.24 cegger sc = device_private(self);
263 1.7 kent pa = aux;
264 1.1 augustss aprint_normal(": Acer Labs M5455 Audio controller\n");
265 1.1 augustss
266 1.1 augustss if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, &sc->iot,
267 1.1 augustss &sc->aud_ioh, NULL, &aud_size)) {
268 1.1 augustss aprint_error(": can't map i/o space\n");
269 1.1 augustss return;
270 1.1 augustss }
271 1.1 augustss
272 1.1 augustss sc->sc_pc = pa->pa_pc;
273 1.1 augustss sc->sc_pt = pa->pa_tag;
274 1.1 augustss sc->dmat = pa->pa_dmat;
275 1.1 augustss
276 1.1 augustss sc->sc_dmamap_flags = BUS_DMA_COHERENT; /* XXX remove */
277 1.1 augustss
278 1.29 jmcneill mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
279 1.30 mrg mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO);
280 1.29 jmcneill
281 1.1 augustss /* enable bus mastering */
282 1.1 augustss v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
283 1.1 augustss pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
284 1.1 augustss v | PCI_COMMAND_MASTER_ENABLE);
285 1.1 augustss
286 1.1 augustss /* Map and establish the interrupt. */
287 1.1 augustss if (pci_intr_map(pa, &ih)) {
288 1.20 cegger aprint_error_dev(&sc->sc_dev, "can't map interrupt\n");
289 1.29 jmcneill mutex_destroy(&sc->sc_lock);
290 1.29 jmcneill mutex_destroy(&sc->sc_intr_lock);
291 1.1 augustss return;
292 1.1 augustss }
293 1.1 augustss intrstr = pci_intr_string(pa->pa_pc, ih);
294 1.30 mrg sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO,
295 1.1 augustss auacer_intr, sc);
296 1.1 augustss if (sc->sc_ih == NULL) {
297 1.20 cegger aprint_error_dev(&sc->sc_dev, "can't establish interrupt");
298 1.1 augustss if (intrstr != NULL)
299 1.25 njoly aprint_error(" at %s", intrstr);
300 1.25 njoly aprint_error("\n");
301 1.29 jmcneill mutex_destroy(&sc->sc_lock);
302 1.29 jmcneill mutex_destroy(&sc->sc_intr_lock);
303 1.1 augustss return;
304 1.1 augustss }
305 1.20 cegger aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr);
306 1.1 augustss
307 1.1 augustss strlcpy(sc->sc_audev.name, "M5455 AC97", MAX_AUDIO_DEV_LEN);
308 1.1 augustss snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN,
309 1.1 augustss "0x%02x", PCI_REVISION(pa->pa_class));
310 1.20 cegger strlcpy(sc->sc_audev.config, device_xname(&sc->sc_dev), MAX_AUDIO_DEV_LEN);
311 1.1 augustss
312 1.1 augustss /* Set up DMA lists. */
313 1.1 augustss auacer_alloc_cdata(sc);
314 1.1 augustss sc->sc_pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo;
315 1.1 augustss sc->sc_pcmo.ptr = 0;
316 1.1 augustss sc->sc_pcmo.port = ALI_BASE_PO;
317 1.1 augustss
318 1.1 augustss DPRINTF(ALI_DEBUG_DMA, ("auacer_attach: lists %p\n",
319 1.1 augustss sc->sc_pcmo.dmalist));
320 1.1 augustss
321 1.1 augustss sc->host_if.arg = sc;
322 1.1 augustss sc->host_if.attach = auacer_attach_codec;
323 1.1 augustss sc->host_if.read = auacer_read_codec;
324 1.1 augustss sc->host_if.write = auacer_write_codec;
325 1.1 augustss sc->host_if.reset = auacer_reset_codec;
326 1.1 augustss
327 1.29 jmcneill if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) {
328 1.29 jmcneill mutex_destroy(&sc->sc_lock);
329 1.29 jmcneill mutex_destroy(&sc->sc_intr_lock);
330 1.1 augustss return;
331 1.29 jmcneill }
332 1.1 augustss
333 1.4 kent /* setup audio_format */
334 1.4 kent memcpy(sc->sc_formats, auacer_formats, sizeof(auacer_formats));
335 1.29 jmcneill mutex_enter(&sc->sc_lock);
336 1.4 kent if (!AC97_IS_4CH(sc->codec_if))
337 1.4 kent AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_4CH]);
338 1.4 kent if (!AC97_IS_6CH(sc->codec_if))
339 1.4 kent AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_6CH]);
340 1.4 kent if (AC97_IS_FIXED_RATE(sc->codec_if)) {
341 1.4 kent for (i = 0; i < AUACER_NFORMATS; i++) {
342 1.4 kent sc->sc_formats[i].frequency_type = 1;
343 1.4 kent sc->sc_formats[i].frequency[0] = 48000;
344 1.4 kent }
345 1.4 kent }
346 1.29 jmcneill mutex_exit(&sc->sc_lock);
347 1.4 kent
348 1.4 kent if (0 != auconv_create_encodings(sc->sc_formats, AUACER_NFORMATS,
349 1.4 kent &sc->sc_encodings)) {
350 1.29 jmcneill mutex_destroy(&sc->sc_lock);
351 1.29 jmcneill mutex_destroy(&sc->sc_intr_lock);
352 1.4 kent return;
353 1.4 kent }
354 1.4 kent
355 1.29 jmcneill mutex_enter(&sc->sc_lock);
356 1.29 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
357 1.29 jmcneill auacer_reset(sc);
358 1.29 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
359 1.29 jmcneill mutex_exit(&sc->sc_lock);
360 1.29 jmcneill
361 1.1 augustss audio_attach_mi(&auacer_hw_if, sc, &sc->sc_dev);
362 1.1 augustss
363 1.18 jmcneill if (!pmf_device_register(self, NULL, auacer_resume))
364 1.18 jmcneill aprint_error_dev(self, "couldn't establish power handler\n");
365 1.1 augustss }
366 1.1 augustss
367 1.10 thorpej CFATTACH_DECL(auacer, sizeof(struct auacer_softc),
368 1.10 thorpej auacer_match, auacer_attach, NULL, NULL);
369 1.10 thorpej
370 1.1 augustss static int
371 1.1 augustss auacer_ready_codec(struct auacer_softc *sc, int mask)
372 1.1 augustss {
373 1.7 kent int count;
374 1.1 augustss
375 1.1 augustss for (count = 0; count < 0x7f; count++) {
376 1.1 augustss int val = READ1(sc, ALI_CSPSR);
377 1.1 augustss if (val & mask)
378 1.1 augustss return 0;
379 1.1 augustss }
380 1.1 augustss
381 1.1 augustss aprint_normal("auacer_ready_codec: AC97 codec ready timeout.\n");
382 1.1 augustss return EBUSY;
383 1.1 augustss }
384 1.1 augustss
385 1.1 augustss static int
386 1.1 augustss auacer_sema_codec(struct auacer_softc *sc)
387 1.1 augustss {
388 1.9 christos int ttime;
389 1.1 augustss
390 1.9 christos ttime = 100;
391 1.9 christos while (ttime-- && (READ4(sc, ALI_CAS) & ALI_CAS_SEM_BUSY))
392 1.1 augustss delay(1);
393 1.9 christos if (!ttime)
394 1.1 augustss aprint_normal("auacer_sema_codec: timeout\n");
395 1.1 augustss return auacer_ready_codec(sc, ALI_CSPSR_CODEC_READY);
396 1.1 augustss }
397 1.1 augustss
398 1.10 thorpej static int
399 1.7 kent auacer_read_codec(void *v, uint8_t reg, uint16_t *val)
400 1.1 augustss {
401 1.7 kent struct auacer_softc *sc;
402 1.1 augustss
403 1.7 kent sc = v;
404 1.1 augustss if (auacer_sema_codec(sc))
405 1.1 augustss return EIO;
406 1.1 augustss
407 1.1 augustss reg |= ALI_CPR_ADDR_READ;
408 1.1 augustss #if 0
409 1.1 augustss if (ac97->num)
410 1.1 augustss reg |= ALI_CPR_ADDR_SECONDARY;
411 1.1 augustss #endif
412 1.1 augustss WRITE2(sc, ALI_CPR_ADDR, reg);
413 1.1 augustss if (auacer_ready_codec(sc, ALI_CSPSR_READ_OK))
414 1.1 augustss return EIO;
415 1.1 augustss *val = READ2(sc, ALI_SPR);
416 1.1 augustss
417 1.1 augustss DPRINTF(ALI_DEBUG_CODECIO, ("auacer_read_codec: reg=0x%x val=0x%x\n",
418 1.1 augustss reg, *val));
419 1.1 augustss
420 1.1 augustss return 0;
421 1.1 augustss }
422 1.1 augustss
423 1.1 augustss int
424 1.7 kent auacer_write_codec(void *v, uint8_t reg, uint16_t val)
425 1.1 augustss {
426 1.7 kent struct auacer_softc *sc;
427 1.1 augustss
428 1.1 augustss DPRINTF(ALI_DEBUG_CODECIO, ("auacer_write_codec: reg=0x%x val=0x%x\n",
429 1.1 augustss reg, val));
430 1.7 kent sc = v;
431 1.1 augustss if (auacer_sema_codec(sc))
432 1.1 augustss return EIO;
433 1.1 augustss WRITE2(sc, ALI_CPR, val);
434 1.1 augustss #if 0
435 1.1 augustss if (ac97->num)
436 1.1 augustss reg |= ALI_CPR_ADDR_SECONDARY;
437 1.1 augustss #endif
438 1.1 augustss WRITE2(sc, ALI_CPR_ADDR, reg);
439 1.1 augustss auacer_ready_codec(sc, ALI_CSPSR_WRITE_OK);
440 1.1 augustss return 0;
441 1.1 augustss }
442 1.1 augustss
443 1.10 thorpej static int
444 1.1 augustss auacer_attach_codec(void *v, struct ac97_codec_if *cif)
445 1.1 augustss {
446 1.7 kent struct auacer_softc *sc;
447 1.1 augustss
448 1.7 kent sc = v;
449 1.1 augustss sc->codec_if = cif;
450 1.1 augustss return 0;
451 1.1 augustss }
452 1.1 augustss
453 1.10 thorpej static int
454 1.1 augustss auacer_reset_codec(void *v)
455 1.1 augustss {
456 1.7 kent struct auacer_softc *sc;
457 1.7 kent uint32_t reg;
458 1.7 kent int i;
459 1.1 augustss
460 1.7 kent sc = v;
461 1.7 kent i = 0;
462 1.1 augustss reg = READ4(sc, ALI_SCR);
463 1.1 augustss if ((reg & 2) == 0) /* Cold required */
464 1.1 augustss reg |= 2;
465 1.1 augustss else
466 1.1 augustss reg |= 1; /* Warm */
467 1.1 augustss reg &= ~0x80000000; /* ACLink on */
468 1.1 augustss WRITE4(sc, ALI_SCR, reg);
469 1.1 augustss
470 1.1 augustss while (i < 10) {
471 1.1 augustss if ((READ4(sc, ALI_INTERRUPTSR) & ALI_INT_GPIO) == 0)
472 1.1 augustss break;
473 1.1 augustss delay(50000); /* XXX */
474 1.1 augustss i++;
475 1.1 augustss }
476 1.1 augustss if (i == 10) {
477 1.1 augustss return EIO;
478 1.1 augustss }
479 1.1 augustss
480 1.1 augustss for (i = 0; i < 10; i++) {
481 1.1 augustss reg = READ4(sc, ALI_RTSR);
482 1.1 augustss if (reg & 0x80) /* primary codec */
483 1.1 augustss break;
484 1.1 augustss WRITE4(sc, ALI_RTSR, reg | 0x80);
485 1.1 augustss delay(50000); /* XXX */
486 1.1 augustss }
487 1.1 augustss
488 1.1 augustss return 0;
489 1.1 augustss }
490 1.1 augustss
491 1.1 augustss static void
492 1.1 augustss auacer_reset(struct auacer_softc *sc)
493 1.1 augustss {
494 1.1 augustss WRITE4(sc, ALI_SCR, ALI_SCR_RESET);
495 1.1 augustss WRITE4(sc, ALI_FIFOCR1, 0x83838383);
496 1.1 augustss WRITE4(sc, ALI_FIFOCR2, 0x83838383);
497 1.1 augustss WRITE4(sc, ALI_FIFOCR3, 0x83838383);
498 1.1 augustss WRITE4(sc, ALI_INTERFACECR, ALI_IF_PO); /* XXX pcm out only */
499 1.1 augustss WRITE4(sc, ALI_INTERRUPTCR, 0x00000000);
500 1.1 augustss WRITE4(sc, ALI_INTERRUPTSR, 0x00000000);
501 1.1 augustss }
502 1.1 augustss
503 1.10 thorpej static int
504 1.1 augustss auacer_query_encoding(void *v, struct audio_encoding *aep)
505 1.1 augustss {
506 1.4 kent struct auacer_softc *sc;
507 1.4 kent
508 1.1 augustss DPRINTF(ALI_DEBUG_API, ("auacer_query_encoding\n"));
509 1.4 kent sc = v;
510 1.4 kent return auconv_query_encoding(sc->sc_encodings, aep);
511 1.1 augustss }
512 1.1 augustss
513 1.10 thorpej static int
514 1.6 kent auacer_set_rate(struct auacer_softc *sc, int mode, u_int srate)
515 1.1 augustss {
516 1.1 augustss int ret;
517 1.6 kent u_int ratetmp;
518 1.1 augustss
519 1.8 augustss DPRINTF(ALI_DEBUG_API, ("auacer_set_rate: srate=%u\n", srate));
520 1.1 augustss
521 1.1 augustss ratetmp = srate;
522 1.1 augustss if (mode == AUMODE_RECORD)
523 1.1 augustss return sc->codec_if->vtbl->set_rate(sc->codec_if,
524 1.1 augustss AC97_REG_PCM_LR_ADC_RATE, &ratetmp);
525 1.1 augustss ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
526 1.1 augustss AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp);
527 1.1 augustss if (ret)
528 1.1 augustss return ret;
529 1.1 augustss ratetmp = srate;
530 1.1 augustss ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
531 1.1 augustss AC97_REG_PCM_SURR_DAC_RATE, &ratetmp);
532 1.1 augustss if (ret)
533 1.1 augustss return ret;
534 1.1 augustss ratetmp = srate;
535 1.1 augustss ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
536 1.1 augustss AC97_REG_PCM_LFE_DAC_RATE, &ratetmp);
537 1.1 augustss return ret;
538 1.1 augustss }
539 1.1 augustss
540 1.10 thorpej static int
541 1.15 christos auacer_set_params(void *v, int setmode, int usemode,
542 1.14 christos audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil,
543 1.14 christos stream_filter_list_t *rfil)
544 1.1 augustss {
545 1.7 kent struct auacer_softc *sc;
546 1.1 augustss struct audio_params *p;
547 1.6 kent stream_filter_list_t *fil;
548 1.1 augustss uint32_t control;
549 1.4 kent int mode, index;
550 1.1 augustss
551 1.1 augustss DPRINTF(ALI_DEBUG_API, ("auacer_set_params\n"));
552 1.7 kent sc = v;
553 1.1 augustss for (mode = AUMODE_RECORD; mode != -1;
554 1.1 augustss mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) {
555 1.1 augustss if ((setmode & mode) == 0)
556 1.1 augustss continue;
557 1.1 augustss
558 1.1 augustss p = mode == AUMODE_PLAY ? play : rec;
559 1.1 augustss if (p == NULL)
560 1.1 augustss continue;
561 1.1 augustss
562 1.1 augustss if ((p->sample_rate != 8000) &&
563 1.1 augustss (p->sample_rate != 11025) &&
564 1.1 augustss (p->sample_rate != 12000) &&
565 1.1 augustss (p->sample_rate != 16000) &&
566 1.1 augustss (p->sample_rate != 22050) &&
567 1.1 augustss (p->sample_rate != 24000) &&
568 1.1 augustss (p->sample_rate != 32000) &&
569 1.1 augustss (p->sample_rate != 44100) &&
570 1.1 augustss (p->sample_rate != 48000))
571 1.1 augustss return (EINVAL);
572 1.1 augustss
573 1.6 kent fil = mode == AUMODE_PLAY ? pfil : rfil;
574 1.4 kent index = auconv_set_converter(sc->sc_formats, AUACER_NFORMATS,
575 1.6 kent mode, p, TRUE, fil);
576 1.4 kent if (index < 0)
577 1.4 kent return EINVAL;
578 1.6 kent if (fil->req_size > 0)
579 1.6 kent p = &fil->filters[0].param;
580 1.6 kent /* p points HW encoding */
581 1.4 kent if (sc->sc_formats[index].frequency_type != 1
582 1.6 kent && auacer_set_rate(sc, mode, p->sample_rate))
583 1.4 kent return EINVAL;
584 1.1 augustss if (mode == AUMODE_PLAY) {
585 1.1 augustss control = READ4(sc, ALI_SCR);
586 1.1 augustss control &= ~ALI_SCR_PCM_246_MASK;
587 1.1 augustss if (p->channels == 4)
588 1.1 augustss control |= ALI_SCR_PCM_4;
589 1.1 augustss else if (p->channels == 6)
590 1.1 augustss control |= ALI_SCR_PCM_6;
591 1.1 augustss WRITE4(sc, ALI_SCR, control);
592 1.1 augustss }
593 1.1 augustss }
594 1.1 augustss
595 1.1 augustss return (0);
596 1.1 augustss }
597 1.1 augustss
598 1.10 thorpej static int
599 1.15 christos auacer_round_blocksize(void *v, int blk, int mode,
600 1.15 christos const audio_params_t *param)
601 1.1 augustss {
602 1.1 augustss
603 1.7 kent return blk & ~0x3f; /* keep good alignment */
604 1.1 augustss }
605 1.1 augustss
606 1.1 augustss static void
607 1.1 augustss auacer_halt(struct auacer_softc *sc, struct auacer_chan *chan)
608 1.1 augustss {
609 1.1 augustss uint32_t val;
610 1.7 kent uint8_t port;
611 1.1 augustss uint32_t slot;
612 1.1 augustss
613 1.7 kent port = chan->port;
614 1.1 augustss DPRINTF(ALI_DEBUG_API, ("auacer_halt: port=0x%x\n", port));
615 1.1 augustss chan->intr = 0;
616 1.1 augustss
617 1.1 augustss slot = ALI_PORT2SLOT(port);
618 1.1 augustss
619 1.1 augustss val = READ4(sc, ALI_DMACR);
620 1.1 augustss val |= 1 << (slot+16); /* pause */
621 1.1 augustss val &= ~(1 << slot); /* no start */
622 1.1 augustss WRITE4(sc, ALI_DMACR, val);
623 1.1 augustss WRITE1(sc, port + ALI_OFF_CR, 0);
624 1.1 augustss while (READ1(sc, port + ALI_OFF_CR))
625 1.1 augustss ;
626 1.1 augustss /* reset whole DMA things */
627 1.1 augustss WRITE1(sc, port + ALI_OFF_CR, ALI_CR_RR);
628 1.1 augustss /* clear interrupts */
629 1.1 augustss WRITE1(sc, port + ALI_OFF_SR, READ1(sc, port+ALI_OFF_SR) | ALI_SR_W1TC);
630 1.1 augustss WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(port));
631 1.1 augustss }
632 1.1 augustss
633 1.10 thorpej static int
634 1.1 augustss auacer_halt_output(void *v)
635 1.1 augustss {
636 1.7 kent struct auacer_softc *sc;
637 1.1 augustss
638 1.1 augustss DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_output\n"));
639 1.7 kent sc = v;
640 1.1 augustss auacer_halt(sc, &sc->sc_pcmo);
641 1.1 augustss
642 1.7 kent return 0;
643 1.1 augustss }
644 1.1 augustss
645 1.10 thorpej static int
646 1.15 christos auacer_halt_input(void *v)
647 1.1 augustss {
648 1.1 augustss DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_input\n"));
649 1.1 augustss
650 1.7 kent return 0;
651 1.1 augustss }
652 1.1 augustss
653 1.10 thorpej static int
654 1.1 augustss auacer_getdev(void *v, struct audio_device *adp)
655 1.1 augustss {
656 1.7 kent struct auacer_softc *sc;
657 1.1 augustss
658 1.1 augustss DPRINTF(ALI_DEBUG_API, ("auacer_getdev\n"));
659 1.7 kent sc = v;
660 1.1 augustss *adp = sc->sc_audev;
661 1.7 kent return 0;
662 1.1 augustss }
663 1.1 augustss
664 1.10 thorpej static int
665 1.1 augustss auacer_set_port(void *v, mixer_ctrl_t *cp)
666 1.1 augustss {
667 1.7 kent struct auacer_softc *sc;
668 1.1 augustss
669 1.1 augustss DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_set_port\n"));
670 1.7 kent sc = v;
671 1.7 kent return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp);
672 1.1 augustss }
673 1.1 augustss
674 1.10 thorpej static int
675 1.1 augustss auacer_get_port(void *v, mixer_ctrl_t *cp)
676 1.1 augustss {
677 1.7 kent struct auacer_softc *sc;
678 1.1 augustss
679 1.1 augustss DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_get_port\n"));
680 1.7 kent sc = v;
681 1.7 kent return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp);
682 1.1 augustss }
683 1.1 augustss
684 1.10 thorpej static int
685 1.1 augustss auacer_query_devinfo(void *v, mixer_devinfo_t *dp)
686 1.1 augustss {
687 1.7 kent struct auacer_softc *sc;
688 1.1 augustss
689 1.1 augustss DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_query_devinfo\n"));
690 1.7 kent sc = v;
691 1.7 kent return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp);
692 1.1 augustss }
693 1.1 augustss
694 1.10 thorpej static void *
695 1.29 jmcneill auacer_allocm(void *v, int direction, size_t size)
696 1.1 augustss {
697 1.7 kent struct auacer_softc *sc;
698 1.1 augustss struct auacer_dma *p;
699 1.1 augustss int error;
700 1.1 augustss
701 1.1 augustss if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX))
702 1.7 kent return NULL;
703 1.1 augustss
704 1.29 jmcneill p = kmem_zalloc(sizeof(*p), KM_SLEEP);
705 1.1 augustss if (p == NULL)
706 1.7 kent return NULL;
707 1.7 kent sc = v;
708 1.1 augustss error = auacer_allocmem(sc, size, 0, p);
709 1.1 augustss if (error) {
710 1.29 jmcneill kmem_free(p, sizeof(*p));
711 1.7 kent return NULL;
712 1.1 augustss }
713 1.1 augustss
714 1.1 augustss p->next = sc->sc_dmas;
715 1.1 augustss sc->sc_dmas = p;
716 1.1 augustss
717 1.7 kent return KERNADDR(p);
718 1.1 augustss }
719 1.1 augustss
720 1.10 thorpej static void
721 1.29 jmcneill auacer_freem(void *v, void *ptr, size_t size)
722 1.1 augustss {
723 1.7 kent struct auacer_softc *sc;
724 1.1 augustss struct auacer_dma *p, **pp;
725 1.1 augustss
726 1.7 kent sc = v;
727 1.1 augustss for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) {
728 1.1 augustss if (KERNADDR(p) == ptr) {
729 1.1 augustss auacer_freemem(sc, p);
730 1.1 augustss *pp = p->next;
731 1.29 jmcneill kmem_free(p, sizeof(*p));
732 1.1 augustss return;
733 1.1 augustss }
734 1.1 augustss }
735 1.1 augustss }
736 1.1 augustss
737 1.10 thorpej static size_t
738 1.15 christos auacer_round_buffersize(void *v, int direction, size_t size)
739 1.1 augustss {
740 1.1 augustss
741 1.1 augustss if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX))
742 1.1 augustss size = ALI_DMALIST_MAX * ALI_DMASEG_MAX;
743 1.1 augustss
744 1.1 augustss return size;
745 1.1 augustss }
746 1.1 augustss
747 1.10 thorpej static paddr_t
748 1.1 augustss auacer_mappage(void *v, void *mem, off_t off, int prot)
749 1.1 augustss {
750 1.7 kent struct auacer_softc *sc;
751 1.1 augustss struct auacer_dma *p;
752 1.1 augustss
753 1.1 augustss if (off < 0)
754 1.7 kent return -1;
755 1.7 kent sc = v;
756 1.1 augustss for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next)
757 1.7 kent continue;
758 1.7 kent if (p == NULL)
759 1.7 kent return -1;
760 1.7 kent return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs,
761 1.7 kent off, prot, BUS_DMA_WAITOK);
762 1.1 augustss }
763 1.1 augustss
764 1.10 thorpej static int
765 1.1 augustss auacer_get_props(void *v)
766 1.1 augustss {
767 1.7 kent struct auacer_softc *sc;
768 1.1 augustss int props;
769 1.1 augustss
770 1.7 kent sc = v;
771 1.1 augustss props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX;
772 1.1 augustss /*
773 1.1 augustss * Even if the codec is fixed-rate, set_param() succeeds for any sample
774 1.1 augustss * rate because of aurateconv. Applications can't know what rate the
775 1.1 augustss * device can process in the case of mmap().
776 1.1 augustss */
777 1.3 kent if (!AC97_IS_FIXED_RATE(sc->codec_if))
778 1.1 augustss props |= AUDIO_PROP_MMAP;
779 1.1 augustss return props;
780 1.1 augustss }
781 1.1 augustss
782 1.1 augustss static void
783 1.29 jmcneill auacer_get_locks(void *v, kmutex_t **intr, kmutex_t **proc)
784 1.29 jmcneill {
785 1.29 jmcneill struct auacer_softc *sc;
786 1.29 jmcneill
787 1.29 jmcneill sc = v;
788 1.29 jmcneill *intr = &sc->sc_intr_lock;
789 1.29 jmcneill *proc = &sc->sc_lock;
790 1.29 jmcneill }
791 1.29 jmcneill
792 1.29 jmcneill static void
793 1.1 augustss auacer_add_entry(struct auacer_chan *chan)
794 1.1 augustss {
795 1.1 augustss struct auacer_dmalist *q;
796 1.1 augustss
797 1.1 augustss q = &chan->dmalist[chan->ptr];
798 1.1 augustss
799 1.1 augustss DPRINTF(ALI_DEBUG_INTR,
800 1.1 augustss ("auacer_add_entry: %p = %x @ 0x%x\n",
801 1.1 augustss q, chan->blksize / 2, chan->p));
802 1.1 augustss
803 1.1 augustss q->base = htole32(chan->p);
804 1.1 augustss q->len = htole32((chan->blksize / ALI_SAMPLE_SIZE) | ALI_DMAF_IOC);
805 1.1 augustss chan->p += chan->blksize;
806 1.1 augustss if (chan->p >= chan->end)
807 1.1 augustss chan->p = chan->start;
808 1.7 kent
809 1.1 augustss if (++chan->ptr >= ALI_DMALIST_MAX)
810 1.1 augustss chan->ptr = 0;
811 1.1 augustss }
812 1.1 augustss
813 1.1 augustss static void
814 1.1 augustss auacer_upd_chan(struct auacer_softc *sc, struct auacer_chan *chan)
815 1.1 augustss {
816 1.1 augustss uint32_t sts;
817 1.1 augustss uint32_t civ;
818 1.1 augustss
819 1.1 augustss sts = READ2(sc, chan->port + ALI_OFF_SR);
820 1.1 augustss /* intr ack */
821 1.1 augustss WRITE2(sc, chan->port + ALI_OFF_SR, sts & ALI_SR_W1TC);
822 1.1 augustss WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(chan->port));
823 1.1 augustss
824 1.1 augustss DPRINTF(ALI_DEBUG_INTR, ("auacer_upd_chan: sts=0x%x\n", sts));
825 1.1 augustss
826 1.1 augustss if (sts & ALI_SR_DMA_INT_FIFO) {
827 1.1 augustss printf("%s: fifo underrun # %u\n",
828 1.20 cegger device_xname(&sc->sc_dev), ++chan->fifoe);
829 1.1 augustss }
830 1.1 augustss
831 1.1 augustss civ = READ1(sc, chan->port + ALI_OFF_CIV);
832 1.7 kent
833 1.1 augustss DPRINTF(ALI_DEBUG_INTR,("auacer_intr: civ=%u ptr=%u\n",civ,chan->ptr));
834 1.7 kent
835 1.1 augustss /* XXX */
836 1.1 augustss while (chan->ptr != civ) {
837 1.1 augustss auacer_add_entry(chan);
838 1.1 augustss }
839 1.1 augustss
840 1.1 augustss WRITE1(sc, chan->port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK);
841 1.1 augustss
842 1.1 augustss while (chan->ack != civ) {
843 1.1 augustss if (chan->intr) {
844 1.1 augustss DPRINTF(ALI_DEBUG_INTR,("auacer_upd_chan: callback\n"));
845 1.1 augustss chan->intr(chan->arg);
846 1.1 augustss }
847 1.1 augustss chan->ack++;
848 1.1 augustss if (chan->ack >= ALI_DMALIST_MAX)
849 1.1 augustss chan->ack = 0;
850 1.1 augustss }
851 1.1 augustss }
852 1.1 augustss
853 1.10 thorpej static int
854 1.1 augustss auacer_intr(void *v)
855 1.1 augustss {
856 1.7 kent struct auacer_softc *sc;
857 1.1 augustss int ret, intrs;
858 1.1 augustss
859 1.7 kent sc = v;
860 1.29 jmcneill
861 1.29 jmcneill DPRINTF(ALI_DEBUG_INTR, ("auacer_intr: intrs=0x%x\n",
862 1.29 jmcneill READ4(sc, ALI_INTERRUPTSR)));
863 1.29 jmcneill
864 1.29 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
865 1.1 augustss intrs = READ4(sc, ALI_INTERRUPTSR);
866 1.1 augustss ret = 0;
867 1.1 augustss if (intrs & ALI_INT_PCMOUT) {
868 1.1 augustss auacer_upd_chan(sc, &sc->sc_pcmo);
869 1.1 augustss ret++;
870 1.1 augustss }
871 1.29 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
872 1.1 augustss
873 1.1 augustss return ret != 0;
874 1.1 augustss }
875 1.1 augustss
876 1.1 augustss static void
877 1.1 augustss auacer_setup_chan(struct auacer_softc *sc, struct auacer_chan *chan,
878 1.1 augustss uint32_t start, uint32_t size, uint32_t blksize,
879 1.1 augustss void (*intr)(void *), void *arg)
880 1.1 augustss {
881 1.1 augustss uint32_t port, slot;
882 1.1 augustss uint32_t offs, val;
883 1.1 augustss
884 1.1 augustss chan->start = start;
885 1.1 augustss chan->ptr = 0;
886 1.1 augustss chan->p = chan->start;
887 1.1 augustss chan->end = chan->start + size;
888 1.1 augustss chan->blksize = blksize;
889 1.1 augustss chan->ack = 0;
890 1.1 augustss chan->intr = intr;
891 1.1 augustss chan->arg = arg;
892 1.1 augustss
893 1.1 augustss auacer_add_entry(chan);
894 1.1 augustss auacer_add_entry(chan);
895 1.1 augustss
896 1.1 augustss port = chan->port;
897 1.1 augustss slot = ALI_PORT2SLOT(port);
898 1.1 augustss
899 1.1 augustss WRITE1(sc, port + ALI_OFF_CIV, 0);
900 1.1 augustss WRITE1(sc, port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK);
901 1.1 augustss offs = (char *)chan->dmalist - (char *)sc->sc_cdata;
902 1.1 augustss WRITE4(sc, port + ALI_OFF_BDBAR, sc->sc_cddma + offs);
903 1.1 augustss WRITE1(sc, port + ALI_OFF_CR,
904 1.1 augustss ALI_CR_IOCE | ALI_CR_FEIE | ALI_CR_LVBIE | ALI_CR_RPBM);
905 1.1 augustss val = READ4(sc, ALI_DMACR);
906 1.1 augustss val &= ~(1 << (slot+16)); /* no pause */
907 1.1 augustss val |= 1 << slot; /* start */
908 1.1 augustss WRITE4(sc, ALI_DMACR, val);
909 1.1 augustss }
910 1.1 augustss
911 1.10 thorpej static int
912 1.1 augustss auacer_trigger_output(void *v, void *start, void *end, int blksize,
913 1.15 christos void (*intr)(void *), void *arg, const audio_params_t *param)
914 1.1 augustss {
915 1.7 kent struct auacer_softc *sc;
916 1.1 augustss struct auacer_dma *p;
917 1.1 augustss uint32_t size;
918 1.1 augustss
919 1.1 augustss DPRINTF(ALI_DEBUG_DMA,
920 1.1 augustss ("auacer_trigger_output(%p, %p, %d, %p, %p, %p)\n",
921 1.1 augustss start, end, blksize, intr, arg, param));
922 1.7 kent sc = v;
923 1.1 augustss for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next)
924 1.7 kent continue;
925 1.1 augustss if (!p) {
926 1.1 augustss printf("auacer_trigger_output: bad addr %p\n", start);
927 1.1 augustss return (EINVAL);
928 1.1 augustss }
929 1.1 augustss
930 1.1 augustss size = (char *)end - (char *)start;
931 1.1 augustss auacer_setup_chan(sc, &sc->sc_pcmo, DMAADDR(p), size, blksize,
932 1.1 augustss intr, arg);
933 1.1 augustss
934 1.1 augustss return 0;
935 1.1 augustss }
936 1.1 augustss
937 1.10 thorpej static int
938 1.15 christos auacer_trigger_input(void *v, void *start, void *end,
939 1.15 christos int blksize, void (*intr)(void *), void *arg,
940 1.15 christos const audio_params_t *param)
941 1.1 augustss {
942 1.7 kent return EINVAL;
943 1.1 augustss }
944 1.1 augustss
945 1.10 thorpej static int
946 1.1 augustss auacer_allocmem(struct auacer_softc *sc, size_t size, size_t align,
947 1.1 augustss struct auacer_dma *p)
948 1.1 augustss {
949 1.1 augustss int error;
950 1.1 augustss
951 1.1 augustss p->size = size;
952 1.1 augustss error = bus_dmamem_alloc(sc->dmat, p->size, align, 0,
953 1.1 augustss p->segs, sizeof(p->segs)/sizeof(p->segs[0]),
954 1.29 jmcneill &p->nsegs, BUS_DMA_WAITOK);
955 1.1 augustss if (error)
956 1.7 kent return error;
957 1.1 augustss
958 1.1 augustss error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size,
959 1.29 jmcneill &p->addr, BUS_DMA_WAITOK|sc->sc_dmamap_flags);
960 1.1 augustss if (error)
961 1.1 augustss goto free;
962 1.1 augustss
963 1.1 augustss error = bus_dmamap_create(sc->dmat, p->size, 1, p->size,
964 1.29 jmcneill 0, BUS_DMA_WAITOK, &p->map);
965 1.1 augustss if (error)
966 1.1 augustss goto unmap;
967 1.1 augustss
968 1.1 augustss error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL,
969 1.29 jmcneill BUS_DMA_WAITOK);
970 1.1 augustss if (error)
971 1.1 augustss goto destroy;
972 1.1 augustss return (0);
973 1.1 augustss
974 1.1 augustss destroy:
975 1.1 augustss bus_dmamap_destroy(sc->dmat, p->map);
976 1.1 augustss unmap:
977 1.1 augustss bus_dmamem_unmap(sc->dmat, p->addr, p->size);
978 1.1 augustss free:
979 1.1 augustss bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
980 1.7 kent return error;
981 1.1 augustss }
982 1.1 augustss
983 1.10 thorpej static int
984 1.1 augustss auacer_freemem(struct auacer_softc *sc, struct auacer_dma *p)
985 1.1 augustss {
986 1.1 augustss
987 1.1 augustss bus_dmamap_unload(sc->dmat, p->map);
988 1.1 augustss bus_dmamap_destroy(sc->dmat, p->map);
989 1.1 augustss bus_dmamem_unmap(sc->dmat, p->addr, p->size);
990 1.1 augustss bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
991 1.7 kent return 0;
992 1.1 augustss }
993 1.1 augustss
994 1.10 thorpej static int
995 1.1 augustss auacer_alloc_cdata(struct auacer_softc *sc)
996 1.1 augustss {
997 1.1 augustss bus_dma_segment_t seg;
998 1.1 augustss int error, rseg;
999 1.1 augustss
1000 1.1 augustss /*
1001 1.1 augustss * Allocate the control data structure, and create and load the
1002 1.1 augustss * DMA map for it.
1003 1.1 augustss */
1004 1.1 augustss if ((error = bus_dmamem_alloc(sc->dmat,
1005 1.1 augustss sizeof(struct auacer_cdata),
1006 1.1 augustss PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) {
1007 1.20 cegger aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n",
1008 1.20 cegger error);
1009 1.1 augustss goto fail_0;
1010 1.1 augustss }
1011 1.1 augustss
1012 1.1 augustss if ((error = bus_dmamem_map(sc->dmat, &seg, rseg,
1013 1.1 augustss sizeof(struct auacer_cdata),
1014 1.16 christos (void **) &sc->sc_cdata,
1015 1.1 augustss sc->sc_dmamap_flags)) != 0) {
1016 1.20 cegger aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n",
1017 1.20 cegger error);
1018 1.1 augustss goto fail_1;
1019 1.1 augustss }
1020 1.1 augustss
1021 1.1 augustss if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auacer_cdata), 1,
1022 1.1 augustss sizeof(struct auacer_cdata), 0, 0,
1023 1.1 augustss &sc->sc_cddmamap)) != 0) {
1024 1.20 cegger aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, "
1025 1.20 cegger "error = %d\n", error);
1026 1.1 augustss goto fail_2;
1027 1.1 augustss }
1028 1.1 augustss
1029 1.1 augustss if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap,
1030 1.1 augustss sc->sc_cdata, sizeof(struct auacer_cdata),
1031 1.1 augustss NULL, 0)) != 0) {
1032 1.20 cegger aprint_error_dev(&sc->sc_dev, "unable to load control data DMA map, "
1033 1.20 cegger "error = %d\n", error);
1034 1.1 augustss goto fail_3;
1035 1.1 augustss }
1036 1.1 augustss
1037 1.7 kent return 0;
1038 1.1 augustss
1039 1.1 augustss fail_3:
1040 1.1 augustss bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap);
1041 1.1 augustss fail_2:
1042 1.16 christos bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata,
1043 1.1 augustss sizeof(struct auacer_cdata));
1044 1.1 augustss fail_1:
1045 1.1 augustss bus_dmamem_free(sc->dmat, &seg, rseg);
1046 1.1 augustss fail_0:
1047 1.7 kent return error;
1048 1.1 augustss }
1049 1.1 augustss
1050 1.18 jmcneill static bool
1051 1.27 dyoung auacer_resume(device_t dv, const pmf_qual_t *qual)
1052 1.1 augustss {
1053 1.18 jmcneill struct auacer_softc *sc = device_private(dv);
1054 1.18 jmcneill
1055 1.29 jmcneill mutex_enter(&sc->sc_lock);
1056 1.29 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
1057 1.18 jmcneill auacer_reset_codec(sc);
1058 1.29 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
1059 1.18 jmcneill delay(1000);
1060 1.18 jmcneill sc->codec_if->vtbl->restore_ports(sc->codec_if);
1061 1.29 jmcneill mutex_exit(&sc->sc_lock);
1062 1.1 augustss
1063 1.18 jmcneill return true;
1064 1.1 augustss }
1065