auacer.c revision 1.36 1 1.36 isaki /* $NetBSD: auacer.c,v 1.36 2019/03/16 12:09:58 isaki Exp $ */
2 1.1 augustss
3 1.1 augustss /*-
4 1.29 jmcneill * Copyright (c) 2004, 2008 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.1 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.1 augustss * by Lennart Augustsson.
9 1.1 augustss *
10 1.1 augustss * Redistribution and use in source and binary forms, with or without
11 1.1 augustss * modification, are permitted provided that the following conditions
12 1.1 augustss * are met:
13 1.1 augustss * 1. Redistributions of source code must retain the above copyright
14 1.1 augustss * notice, this list of conditions and the following disclaimer.
15 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 augustss * notice, this list of conditions and the following disclaimer in the
17 1.1 augustss * documentation and/or other materials provided with the distribution.
18 1.1 augustss *
19 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
30 1.1 augustss */
31 1.1 augustss
32 1.1 augustss /*
33 1.1 augustss * Acer Labs M5455 audio driver
34 1.1 augustss *
35 1.5 augustss * Acer provides data sheets after signing an NDA, so this is guess work.
36 1.1 augustss * The chip behaves somewhat like the Intel i8x0, so this driver
37 1.1 augustss * is loosely based on the auich driver. Additional information taken from
38 1.1 augustss * the ALSA intel8x0.c driver (which handles M5455 as well).
39 1.1 augustss *
40 1.1 augustss * As an historical note one can observe that the auich driver borrows
41 1.1 augustss * lot from the first NetBSD PCI audio driver, the eap driver. But this
42 1.1 augustss * is not attributed anywhere.
43 1.1 augustss */
44 1.1 augustss
45 1.1 augustss
46 1.1 augustss #include <sys/cdefs.h>
47 1.36 isaki __KERNEL_RCSID(0, "$NetBSD: auacer.c,v 1.36 2019/03/16 12:09:58 isaki Exp $");
48 1.1 augustss
49 1.1 augustss #include <sys/param.h>
50 1.1 augustss #include <sys/systm.h>
51 1.1 augustss #include <sys/kernel.h>
52 1.29 jmcneill #include <sys/kmem.h>
53 1.1 augustss #include <sys/device.h>
54 1.1 augustss #include <sys/fcntl.h>
55 1.1 augustss #include <sys/proc.h>
56 1.1 augustss
57 1.1 augustss #include <dev/pci/pcidevs.h>
58 1.1 augustss #include <dev/pci/pcivar.h>
59 1.1 augustss #include <dev/pci/auacerreg.h>
60 1.1 augustss
61 1.1 augustss #include <sys/audioio.h>
62 1.1 augustss #include <dev/audio_if.h>
63 1.1 augustss #include <dev/mulaw.h>
64 1.1 augustss #include <dev/auconv.h>
65 1.1 augustss
66 1.17 ad #include <sys/bus.h>
67 1.1 augustss
68 1.1 augustss #include <dev/ic/ac97reg.h>
69 1.1 augustss #include <dev/ic/ac97var.h>
70 1.1 augustss
71 1.1 augustss struct auacer_dma {
72 1.1 augustss bus_dmamap_t map;
73 1.16 christos void *addr;
74 1.1 augustss bus_dma_segment_t segs[1];
75 1.1 augustss int nsegs;
76 1.1 augustss size_t size;
77 1.1 augustss struct auacer_dma *next;
78 1.1 augustss };
79 1.1 augustss
80 1.1 augustss #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr)
81 1.1 augustss #define KERNADDR(p) ((void *)((p)->addr))
82 1.1 augustss
83 1.1 augustss struct auacer_cdata {
84 1.1 augustss struct auacer_dmalist ic_dmalist_pcmo[ALI_DMALIST_MAX];
85 1.1 augustss };
86 1.1 augustss
87 1.1 augustss struct auacer_chan {
88 1.1 augustss uint32_t ptr;
89 1.1 augustss uint32_t start, p, end;
90 1.1 augustss uint32_t blksize, fifoe;
91 1.1 augustss uint32_t ack;
92 1.1 augustss uint32_t port;
93 1.1 augustss struct auacer_dmalist *dmalist;
94 1.1 augustss void (*intr)(void *);
95 1.1 augustss void *arg;
96 1.1 augustss };
97 1.1 augustss
98 1.1 augustss struct auacer_softc {
99 1.31 chs device_t sc_dev;
100 1.1 augustss void *sc_ih;
101 1.29 jmcneill kmutex_t sc_lock;
102 1.29 jmcneill kmutex_t sc_intr_lock;
103 1.1 augustss
104 1.1 augustss audio_device_t sc_audev;
105 1.1 augustss
106 1.1 augustss bus_space_tag_t iot;
107 1.1 augustss bus_space_handle_t mix_ioh;
108 1.1 augustss bus_space_handle_t aud_ioh;
109 1.1 augustss bus_dma_tag_t dmat;
110 1.1 augustss
111 1.1 augustss struct ac97_codec_if *codec_if;
112 1.1 augustss struct ac97_host_if host_if;
113 1.1 augustss
114 1.1 augustss /* DMA scatter-gather lists. */
115 1.1 augustss bus_dmamap_t sc_cddmamap;
116 1.1 augustss #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
117 1.1 augustss
118 1.1 augustss struct auacer_cdata *sc_cdata;
119 1.1 augustss
120 1.1 augustss struct auacer_chan sc_pcmo;
121 1.1 augustss
122 1.1 augustss struct auacer_dma *sc_dmas;
123 1.1 augustss
124 1.1 augustss pci_chipset_tag_t sc_pc;
125 1.1 augustss pcitag_t sc_pt;
126 1.1 augustss
127 1.1 augustss int sc_dmamap_flags;
128 1.1 augustss
129 1.4 kent #define AUACER_NFORMATS 3
130 1.4 kent struct audio_format sc_formats[AUACER_NFORMATS];
131 1.4 kent struct audio_encoding_set *sc_encodings;
132 1.1 augustss };
133 1.1 augustss
134 1.1 augustss #define READ1(sc, a) bus_space_read_1(sc->iot, sc->aud_ioh, a)
135 1.1 augustss #define READ2(sc, a) bus_space_read_2(sc->iot, sc->aud_ioh, a)
136 1.1 augustss #define READ4(sc, a) bus_space_read_4(sc->iot, sc->aud_ioh, a)
137 1.1 augustss #define WRITE1(sc, a, v) bus_space_write_1(sc->iot, sc->aud_ioh, a, v)
138 1.1 augustss #define WRITE2(sc, a, v) bus_space_write_2(sc->iot, sc->aud_ioh, a, v)
139 1.1 augustss #define WRITE4(sc, a, v) bus_space_write_4(sc->iot, sc->aud_ioh, a, v)
140 1.1 augustss
141 1.1 augustss /* Debug */
142 1.1 augustss #ifdef AUACER_DEBUG
143 1.1 augustss #define DPRINTF(l,x) do { if (auacer_debug & (l)) printf x; } while(0)
144 1.1 augustss int auacer_debug = 0;
145 1.1 augustss #define ALI_DEBUG_CODECIO 0x0001
146 1.1 augustss #define ALI_DEBUG_DMA 0x0002
147 1.1 augustss #define ALI_DEBUG_INTR 0x0004
148 1.1 augustss #define ALI_DEBUG_API 0x0008
149 1.1 augustss #define ALI_DEBUG_MIXERAPI 0x0010
150 1.1 augustss #else
151 1.1 augustss #define DPRINTF(x,y) /* nothing */
152 1.1 augustss #endif
153 1.1 augustss
154 1.10 thorpej static int auacer_intr(void *);
155 1.1 augustss
156 1.10 thorpej static int auacer_query_encoding(void *, struct audio_encoding *);
157 1.10 thorpej static int auacer_set_params(void *, int, int, audio_params_t *,
158 1.10 thorpej audio_params_t *, stream_filter_list_t *,
159 1.10 thorpej stream_filter_list_t *);
160 1.10 thorpej static int auacer_round_blocksize(void *, int, int,
161 1.10 thorpej const audio_params_t *);
162 1.10 thorpej static int auacer_halt_output(void *);
163 1.10 thorpej static int auacer_halt_input(void *);
164 1.10 thorpej static int auacer_getdev(void *, struct audio_device *);
165 1.10 thorpej static int auacer_set_port(void *, mixer_ctrl_t *);
166 1.10 thorpej static int auacer_get_port(void *, mixer_ctrl_t *);
167 1.10 thorpej static int auacer_query_devinfo(void *, mixer_devinfo_t *);
168 1.29 jmcneill static void *auacer_allocm(void *, int, size_t);
169 1.29 jmcneill static void auacer_freem(void *, void *, size_t);
170 1.10 thorpej static size_t auacer_round_buffersize(void *, int, size_t);
171 1.10 thorpej static paddr_t auacer_mappage(void *, void *, off_t, int);
172 1.10 thorpej static int auacer_get_props(void *);
173 1.10 thorpej static int auacer_trigger_output(void *, void *, void *, int,
174 1.10 thorpej void (*)(void *), void *,
175 1.10 thorpej const audio_params_t *);
176 1.10 thorpej static int auacer_trigger_input(void *, void *, void *, int,
177 1.10 thorpej void (*)(void *), void *,
178 1.10 thorpej const audio_params_t *);
179 1.10 thorpej
180 1.10 thorpej static int auacer_alloc_cdata(struct auacer_softc *);
181 1.10 thorpej
182 1.10 thorpej static int auacer_allocmem(struct auacer_softc *, size_t, size_t,
183 1.10 thorpej struct auacer_dma *);
184 1.10 thorpej static int auacer_freemem(struct auacer_softc *, struct auacer_dma *);
185 1.29 jmcneill static void auacer_get_locks(void *, kmutex_t **, kmutex_t **);
186 1.1 augustss
187 1.27 dyoung static bool auacer_resume(device_t, const pmf_qual_t *);
188 1.10 thorpej static int auacer_set_rate(struct auacer_softc *, int, u_int);
189 1.1 augustss
190 1.1 augustss static void auacer_reset(struct auacer_softc *sc);
191 1.1 augustss
192 1.34 maxv static const struct audio_hw_if auacer_hw_if = {
193 1.36 isaki .query_encoding = auacer_query_encoding,
194 1.36 isaki .set_params = auacer_set_params,
195 1.36 isaki .round_blocksize = auacer_round_blocksize,
196 1.36 isaki .halt_output = auacer_halt_output,
197 1.36 isaki .halt_input = auacer_halt_input,
198 1.36 isaki .getdev = auacer_getdev,
199 1.36 isaki .set_port = auacer_set_port,
200 1.36 isaki .get_port = auacer_get_port,
201 1.36 isaki .query_devinfo = auacer_query_devinfo,
202 1.36 isaki .allocm = auacer_allocm,
203 1.36 isaki .freem = auacer_freem,
204 1.36 isaki .round_buffersize = auacer_round_buffersize,
205 1.36 isaki .mappage = auacer_mappage,
206 1.36 isaki .get_props = auacer_get_props,
207 1.36 isaki .trigger_output = auacer_trigger_output,
208 1.36 isaki .trigger_input = auacer_trigger_input,
209 1.36 isaki .get_locks = auacer_get_locks,
210 1.1 augustss };
211 1.1 augustss
212 1.4 kent #define AUACER_FORMATS_4CH 1
213 1.4 kent #define AUACER_FORMATS_6CH 2
214 1.4 kent static const struct audio_format auacer_formats[AUACER_NFORMATS] = {
215 1.5 augustss {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
216 1.4 kent 2, AUFMT_STEREO, 0, {8000, 48000}},
217 1.4 kent {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
218 1.4 kent 4, AUFMT_SURROUND4, 0, {8000, 48000}},
219 1.4 kent {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
220 1.4 kent 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}},
221 1.4 kent };
222 1.4 kent
223 1.10 thorpej static int auacer_attach_codec(void *, struct ac97_codec_if *);
224 1.10 thorpej static int auacer_read_codec(void *, uint8_t, uint16_t *);
225 1.10 thorpej static int auacer_write_codec(void *, uint8_t, uint16_t);
226 1.10 thorpej static int auacer_reset_codec(void *);
227 1.1 augustss
228 1.10 thorpej static int
229 1.23 cegger auacer_match(device_t parent, cfdata_t match, void *aux)
230 1.1 augustss {
231 1.7 kent struct pci_attach_args *pa;
232 1.1 augustss
233 1.7 kent pa = (struct pci_attach_args *)aux;
234 1.1 augustss if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI &&
235 1.1 augustss PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M5455)
236 1.1 augustss return 1;
237 1.1 augustss return 0;
238 1.1 augustss }
239 1.1 augustss
240 1.10 thorpej static void
241 1.23 cegger auacer_attach(device_t parent, device_t self, void *aux)
242 1.1 augustss {
243 1.7 kent struct auacer_softc *sc;
244 1.7 kent struct pci_attach_args *pa;
245 1.1 augustss pci_intr_handle_t ih;
246 1.1 augustss bus_size_t aud_size;
247 1.1 augustss pcireg_t v;
248 1.1 augustss const char *intrstr;
249 1.4 kent int i;
250 1.32 christos char intrbuf[PCI_INTRSTR_LEN];
251 1.1 augustss
252 1.24 cegger sc = device_private(self);
253 1.31 chs sc->sc_dev = self;
254 1.7 kent pa = aux;
255 1.1 augustss aprint_normal(": Acer Labs M5455 Audio controller\n");
256 1.1 augustss
257 1.1 augustss if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, &sc->iot,
258 1.1 augustss &sc->aud_ioh, NULL, &aud_size)) {
259 1.1 augustss aprint_error(": can't map i/o space\n");
260 1.1 augustss return;
261 1.1 augustss }
262 1.1 augustss
263 1.1 augustss sc->sc_pc = pa->pa_pc;
264 1.1 augustss sc->sc_pt = pa->pa_tag;
265 1.1 augustss sc->dmat = pa->pa_dmat;
266 1.1 augustss
267 1.1 augustss sc->sc_dmamap_flags = BUS_DMA_COHERENT; /* XXX remove */
268 1.1 augustss
269 1.29 jmcneill mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
270 1.30 mrg mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO);
271 1.29 jmcneill
272 1.1 augustss /* enable bus mastering */
273 1.1 augustss v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
274 1.1 augustss pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
275 1.1 augustss v | PCI_COMMAND_MASTER_ENABLE);
276 1.1 augustss
277 1.1 augustss /* Map and establish the interrupt. */
278 1.1 augustss if (pci_intr_map(pa, &ih)) {
279 1.31 chs aprint_error_dev(sc->sc_dev, "can't map interrupt\n");
280 1.29 jmcneill mutex_destroy(&sc->sc_lock);
281 1.29 jmcneill mutex_destroy(&sc->sc_intr_lock);
282 1.1 augustss return;
283 1.1 augustss }
284 1.32 christos intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf));
285 1.35 jdolecek sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_AUDIO,
286 1.35 jdolecek auacer_intr, sc, device_xname(self));
287 1.1 augustss if (sc->sc_ih == NULL) {
288 1.31 chs aprint_error_dev(sc->sc_dev, "can't establish interrupt");
289 1.1 augustss if (intrstr != NULL)
290 1.25 njoly aprint_error(" at %s", intrstr);
291 1.25 njoly aprint_error("\n");
292 1.29 jmcneill mutex_destroy(&sc->sc_lock);
293 1.29 jmcneill mutex_destroy(&sc->sc_intr_lock);
294 1.1 augustss return;
295 1.1 augustss }
296 1.31 chs aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
297 1.1 augustss
298 1.1 augustss strlcpy(sc->sc_audev.name, "M5455 AC97", MAX_AUDIO_DEV_LEN);
299 1.1 augustss snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN,
300 1.1 augustss "0x%02x", PCI_REVISION(pa->pa_class));
301 1.31 chs strlcpy(sc->sc_audev.config, device_xname(sc->sc_dev), MAX_AUDIO_DEV_LEN);
302 1.1 augustss
303 1.1 augustss /* Set up DMA lists. */
304 1.1 augustss auacer_alloc_cdata(sc);
305 1.1 augustss sc->sc_pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo;
306 1.1 augustss sc->sc_pcmo.ptr = 0;
307 1.1 augustss sc->sc_pcmo.port = ALI_BASE_PO;
308 1.1 augustss
309 1.1 augustss DPRINTF(ALI_DEBUG_DMA, ("auacer_attach: lists %p\n",
310 1.1 augustss sc->sc_pcmo.dmalist));
311 1.1 augustss
312 1.1 augustss sc->host_if.arg = sc;
313 1.1 augustss sc->host_if.attach = auacer_attach_codec;
314 1.1 augustss sc->host_if.read = auacer_read_codec;
315 1.1 augustss sc->host_if.write = auacer_write_codec;
316 1.1 augustss sc->host_if.reset = auacer_reset_codec;
317 1.1 augustss
318 1.29 jmcneill if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) {
319 1.29 jmcneill mutex_destroy(&sc->sc_lock);
320 1.29 jmcneill mutex_destroy(&sc->sc_intr_lock);
321 1.1 augustss return;
322 1.29 jmcneill }
323 1.1 augustss
324 1.4 kent /* setup audio_format */
325 1.4 kent memcpy(sc->sc_formats, auacer_formats, sizeof(auacer_formats));
326 1.29 jmcneill mutex_enter(&sc->sc_lock);
327 1.4 kent if (!AC97_IS_4CH(sc->codec_if))
328 1.4 kent AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_4CH]);
329 1.4 kent if (!AC97_IS_6CH(sc->codec_if))
330 1.4 kent AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_6CH]);
331 1.4 kent if (AC97_IS_FIXED_RATE(sc->codec_if)) {
332 1.4 kent for (i = 0; i < AUACER_NFORMATS; i++) {
333 1.4 kent sc->sc_formats[i].frequency_type = 1;
334 1.4 kent sc->sc_formats[i].frequency[0] = 48000;
335 1.4 kent }
336 1.4 kent }
337 1.29 jmcneill mutex_exit(&sc->sc_lock);
338 1.4 kent
339 1.4 kent if (0 != auconv_create_encodings(sc->sc_formats, AUACER_NFORMATS,
340 1.4 kent &sc->sc_encodings)) {
341 1.29 jmcneill mutex_destroy(&sc->sc_lock);
342 1.29 jmcneill mutex_destroy(&sc->sc_intr_lock);
343 1.4 kent return;
344 1.4 kent }
345 1.4 kent
346 1.29 jmcneill mutex_enter(&sc->sc_lock);
347 1.29 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
348 1.29 jmcneill auacer_reset(sc);
349 1.29 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
350 1.29 jmcneill mutex_exit(&sc->sc_lock);
351 1.29 jmcneill
352 1.31 chs audio_attach_mi(&auacer_hw_if, sc, sc->sc_dev);
353 1.1 augustss
354 1.18 jmcneill if (!pmf_device_register(self, NULL, auacer_resume))
355 1.18 jmcneill aprint_error_dev(self, "couldn't establish power handler\n");
356 1.1 augustss }
357 1.1 augustss
358 1.31 chs CFATTACH_DECL_NEW(auacer, sizeof(struct auacer_softc),
359 1.10 thorpej auacer_match, auacer_attach, NULL, NULL);
360 1.10 thorpej
361 1.1 augustss static int
362 1.1 augustss auacer_ready_codec(struct auacer_softc *sc, int mask)
363 1.1 augustss {
364 1.7 kent int count;
365 1.1 augustss
366 1.1 augustss for (count = 0; count < 0x7f; count++) {
367 1.1 augustss int val = READ1(sc, ALI_CSPSR);
368 1.1 augustss if (val & mask)
369 1.1 augustss return 0;
370 1.1 augustss }
371 1.1 augustss
372 1.1 augustss aprint_normal("auacer_ready_codec: AC97 codec ready timeout.\n");
373 1.1 augustss return EBUSY;
374 1.1 augustss }
375 1.1 augustss
376 1.1 augustss static int
377 1.1 augustss auacer_sema_codec(struct auacer_softc *sc)
378 1.1 augustss {
379 1.9 christos int ttime;
380 1.1 augustss
381 1.9 christos ttime = 100;
382 1.9 christos while (ttime-- && (READ4(sc, ALI_CAS) & ALI_CAS_SEM_BUSY))
383 1.1 augustss delay(1);
384 1.9 christos if (!ttime)
385 1.1 augustss aprint_normal("auacer_sema_codec: timeout\n");
386 1.1 augustss return auacer_ready_codec(sc, ALI_CSPSR_CODEC_READY);
387 1.1 augustss }
388 1.1 augustss
389 1.10 thorpej static int
390 1.7 kent auacer_read_codec(void *v, uint8_t reg, uint16_t *val)
391 1.1 augustss {
392 1.7 kent struct auacer_softc *sc;
393 1.1 augustss
394 1.7 kent sc = v;
395 1.1 augustss if (auacer_sema_codec(sc))
396 1.1 augustss return EIO;
397 1.1 augustss
398 1.1 augustss reg |= ALI_CPR_ADDR_READ;
399 1.1 augustss #if 0
400 1.1 augustss if (ac97->num)
401 1.1 augustss reg |= ALI_CPR_ADDR_SECONDARY;
402 1.1 augustss #endif
403 1.1 augustss WRITE2(sc, ALI_CPR_ADDR, reg);
404 1.1 augustss if (auacer_ready_codec(sc, ALI_CSPSR_READ_OK))
405 1.1 augustss return EIO;
406 1.1 augustss *val = READ2(sc, ALI_SPR);
407 1.1 augustss
408 1.1 augustss DPRINTF(ALI_DEBUG_CODECIO, ("auacer_read_codec: reg=0x%x val=0x%x\n",
409 1.1 augustss reg, *val));
410 1.1 augustss
411 1.1 augustss return 0;
412 1.1 augustss }
413 1.1 augustss
414 1.1 augustss int
415 1.7 kent auacer_write_codec(void *v, uint8_t reg, uint16_t val)
416 1.1 augustss {
417 1.7 kent struct auacer_softc *sc;
418 1.1 augustss
419 1.1 augustss DPRINTF(ALI_DEBUG_CODECIO, ("auacer_write_codec: reg=0x%x val=0x%x\n",
420 1.1 augustss reg, val));
421 1.7 kent sc = v;
422 1.1 augustss if (auacer_sema_codec(sc))
423 1.1 augustss return EIO;
424 1.1 augustss WRITE2(sc, ALI_CPR, val);
425 1.1 augustss #if 0
426 1.1 augustss if (ac97->num)
427 1.1 augustss reg |= ALI_CPR_ADDR_SECONDARY;
428 1.1 augustss #endif
429 1.1 augustss WRITE2(sc, ALI_CPR_ADDR, reg);
430 1.1 augustss auacer_ready_codec(sc, ALI_CSPSR_WRITE_OK);
431 1.1 augustss return 0;
432 1.1 augustss }
433 1.1 augustss
434 1.10 thorpej static int
435 1.1 augustss auacer_attach_codec(void *v, struct ac97_codec_if *cif)
436 1.1 augustss {
437 1.7 kent struct auacer_softc *sc;
438 1.1 augustss
439 1.7 kent sc = v;
440 1.1 augustss sc->codec_if = cif;
441 1.1 augustss return 0;
442 1.1 augustss }
443 1.1 augustss
444 1.10 thorpej static int
445 1.1 augustss auacer_reset_codec(void *v)
446 1.1 augustss {
447 1.7 kent struct auacer_softc *sc;
448 1.7 kent uint32_t reg;
449 1.7 kent int i;
450 1.1 augustss
451 1.7 kent sc = v;
452 1.7 kent i = 0;
453 1.1 augustss reg = READ4(sc, ALI_SCR);
454 1.1 augustss if ((reg & 2) == 0) /* Cold required */
455 1.1 augustss reg |= 2;
456 1.1 augustss else
457 1.1 augustss reg |= 1; /* Warm */
458 1.1 augustss reg &= ~0x80000000; /* ACLink on */
459 1.1 augustss WRITE4(sc, ALI_SCR, reg);
460 1.1 augustss
461 1.1 augustss while (i < 10) {
462 1.1 augustss if ((READ4(sc, ALI_INTERRUPTSR) & ALI_INT_GPIO) == 0)
463 1.1 augustss break;
464 1.1 augustss delay(50000); /* XXX */
465 1.1 augustss i++;
466 1.1 augustss }
467 1.1 augustss if (i == 10) {
468 1.1 augustss return EIO;
469 1.1 augustss }
470 1.1 augustss
471 1.1 augustss for (i = 0; i < 10; i++) {
472 1.1 augustss reg = READ4(sc, ALI_RTSR);
473 1.1 augustss if (reg & 0x80) /* primary codec */
474 1.1 augustss break;
475 1.1 augustss WRITE4(sc, ALI_RTSR, reg | 0x80);
476 1.1 augustss delay(50000); /* XXX */
477 1.1 augustss }
478 1.1 augustss
479 1.1 augustss return 0;
480 1.1 augustss }
481 1.1 augustss
482 1.1 augustss static void
483 1.1 augustss auacer_reset(struct auacer_softc *sc)
484 1.1 augustss {
485 1.1 augustss WRITE4(sc, ALI_SCR, ALI_SCR_RESET);
486 1.1 augustss WRITE4(sc, ALI_FIFOCR1, 0x83838383);
487 1.1 augustss WRITE4(sc, ALI_FIFOCR2, 0x83838383);
488 1.1 augustss WRITE4(sc, ALI_FIFOCR3, 0x83838383);
489 1.1 augustss WRITE4(sc, ALI_INTERFACECR, ALI_IF_PO); /* XXX pcm out only */
490 1.1 augustss WRITE4(sc, ALI_INTERRUPTCR, 0x00000000);
491 1.1 augustss WRITE4(sc, ALI_INTERRUPTSR, 0x00000000);
492 1.1 augustss }
493 1.1 augustss
494 1.10 thorpej static int
495 1.1 augustss auacer_query_encoding(void *v, struct audio_encoding *aep)
496 1.1 augustss {
497 1.4 kent struct auacer_softc *sc;
498 1.4 kent
499 1.1 augustss DPRINTF(ALI_DEBUG_API, ("auacer_query_encoding\n"));
500 1.4 kent sc = v;
501 1.4 kent return auconv_query_encoding(sc->sc_encodings, aep);
502 1.1 augustss }
503 1.1 augustss
504 1.10 thorpej static int
505 1.6 kent auacer_set_rate(struct auacer_softc *sc, int mode, u_int srate)
506 1.1 augustss {
507 1.1 augustss int ret;
508 1.6 kent u_int ratetmp;
509 1.1 augustss
510 1.8 augustss DPRINTF(ALI_DEBUG_API, ("auacer_set_rate: srate=%u\n", srate));
511 1.1 augustss
512 1.1 augustss ratetmp = srate;
513 1.1 augustss if (mode == AUMODE_RECORD)
514 1.1 augustss return sc->codec_if->vtbl->set_rate(sc->codec_if,
515 1.1 augustss AC97_REG_PCM_LR_ADC_RATE, &ratetmp);
516 1.1 augustss ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
517 1.1 augustss AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp);
518 1.1 augustss if (ret)
519 1.1 augustss return ret;
520 1.1 augustss ratetmp = srate;
521 1.1 augustss ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
522 1.1 augustss AC97_REG_PCM_SURR_DAC_RATE, &ratetmp);
523 1.1 augustss if (ret)
524 1.1 augustss return ret;
525 1.1 augustss ratetmp = srate;
526 1.1 augustss ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
527 1.1 augustss AC97_REG_PCM_LFE_DAC_RATE, &ratetmp);
528 1.1 augustss return ret;
529 1.1 augustss }
530 1.1 augustss
531 1.10 thorpej static int
532 1.15 christos auacer_set_params(void *v, int setmode, int usemode,
533 1.14 christos audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil,
534 1.14 christos stream_filter_list_t *rfil)
535 1.1 augustss {
536 1.7 kent struct auacer_softc *sc;
537 1.1 augustss struct audio_params *p;
538 1.6 kent stream_filter_list_t *fil;
539 1.1 augustss uint32_t control;
540 1.4 kent int mode, index;
541 1.1 augustss
542 1.1 augustss DPRINTF(ALI_DEBUG_API, ("auacer_set_params\n"));
543 1.7 kent sc = v;
544 1.1 augustss for (mode = AUMODE_RECORD; mode != -1;
545 1.1 augustss mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) {
546 1.1 augustss if ((setmode & mode) == 0)
547 1.1 augustss continue;
548 1.1 augustss
549 1.1 augustss p = mode == AUMODE_PLAY ? play : rec;
550 1.1 augustss if (p == NULL)
551 1.1 augustss continue;
552 1.1 augustss
553 1.1 augustss if ((p->sample_rate != 8000) &&
554 1.1 augustss (p->sample_rate != 11025) &&
555 1.1 augustss (p->sample_rate != 12000) &&
556 1.1 augustss (p->sample_rate != 16000) &&
557 1.1 augustss (p->sample_rate != 22050) &&
558 1.1 augustss (p->sample_rate != 24000) &&
559 1.1 augustss (p->sample_rate != 32000) &&
560 1.1 augustss (p->sample_rate != 44100) &&
561 1.1 augustss (p->sample_rate != 48000))
562 1.1 augustss return (EINVAL);
563 1.1 augustss
564 1.6 kent fil = mode == AUMODE_PLAY ? pfil : rfil;
565 1.4 kent index = auconv_set_converter(sc->sc_formats, AUACER_NFORMATS,
566 1.6 kent mode, p, TRUE, fil);
567 1.4 kent if (index < 0)
568 1.4 kent return EINVAL;
569 1.6 kent if (fil->req_size > 0)
570 1.6 kent p = &fil->filters[0].param;
571 1.6 kent /* p points HW encoding */
572 1.4 kent if (sc->sc_formats[index].frequency_type != 1
573 1.6 kent && auacer_set_rate(sc, mode, p->sample_rate))
574 1.4 kent return EINVAL;
575 1.1 augustss if (mode == AUMODE_PLAY) {
576 1.1 augustss control = READ4(sc, ALI_SCR);
577 1.1 augustss control &= ~ALI_SCR_PCM_246_MASK;
578 1.1 augustss if (p->channels == 4)
579 1.1 augustss control |= ALI_SCR_PCM_4;
580 1.1 augustss else if (p->channels == 6)
581 1.1 augustss control |= ALI_SCR_PCM_6;
582 1.1 augustss WRITE4(sc, ALI_SCR, control);
583 1.1 augustss }
584 1.1 augustss }
585 1.1 augustss
586 1.1 augustss return (0);
587 1.1 augustss }
588 1.1 augustss
589 1.10 thorpej static int
590 1.15 christos auacer_round_blocksize(void *v, int blk, int mode,
591 1.15 christos const audio_params_t *param)
592 1.1 augustss {
593 1.1 augustss
594 1.7 kent return blk & ~0x3f; /* keep good alignment */
595 1.1 augustss }
596 1.1 augustss
597 1.1 augustss static void
598 1.1 augustss auacer_halt(struct auacer_softc *sc, struct auacer_chan *chan)
599 1.1 augustss {
600 1.1 augustss uint32_t val;
601 1.7 kent uint8_t port;
602 1.1 augustss uint32_t slot;
603 1.1 augustss
604 1.7 kent port = chan->port;
605 1.1 augustss DPRINTF(ALI_DEBUG_API, ("auacer_halt: port=0x%x\n", port));
606 1.1 augustss chan->intr = 0;
607 1.1 augustss
608 1.1 augustss slot = ALI_PORT2SLOT(port);
609 1.1 augustss
610 1.1 augustss val = READ4(sc, ALI_DMACR);
611 1.1 augustss val |= 1 << (slot+16); /* pause */
612 1.1 augustss val &= ~(1 << slot); /* no start */
613 1.1 augustss WRITE4(sc, ALI_DMACR, val);
614 1.1 augustss WRITE1(sc, port + ALI_OFF_CR, 0);
615 1.1 augustss while (READ1(sc, port + ALI_OFF_CR))
616 1.1 augustss ;
617 1.1 augustss /* reset whole DMA things */
618 1.1 augustss WRITE1(sc, port + ALI_OFF_CR, ALI_CR_RR);
619 1.1 augustss /* clear interrupts */
620 1.1 augustss WRITE1(sc, port + ALI_OFF_SR, READ1(sc, port+ALI_OFF_SR) | ALI_SR_W1TC);
621 1.1 augustss WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(port));
622 1.1 augustss }
623 1.1 augustss
624 1.10 thorpej static int
625 1.1 augustss auacer_halt_output(void *v)
626 1.1 augustss {
627 1.7 kent struct auacer_softc *sc;
628 1.1 augustss
629 1.1 augustss DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_output\n"));
630 1.7 kent sc = v;
631 1.1 augustss auacer_halt(sc, &sc->sc_pcmo);
632 1.1 augustss
633 1.7 kent return 0;
634 1.1 augustss }
635 1.1 augustss
636 1.10 thorpej static int
637 1.15 christos auacer_halt_input(void *v)
638 1.1 augustss {
639 1.1 augustss DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_input\n"));
640 1.1 augustss
641 1.7 kent return 0;
642 1.1 augustss }
643 1.1 augustss
644 1.10 thorpej static int
645 1.1 augustss auacer_getdev(void *v, struct audio_device *adp)
646 1.1 augustss {
647 1.7 kent struct auacer_softc *sc;
648 1.1 augustss
649 1.1 augustss DPRINTF(ALI_DEBUG_API, ("auacer_getdev\n"));
650 1.7 kent sc = v;
651 1.1 augustss *adp = sc->sc_audev;
652 1.7 kent return 0;
653 1.1 augustss }
654 1.1 augustss
655 1.10 thorpej static int
656 1.1 augustss auacer_set_port(void *v, mixer_ctrl_t *cp)
657 1.1 augustss {
658 1.7 kent struct auacer_softc *sc;
659 1.1 augustss
660 1.1 augustss DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_set_port\n"));
661 1.7 kent sc = v;
662 1.7 kent return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp);
663 1.1 augustss }
664 1.1 augustss
665 1.10 thorpej static int
666 1.1 augustss auacer_get_port(void *v, mixer_ctrl_t *cp)
667 1.1 augustss {
668 1.7 kent struct auacer_softc *sc;
669 1.1 augustss
670 1.1 augustss DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_get_port\n"));
671 1.7 kent sc = v;
672 1.7 kent return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp);
673 1.1 augustss }
674 1.1 augustss
675 1.10 thorpej static int
676 1.1 augustss auacer_query_devinfo(void *v, mixer_devinfo_t *dp)
677 1.1 augustss {
678 1.7 kent struct auacer_softc *sc;
679 1.1 augustss
680 1.1 augustss DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_query_devinfo\n"));
681 1.7 kent sc = v;
682 1.7 kent return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp);
683 1.1 augustss }
684 1.1 augustss
685 1.10 thorpej static void *
686 1.29 jmcneill auacer_allocm(void *v, int direction, size_t size)
687 1.1 augustss {
688 1.7 kent struct auacer_softc *sc;
689 1.1 augustss struct auacer_dma *p;
690 1.1 augustss int error;
691 1.1 augustss
692 1.1 augustss if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX))
693 1.7 kent return NULL;
694 1.1 augustss
695 1.29 jmcneill p = kmem_zalloc(sizeof(*p), KM_SLEEP);
696 1.7 kent sc = v;
697 1.1 augustss error = auacer_allocmem(sc, size, 0, p);
698 1.1 augustss if (error) {
699 1.29 jmcneill kmem_free(p, sizeof(*p));
700 1.7 kent return NULL;
701 1.1 augustss }
702 1.1 augustss
703 1.1 augustss p->next = sc->sc_dmas;
704 1.1 augustss sc->sc_dmas = p;
705 1.1 augustss
706 1.7 kent return KERNADDR(p);
707 1.1 augustss }
708 1.1 augustss
709 1.10 thorpej static void
710 1.29 jmcneill auacer_freem(void *v, void *ptr, size_t size)
711 1.1 augustss {
712 1.7 kent struct auacer_softc *sc;
713 1.1 augustss struct auacer_dma *p, **pp;
714 1.1 augustss
715 1.7 kent sc = v;
716 1.1 augustss for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) {
717 1.1 augustss if (KERNADDR(p) == ptr) {
718 1.1 augustss auacer_freemem(sc, p);
719 1.1 augustss *pp = p->next;
720 1.29 jmcneill kmem_free(p, sizeof(*p));
721 1.1 augustss return;
722 1.1 augustss }
723 1.1 augustss }
724 1.1 augustss }
725 1.1 augustss
726 1.10 thorpej static size_t
727 1.15 christos auacer_round_buffersize(void *v, int direction, size_t size)
728 1.1 augustss {
729 1.1 augustss
730 1.1 augustss if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX))
731 1.1 augustss size = ALI_DMALIST_MAX * ALI_DMASEG_MAX;
732 1.1 augustss
733 1.1 augustss return size;
734 1.1 augustss }
735 1.1 augustss
736 1.10 thorpej static paddr_t
737 1.1 augustss auacer_mappage(void *v, void *mem, off_t off, int prot)
738 1.1 augustss {
739 1.7 kent struct auacer_softc *sc;
740 1.1 augustss struct auacer_dma *p;
741 1.1 augustss
742 1.1 augustss if (off < 0)
743 1.7 kent return -1;
744 1.7 kent sc = v;
745 1.1 augustss for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next)
746 1.7 kent continue;
747 1.7 kent if (p == NULL)
748 1.7 kent return -1;
749 1.7 kent return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs,
750 1.7 kent off, prot, BUS_DMA_WAITOK);
751 1.1 augustss }
752 1.1 augustss
753 1.10 thorpej static int
754 1.1 augustss auacer_get_props(void *v)
755 1.1 augustss {
756 1.7 kent struct auacer_softc *sc;
757 1.1 augustss int props;
758 1.1 augustss
759 1.7 kent sc = v;
760 1.1 augustss props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX;
761 1.1 augustss /*
762 1.1 augustss * Even if the codec is fixed-rate, set_param() succeeds for any sample
763 1.1 augustss * rate because of aurateconv. Applications can't know what rate the
764 1.1 augustss * device can process in the case of mmap().
765 1.1 augustss */
766 1.3 kent if (!AC97_IS_FIXED_RATE(sc->codec_if))
767 1.1 augustss props |= AUDIO_PROP_MMAP;
768 1.1 augustss return props;
769 1.1 augustss }
770 1.1 augustss
771 1.1 augustss static void
772 1.29 jmcneill auacer_get_locks(void *v, kmutex_t **intr, kmutex_t **proc)
773 1.29 jmcneill {
774 1.29 jmcneill struct auacer_softc *sc;
775 1.29 jmcneill
776 1.29 jmcneill sc = v;
777 1.29 jmcneill *intr = &sc->sc_intr_lock;
778 1.29 jmcneill *proc = &sc->sc_lock;
779 1.29 jmcneill }
780 1.29 jmcneill
781 1.29 jmcneill static void
782 1.1 augustss auacer_add_entry(struct auacer_chan *chan)
783 1.1 augustss {
784 1.1 augustss struct auacer_dmalist *q;
785 1.1 augustss
786 1.1 augustss q = &chan->dmalist[chan->ptr];
787 1.1 augustss
788 1.1 augustss DPRINTF(ALI_DEBUG_INTR,
789 1.1 augustss ("auacer_add_entry: %p = %x @ 0x%x\n",
790 1.1 augustss q, chan->blksize / 2, chan->p));
791 1.1 augustss
792 1.1 augustss q->base = htole32(chan->p);
793 1.1 augustss q->len = htole32((chan->blksize / ALI_SAMPLE_SIZE) | ALI_DMAF_IOC);
794 1.1 augustss chan->p += chan->blksize;
795 1.1 augustss if (chan->p >= chan->end)
796 1.1 augustss chan->p = chan->start;
797 1.7 kent
798 1.1 augustss if (++chan->ptr >= ALI_DMALIST_MAX)
799 1.1 augustss chan->ptr = 0;
800 1.1 augustss }
801 1.1 augustss
802 1.1 augustss static void
803 1.1 augustss auacer_upd_chan(struct auacer_softc *sc, struct auacer_chan *chan)
804 1.1 augustss {
805 1.1 augustss uint32_t sts;
806 1.1 augustss uint32_t civ;
807 1.1 augustss
808 1.1 augustss sts = READ2(sc, chan->port + ALI_OFF_SR);
809 1.1 augustss /* intr ack */
810 1.1 augustss WRITE2(sc, chan->port + ALI_OFF_SR, sts & ALI_SR_W1TC);
811 1.1 augustss WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(chan->port));
812 1.1 augustss
813 1.1 augustss DPRINTF(ALI_DEBUG_INTR, ("auacer_upd_chan: sts=0x%x\n", sts));
814 1.1 augustss
815 1.1 augustss if (sts & ALI_SR_DMA_INT_FIFO) {
816 1.1 augustss printf("%s: fifo underrun # %u\n",
817 1.31 chs device_xname(sc->sc_dev), ++chan->fifoe);
818 1.1 augustss }
819 1.1 augustss
820 1.1 augustss civ = READ1(sc, chan->port + ALI_OFF_CIV);
821 1.7 kent
822 1.1 augustss DPRINTF(ALI_DEBUG_INTR,("auacer_intr: civ=%u ptr=%u\n",civ,chan->ptr));
823 1.7 kent
824 1.1 augustss /* XXX */
825 1.1 augustss while (chan->ptr != civ) {
826 1.1 augustss auacer_add_entry(chan);
827 1.1 augustss }
828 1.1 augustss
829 1.1 augustss WRITE1(sc, chan->port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK);
830 1.1 augustss
831 1.1 augustss while (chan->ack != civ) {
832 1.1 augustss if (chan->intr) {
833 1.1 augustss DPRINTF(ALI_DEBUG_INTR,("auacer_upd_chan: callback\n"));
834 1.1 augustss chan->intr(chan->arg);
835 1.1 augustss }
836 1.1 augustss chan->ack++;
837 1.1 augustss if (chan->ack >= ALI_DMALIST_MAX)
838 1.1 augustss chan->ack = 0;
839 1.1 augustss }
840 1.1 augustss }
841 1.1 augustss
842 1.10 thorpej static int
843 1.1 augustss auacer_intr(void *v)
844 1.1 augustss {
845 1.7 kent struct auacer_softc *sc;
846 1.1 augustss int ret, intrs;
847 1.1 augustss
848 1.7 kent sc = v;
849 1.29 jmcneill
850 1.29 jmcneill DPRINTF(ALI_DEBUG_INTR, ("auacer_intr: intrs=0x%x\n",
851 1.29 jmcneill READ4(sc, ALI_INTERRUPTSR)));
852 1.29 jmcneill
853 1.29 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
854 1.1 augustss intrs = READ4(sc, ALI_INTERRUPTSR);
855 1.1 augustss ret = 0;
856 1.1 augustss if (intrs & ALI_INT_PCMOUT) {
857 1.1 augustss auacer_upd_chan(sc, &sc->sc_pcmo);
858 1.1 augustss ret++;
859 1.1 augustss }
860 1.29 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
861 1.1 augustss
862 1.1 augustss return ret != 0;
863 1.1 augustss }
864 1.1 augustss
865 1.1 augustss static void
866 1.1 augustss auacer_setup_chan(struct auacer_softc *sc, struct auacer_chan *chan,
867 1.1 augustss uint32_t start, uint32_t size, uint32_t blksize,
868 1.1 augustss void (*intr)(void *), void *arg)
869 1.1 augustss {
870 1.1 augustss uint32_t port, slot;
871 1.1 augustss uint32_t offs, val;
872 1.1 augustss
873 1.1 augustss chan->start = start;
874 1.1 augustss chan->ptr = 0;
875 1.1 augustss chan->p = chan->start;
876 1.1 augustss chan->end = chan->start + size;
877 1.1 augustss chan->blksize = blksize;
878 1.1 augustss chan->ack = 0;
879 1.1 augustss chan->intr = intr;
880 1.1 augustss chan->arg = arg;
881 1.1 augustss
882 1.1 augustss auacer_add_entry(chan);
883 1.1 augustss auacer_add_entry(chan);
884 1.1 augustss
885 1.1 augustss port = chan->port;
886 1.1 augustss slot = ALI_PORT2SLOT(port);
887 1.1 augustss
888 1.1 augustss WRITE1(sc, port + ALI_OFF_CIV, 0);
889 1.1 augustss WRITE1(sc, port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK);
890 1.1 augustss offs = (char *)chan->dmalist - (char *)sc->sc_cdata;
891 1.1 augustss WRITE4(sc, port + ALI_OFF_BDBAR, sc->sc_cddma + offs);
892 1.1 augustss WRITE1(sc, port + ALI_OFF_CR,
893 1.1 augustss ALI_CR_IOCE | ALI_CR_FEIE | ALI_CR_LVBIE | ALI_CR_RPBM);
894 1.1 augustss val = READ4(sc, ALI_DMACR);
895 1.1 augustss val &= ~(1 << (slot+16)); /* no pause */
896 1.1 augustss val |= 1 << slot; /* start */
897 1.1 augustss WRITE4(sc, ALI_DMACR, val);
898 1.1 augustss }
899 1.1 augustss
900 1.10 thorpej static int
901 1.1 augustss auacer_trigger_output(void *v, void *start, void *end, int blksize,
902 1.15 christos void (*intr)(void *), void *arg, const audio_params_t *param)
903 1.1 augustss {
904 1.7 kent struct auacer_softc *sc;
905 1.1 augustss struct auacer_dma *p;
906 1.1 augustss uint32_t size;
907 1.1 augustss
908 1.1 augustss DPRINTF(ALI_DEBUG_DMA,
909 1.1 augustss ("auacer_trigger_output(%p, %p, %d, %p, %p, %p)\n",
910 1.1 augustss start, end, blksize, intr, arg, param));
911 1.7 kent sc = v;
912 1.1 augustss for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next)
913 1.7 kent continue;
914 1.1 augustss if (!p) {
915 1.1 augustss printf("auacer_trigger_output: bad addr %p\n", start);
916 1.1 augustss return (EINVAL);
917 1.1 augustss }
918 1.1 augustss
919 1.1 augustss size = (char *)end - (char *)start;
920 1.1 augustss auacer_setup_chan(sc, &sc->sc_pcmo, DMAADDR(p), size, blksize,
921 1.1 augustss intr, arg);
922 1.1 augustss
923 1.1 augustss return 0;
924 1.1 augustss }
925 1.1 augustss
926 1.10 thorpej static int
927 1.15 christos auacer_trigger_input(void *v, void *start, void *end,
928 1.15 christos int blksize, void (*intr)(void *), void *arg,
929 1.15 christos const audio_params_t *param)
930 1.1 augustss {
931 1.7 kent return EINVAL;
932 1.1 augustss }
933 1.1 augustss
934 1.10 thorpej static int
935 1.1 augustss auacer_allocmem(struct auacer_softc *sc, size_t size, size_t align,
936 1.1 augustss struct auacer_dma *p)
937 1.1 augustss {
938 1.1 augustss int error;
939 1.1 augustss
940 1.1 augustss p->size = size;
941 1.1 augustss error = bus_dmamem_alloc(sc->dmat, p->size, align, 0,
942 1.1 augustss p->segs, sizeof(p->segs)/sizeof(p->segs[0]),
943 1.29 jmcneill &p->nsegs, BUS_DMA_WAITOK);
944 1.1 augustss if (error)
945 1.7 kent return error;
946 1.1 augustss
947 1.1 augustss error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size,
948 1.29 jmcneill &p->addr, BUS_DMA_WAITOK|sc->sc_dmamap_flags);
949 1.1 augustss if (error)
950 1.1 augustss goto free;
951 1.1 augustss
952 1.1 augustss error = bus_dmamap_create(sc->dmat, p->size, 1, p->size,
953 1.29 jmcneill 0, BUS_DMA_WAITOK, &p->map);
954 1.1 augustss if (error)
955 1.1 augustss goto unmap;
956 1.1 augustss
957 1.1 augustss error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL,
958 1.29 jmcneill BUS_DMA_WAITOK);
959 1.1 augustss if (error)
960 1.1 augustss goto destroy;
961 1.1 augustss return (0);
962 1.1 augustss
963 1.1 augustss destroy:
964 1.1 augustss bus_dmamap_destroy(sc->dmat, p->map);
965 1.1 augustss unmap:
966 1.1 augustss bus_dmamem_unmap(sc->dmat, p->addr, p->size);
967 1.1 augustss free:
968 1.1 augustss bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
969 1.7 kent return error;
970 1.1 augustss }
971 1.1 augustss
972 1.10 thorpej static int
973 1.1 augustss auacer_freemem(struct auacer_softc *sc, struct auacer_dma *p)
974 1.1 augustss {
975 1.1 augustss
976 1.1 augustss bus_dmamap_unload(sc->dmat, p->map);
977 1.1 augustss bus_dmamap_destroy(sc->dmat, p->map);
978 1.1 augustss bus_dmamem_unmap(sc->dmat, p->addr, p->size);
979 1.1 augustss bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
980 1.7 kent return 0;
981 1.1 augustss }
982 1.1 augustss
983 1.10 thorpej static int
984 1.1 augustss auacer_alloc_cdata(struct auacer_softc *sc)
985 1.1 augustss {
986 1.1 augustss bus_dma_segment_t seg;
987 1.1 augustss int error, rseg;
988 1.1 augustss
989 1.1 augustss /*
990 1.1 augustss * Allocate the control data structure, and create and load the
991 1.1 augustss * DMA map for it.
992 1.1 augustss */
993 1.1 augustss if ((error = bus_dmamem_alloc(sc->dmat,
994 1.1 augustss sizeof(struct auacer_cdata),
995 1.1 augustss PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) {
996 1.31 chs aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n",
997 1.20 cegger error);
998 1.1 augustss goto fail_0;
999 1.1 augustss }
1000 1.1 augustss
1001 1.1 augustss if ((error = bus_dmamem_map(sc->dmat, &seg, rseg,
1002 1.1 augustss sizeof(struct auacer_cdata),
1003 1.16 christos (void **) &sc->sc_cdata,
1004 1.1 augustss sc->sc_dmamap_flags)) != 0) {
1005 1.31 chs aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n",
1006 1.20 cegger error);
1007 1.1 augustss goto fail_1;
1008 1.1 augustss }
1009 1.1 augustss
1010 1.1 augustss if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auacer_cdata), 1,
1011 1.1 augustss sizeof(struct auacer_cdata), 0, 0,
1012 1.1 augustss &sc->sc_cddmamap)) != 0) {
1013 1.31 chs aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, "
1014 1.20 cegger "error = %d\n", error);
1015 1.1 augustss goto fail_2;
1016 1.1 augustss }
1017 1.1 augustss
1018 1.1 augustss if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap,
1019 1.1 augustss sc->sc_cdata, sizeof(struct auacer_cdata),
1020 1.1 augustss NULL, 0)) != 0) {
1021 1.31 chs aprint_error_dev(sc->sc_dev, "unable to load control data DMA map, "
1022 1.20 cegger "error = %d\n", error);
1023 1.1 augustss goto fail_3;
1024 1.1 augustss }
1025 1.1 augustss
1026 1.7 kent return 0;
1027 1.1 augustss
1028 1.1 augustss fail_3:
1029 1.1 augustss bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap);
1030 1.1 augustss fail_2:
1031 1.16 christos bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata,
1032 1.1 augustss sizeof(struct auacer_cdata));
1033 1.1 augustss fail_1:
1034 1.1 augustss bus_dmamem_free(sc->dmat, &seg, rseg);
1035 1.1 augustss fail_0:
1036 1.7 kent return error;
1037 1.1 augustss }
1038 1.1 augustss
1039 1.18 jmcneill static bool
1040 1.27 dyoung auacer_resume(device_t dv, const pmf_qual_t *qual)
1041 1.1 augustss {
1042 1.18 jmcneill struct auacer_softc *sc = device_private(dv);
1043 1.18 jmcneill
1044 1.29 jmcneill mutex_enter(&sc->sc_lock);
1045 1.29 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
1046 1.18 jmcneill auacer_reset_codec(sc);
1047 1.29 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
1048 1.18 jmcneill delay(1000);
1049 1.18 jmcneill sc->codec_if->vtbl->restore_ports(sc->codec_if);
1050 1.29 jmcneill mutex_exit(&sc->sc_lock);
1051 1.1 augustss
1052 1.18 jmcneill return true;
1053 1.1 augustss }
1054