auacer.c revision 1.38 1 1.38 isaki /* $NetBSD: auacer.c,v 1.38 2019/06/08 08:02:38 isaki Exp $ */
2 1.1 augustss
3 1.1 augustss /*-
4 1.29 jmcneill * Copyright (c) 2004, 2008 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.1 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.1 augustss * by Lennart Augustsson.
9 1.1 augustss *
10 1.1 augustss * Redistribution and use in source and binary forms, with or without
11 1.1 augustss * modification, are permitted provided that the following conditions
12 1.1 augustss * are met:
13 1.1 augustss * 1. Redistributions of source code must retain the above copyright
14 1.1 augustss * notice, this list of conditions and the following disclaimer.
15 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 augustss * notice, this list of conditions and the following disclaimer in the
17 1.1 augustss * documentation and/or other materials provided with the distribution.
18 1.1 augustss *
19 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
30 1.1 augustss */
31 1.1 augustss
32 1.1 augustss /*
33 1.1 augustss * Acer Labs M5455 audio driver
34 1.1 augustss *
35 1.5 augustss * Acer provides data sheets after signing an NDA, so this is guess work.
36 1.1 augustss * The chip behaves somewhat like the Intel i8x0, so this driver
37 1.1 augustss * is loosely based on the auich driver. Additional information taken from
38 1.1 augustss * the ALSA intel8x0.c driver (which handles M5455 as well).
39 1.1 augustss *
40 1.1 augustss * As an historical note one can observe that the auich driver borrows
41 1.1 augustss * lot from the first NetBSD PCI audio driver, the eap driver. But this
42 1.1 augustss * is not attributed anywhere.
43 1.1 augustss */
44 1.1 augustss
45 1.1 augustss
46 1.1 augustss #include <sys/cdefs.h>
47 1.38 isaki __KERNEL_RCSID(0, "$NetBSD: auacer.c,v 1.38 2019/06/08 08:02:38 isaki Exp $");
48 1.1 augustss
49 1.1 augustss #include <sys/param.h>
50 1.1 augustss #include <sys/systm.h>
51 1.1 augustss #include <sys/kernel.h>
52 1.29 jmcneill #include <sys/kmem.h>
53 1.1 augustss #include <sys/device.h>
54 1.1 augustss #include <sys/fcntl.h>
55 1.1 augustss #include <sys/proc.h>
56 1.1 augustss
57 1.1 augustss #include <dev/pci/pcidevs.h>
58 1.1 augustss #include <dev/pci/pcivar.h>
59 1.1 augustss #include <dev/pci/auacerreg.h>
60 1.1 augustss
61 1.1 augustss #include <sys/audioio.h>
62 1.37 isaki #include <dev/audio/audio_if.h>
63 1.1 augustss
64 1.17 ad #include <sys/bus.h>
65 1.1 augustss
66 1.1 augustss #include <dev/ic/ac97reg.h>
67 1.1 augustss #include <dev/ic/ac97var.h>
68 1.1 augustss
69 1.1 augustss struct auacer_dma {
70 1.1 augustss bus_dmamap_t map;
71 1.16 christos void *addr;
72 1.1 augustss bus_dma_segment_t segs[1];
73 1.1 augustss int nsegs;
74 1.1 augustss size_t size;
75 1.1 augustss struct auacer_dma *next;
76 1.1 augustss };
77 1.1 augustss
78 1.1 augustss #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr)
79 1.1 augustss #define KERNADDR(p) ((void *)((p)->addr))
80 1.1 augustss
81 1.1 augustss struct auacer_cdata {
82 1.1 augustss struct auacer_dmalist ic_dmalist_pcmo[ALI_DMALIST_MAX];
83 1.1 augustss };
84 1.1 augustss
85 1.1 augustss struct auacer_chan {
86 1.1 augustss uint32_t ptr;
87 1.1 augustss uint32_t start, p, end;
88 1.1 augustss uint32_t blksize, fifoe;
89 1.1 augustss uint32_t ack;
90 1.1 augustss uint32_t port;
91 1.1 augustss struct auacer_dmalist *dmalist;
92 1.1 augustss void (*intr)(void *);
93 1.1 augustss void *arg;
94 1.1 augustss };
95 1.1 augustss
96 1.1 augustss struct auacer_softc {
97 1.31 chs device_t sc_dev;
98 1.1 augustss void *sc_ih;
99 1.29 jmcneill kmutex_t sc_lock;
100 1.29 jmcneill kmutex_t sc_intr_lock;
101 1.1 augustss
102 1.1 augustss audio_device_t sc_audev;
103 1.1 augustss
104 1.1 augustss bus_space_tag_t iot;
105 1.1 augustss bus_space_handle_t mix_ioh;
106 1.1 augustss bus_space_handle_t aud_ioh;
107 1.1 augustss bus_dma_tag_t dmat;
108 1.1 augustss
109 1.1 augustss struct ac97_codec_if *codec_if;
110 1.1 augustss struct ac97_host_if host_if;
111 1.1 augustss
112 1.1 augustss /* DMA scatter-gather lists. */
113 1.1 augustss bus_dmamap_t sc_cddmamap;
114 1.1 augustss #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
115 1.1 augustss
116 1.1 augustss struct auacer_cdata *sc_cdata;
117 1.1 augustss
118 1.1 augustss struct auacer_chan sc_pcmo;
119 1.1 augustss
120 1.1 augustss struct auacer_dma *sc_dmas;
121 1.1 augustss
122 1.1 augustss pci_chipset_tag_t sc_pc;
123 1.1 augustss pcitag_t sc_pt;
124 1.1 augustss
125 1.1 augustss int sc_dmamap_flags;
126 1.1 augustss
127 1.4 kent #define AUACER_NFORMATS 3
128 1.4 kent struct audio_format sc_formats[AUACER_NFORMATS];
129 1.1 augustss };
130 1.1 augustss
131 1.1 augustss #define READ1(sc, a) bus_space_read_1(sc->iot, sc->aud_ioh, a)
132 1.1 augustss #define READ2(sc, a) bus_space_read_2(sc->iot, sc->aud_ioh, a)
133 1.1 augustss #define READ4(sc, a) bus_space_read_4(sc->iot, sc->aud_ioh, a)
134 1.1 augustss #define WRITE1(sc, a, v) bus_space_write_1(sc->iot, sc->aud_ioh, a, v)
135 1.1 augustss #define WRITE2(sc, a, v) bus_space_write_2(sc->iot, sc->aud_ioh, a, v)
136 1.1 augustss #define WRITE4(sc, a, v) bus_space_write_4(sc->iot, sc->aud_ioh, a, v)
137 1.1 augustss
138 1.1 augustss /* Debug */
139 1.1 augustss #ifdef AUACER_DEBUG
140 1.1 augustss #define DPRINTF(l,x) do { if (auacer_debug & (l)) printf x; } while(0)
141 1.1 augustss int auacer_debug = 0;
142 1.1 augustss #define ALI_DEBUG_CODECIO 0x0001
143 1.1 augustss #define ALI_DEBUG_DMA 0x0002
144 1.1 augustss #define ALI_DEBUG_INTR 0x0004
145 1.1 augustss #define ALI_DEBUG_API 0x0008
146 1.1 augustss #define ALI_DEBUG_MIXERAPI 0x0010
147 1.1 augustss #else
148 1.1 augustss #define DPRINTF(x,y) /* nothing */
149 1.1 augustss #endif
150 1.1 augustss
151 1.10 thorpej static int auacer_intr(void *);
152 1.1 augustss
153 1.37 isaki static int auacer_query_format(void *, audio_format_query_t *);
154 1.37 isaki static int auacer_set_format(void *, int,
155 1.37 isaki const audio_params_t *, const audio_params_t *,
156 1.37 isaki audio_filter_reg_t *, audio_filter_reg_t *);
157 1.10 thorpej static int auacer_round_blocksize(void *, int, int,
158 1.10 thorpej const audio_params_t *);
159 1.10 thorpej static int auacer_halt_output(void *);
160 1.10 thorpej static int auacer_halt_input(void *);
161 1.10 thorpej static int auacer_getdev(void *, struct audio_device *);
162 1.10 thorpej static int auacer_set_port(void *, mixer_ctrl_t *);
163 1.10 thorpej static int auacer_get_port(void *, mixer_ctrl_t *);
164 1.10 thorpej static int auacer_query_devinfo(void *, mixer_devinfo_t *);
165 1.29 jmcneill static void *auacer_allocm(void *, int, size_t);
166 1.29 jmcneill static void auacer_freem(void *, void *, size_t);
167 1.10 thorpej static size_t auacer_round_buffersize(void *, int, size_t);
168 1.10 thorpej static int auacer_get_props(void *);
169 1.10 thorpej static int auacer_trigger_output(void *, void *, void *, int,
170 1.10 thorpej void (*)(void *), void *,
171 1.10 thorpej const audio_params_t *);
172 1.10 thorpej static int auacer_trigger_input(void *, void *, void *, int,
173 1.10 thorpej void (*)(void *), void *,
174 1.10 thorpej const audio_params_t *);
175 1.10 thorpej
176 1.10 thorpej static int auacer_alloc_cdata(struct auacer_softc *);
177 1.10 thorpej
178 1.10 thorpej static int auacer_allocmem(struct auacer_softc *, size_t, size_t,
179 1.10 thorpej struct auacer_dma *);
180 1.10 thorpej static int auacer_freemem(struct auacer_softc *, struct auacer_dma *);
181 1.29 jmcneill static void auacer_get_locks(void *, kmutex_t **, kmutex_t **);
182 1.1 augustss
183 1.27 dyoung static bool auacer_resume(device_t, const pmf_qual_t *);
184 1.10 thorpej static int auacer_set_rate(struct auacer_softc *, int, u_int);
185 1.1 augustss
186 1.1 augustss static void auacer_reset(struct auacer_softc *sc);
187 1.1 augustss
188 1.34 maxv static const struct audio_hw_if auacer_hw_if = {
189 1.37 isaki .query_format = auacer_query_format,
190 1.37 isaki .set_format = auacer_set_format,
191 1.36 isaki .round_blocksize = auacer_round_blocksize,
192 1.36 isaki .halt_output = auacer_halt_output,
193 1.36 isaki .halt_input = auacer_halt_input,
194 1.36 isaki .getdev = auacer_getdev,
195 1.36 isaki .set_port = auacer_set_port,
196 1.36 isaki .get_port = auacer_get_port,
197 1.36 isaki .query_devinfo = auacer_query_devinfo,
198 1.36 isaki .allocm = auacer_allocm,
199 1.36 isaki .freem = auacer_freem,
200 1.36 isaki .round_buffersize = auacer_round_buffersize,
201 1.36 isaki .get_props = auacer_get_props,
202 1.36 isaki .trigger_output = auacer_trigger_output,
203 1.36 isaki .trigger_input = auacer_trigger_input,
204 1.36 isaki .get_locks = auacer_get_locks,
205 1.1 augustss };
206 1.1 augustss
207 1.4 kent #define AUACER_FORMATS_4CH 1
208 1.4 kent #define AUACER_FORMATS_6CH 2
209 1.37 isaki #define AUACER_FORMAT(aumode, ch, chmask) \
210 1.37 isaki { \
211 1.37 isaki .mode = (aumode), \
212 1.37 isaki .encoding = AUDIO_ENCODING_SLINEAR_LE, \
213 1.37 isaki .validbits = 16, \
214 1.37 isaki .precision = 16, \
215 1.37 isaki .channels = (ch), \
216 1.37 isaki .channel_mask = (chmask), \
217 1.37 isaki .frequency_type = 9, \
218 1.37 isaki .frequency = { 8000, 11025, 12000, 16000, 22050, \
219 1.37 isaki 24000, 32000, 44100, 48000, }, \
220 1.37 isaki }
221 1.4 kent static const struct audio_format auacer_formats[AUACER_NFORMATS] = {
222 1.37 isaki AUACER_FORMAT(AUMODE_PLAY | AUMODE_RECORD, 2, AUFMT_STEREO),
223 1.37 isaki AUACER_FORMAT(AUMODE_PLAY , 4, AUFMT_SURROUND4),
224 1.37 isaki AUACER_FORMAT(AUMODE_PLAY , 6, AUFMT_DOLBY_5_1),
225 1.4 kent };
226 1.4 kent
227 1.10 thorpej static int auacer_attach_codec(void *, struct ac97_codec_if *);
228 1.10 thorpej static int auacer_read_codec(void *, uint8_t, uint16_t *);
229 1.10 thorpej static int auacer_write_codec(void *, uint8_t, uint16_t);
230 1.10 thorpej static int auacer_reset_codec(void *);
231 1.1 augustss
232 1.10 thorpej static int
233 1.23 cegger auacer_match(device_t parent, cfdata_t match, void *aux)
234 1.1 augustss {
235 1.7 kent struct pci_attach_args *pa;
236 1.1 augustss
237 1.7 kent pa = (struct pci_attach_args *)aux;
238 1.1 augustss if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI &&
239 1.1 augustss PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M5455)
240 1.1 augustss return 1;
241 1.1 augustss return 0;
242 1.1 augustss }
243 1.1 augustss
244 1.10 thorpej static void
245 1.23 cegger auacer_attach(device_t parent, device_t self, void *aux)
246 1.1 augustss {
247 1.7 kent struct auacer_softc *sc;
248 1.7 kent struct pci_attach_args *pa;
249 1.1 augustss pci_intr_handle_t ih;
250 1.1 augustss bus_size_t aud_size;
251 1.1 augustss pcireg_t v;
252 1.1 augustss const char *intrstr;
253 1.4 kent int i;
254 1.32 christos char intrbuf[PCI_INTRSTR_LEN];
255 1.1 augustss
256 1.24 cegger sc = device_private(self);
257 1.31 chs sc->sc_dev = self;
258 1.7 kent pa = aux;
259 1.1 augustss aprint_normal(": Acer Labs M5455 Audio controller\n");
260 1.1 augustss
261 1.1 augustss if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, &sc->iot,
262 1.1 augustss &sc->aud_ioh, NULL, &aud_size)) {
263 1.1 augustss aprint_error(": can't map i/o space\n");
264 1.1 augustss return;
265 1.1 augustss }
266 1.1 augustss
267 1.1 augustss sc->sc_pc = pa->pa_pc;
268 1.1 augustss sc->sc_pt = pa->pa_tag;
269 1.1 augustss sc->dmat = pa->pa_dmat;
270 1.1 augustss
271 1.1 augustss sc->sc_dmamap_flags = BUS_DMA_COHERENT; /* XXX remove */
272 1.1 augustss
273 1.29 jmcneill mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
274 1.30 mrg mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO);
275 1.29 jmcneill
276 1.1 augustss /* enable bus mastering */
277 1.1 augustss v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
278 1.1 augustss pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
279 1.1 augustss v | PCI_COMMAND_MASTER_ENABLE);
280 1.1 augustss
281 1.1 augustss /* Map and establish the interrupt. */
282 1.1 augustss if (pci_intr_map(pa, &ih)) {
283 1.31 chs aprint_error_dev(sc->sc_dev, "can't map interrupt\n");
284 1.29 jmcneill mutex_destroy(&sc->sc_lock);
285 1.29 jmcneill mutex_destroy(&sc->sc_intr_lock);
286 1.1 augustss return;
287 1.1 augustss }
288 1.32 christos intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf));
289 1.35 jdolecek sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_AUDIO,
290 1.35 jdolecek auacer_intr, sc, device_xname(self));
291 1.1 augustss if (sc->sc_ih == NULL) {
292 1.31 chs aprint_error_dev(sc->sc_dev, "can't establish interrupt");
293 1.1 augustss if (intrstr != NULL)
294 1.25 njoly aprint_error(" at %s", intrstr);
295 1.25 njoly aprint_error("\n");
296 1.29 jmcneill mutex_destroy(&sc->sc_lock);
297 1.29 jmcneill mutex_destroy(&sc->sc_intr_lock);
298 1.1 augustss return;
299 1.1 augustss }
300 1.31 chs aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
301 1.1 augustss
302 1.1 augustss strlcpy(sc->sc_audev.name, "M5455 AC97", MAX_AUDIO_DEV_LEN);
303 1.1 augustss snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN,
304 1.1 augustss "0x%02x", PCI_REVISION(pa->pa_class));
305 1.31 chs strlcpy(sc->sc_audev.config, device_xname(sc->sc_dev), MAX_AUDIO_DEV_LEN);
306 1.1 augustss
307 1.1 augustss /* Set up DMA lists. */
308 1.1 augustss auacer_alloc_cdata(sc);
309 1.1 augustss sc->sc_pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo;
310 1.1 augustss sc->sc_pcmo.ptr = 0;
311 1.1 augustss sc->sc_pcmo.port = ALI_BASE_PO;
312 1.1 augustss
313 1.1 augustss DPRINTF(ALI_DEBUG_DMA, ("auacer_attach: lists %p\n",
314 1.1 augustss sc->sc_pcmo.dmalist));
315 1.1 augustss
316 1.1 augustss sc->host_if.arg = sc;
317 1.1 augustss sc->host_if.attach = auacer_attach_codec;
318 1.1 augustss sc->host_if.read = auacer_read_codec;
319 1.1 augustss sc->host_if.write = auacer_write_codec;
320 1.1 augustss sc->host_if.reset = auacer_reset_codec;
321 1.1 augustss
322 1.29 jmcneill if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) {
323 1.29 jmcneill mutex_destroy(&sc->sc_lock);
324 1.29 jmcneill mutex_destroy(&sc->sc_intr_lock);
325 1.1 augustss return;
326 1.29 jmcneill }
327 1.1 augustss
328 1.4 kent /* setup audio_format */
329 1.4 kent memcpy(sc->sc_formats, auacer_formats, sizeof(auacer_formats));
330 1.29 jmcneill mutex_enter(&sc->sc_lock);
331 1.4 kent if (!AC97_IS_4CH(sc->codec_if))
332 1.4 kent AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_4CH]);
333 1.4 kent if (!AC97_IS_6CH(sc->codec_if))
334 1.4 kent AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_6CH]);
335 1.4 kent if (AC97_IS_FIXED_RATE(sc->codec_if)) {
336 1.4 kent for (i = 0; i < AUACER_NFORMATS; i++) {
337 1.4 kent sc->sc_formats[i].frequency_type = 1;
338 1.4 kent sc->sc_formats[i].frequency[0] = 48000;
339 1.4 kent }
340 1.4 kent }
341 1.4 kent
342 1.29 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
343 1.29 jmcneill auacer_reset(sc);
344 1.29 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
345 1.29 jmcneill mutex_exit(&sc->sc_lock);
346 1.29 jmcneill
347 1.31 chs audio_attach_mi(&auacer_hw_if, sc, sc->sc_dev);
348 1.1 augustss
349 1.18 jmcneill if (!pmf_device_register(self, NULL, auacer_resume))
350 1.18 jmcneill aprint_error_dev(self, "couldn't establish power handler\n");
351 1.1 augustss }
352 1.1 augustss
353 1.31 chs CFATTACH_DECL_NEW(auacer, sizeof(struct auacer_softc),
354 1.10 thorpej auacer_match, auacer_attach, NULL, NULL);
355 1.10 thorpej
356 1.1 augustss static int
357 1.1 augustss auacer_ready_codec(struct auacer_softc *sc, int mask)
358 1.1 augustss {
359 1.7 kent int count;
360 1.1 augustss
361 1.1 augustss for (count = 0; count < 0x7f; count++) {
362 1.1 augustss int val = READ1(sc, ALI_CSPSR);
363 1.1 augustss if (val & mask)
364 1.1 augustss return 0;
365 1.1 augustss }
366 1.1 augustss
367 1.1 augustss aprint_normal("auacer_ready_codec: AC97 codec ready timeout.\n");
368 1.1 augustss return EBUSY;
369 1.1 augustss }
370 1.1 augustss
371 1.1 augustss static int
372 1.1 augustss auacer_sema_codec(struct auacer_softc *sc)
373 1.1 augustss {
374 1.9 christos int ttime;
375 1.1 augustss
376 1.9 christos ttime = 100;
377 1.9 christos while (ttime-- && (READ4(sc, ALI_CAS) & ALI_CAS_SEM_BUSY))
378 1.1 augustss delay(1);
379 1.9 christos if (!ttime)
380 1.1 augustss aprint_normal("auacer_sema_codec: timeout\n");
381 1.1 augustss return auacer_ready_codec(sc, ALI_CSPSR_CODEC_READY);
382 1.1 augustss }
383 1.1 augustss
384 1.10 thorpej static int
385 1.7 kent auacer_read_codec(void *v, uint8_t reg, uint16_t *val)
386 1.1 augustss {
387 1.7 kent struct auacer_softc *sc;
388 1.1 augustss
389 1.7 kent sc = v;
390 1.1 augustss if (auacer_sema_codec(sc))
391 1.1 augustss return EIO;
392 1.1 augustss
393 1.1 augustss reg |= ALI_CPR_ADDR_READ;
394 1.1 augustss #if 0
395 1.1 augustss if (ac97->num)
396 1.1 augustss reg |= ALI_CPR_ADDR_SECONDARY;
397 1.1 augustss #endif
398 1.1 augustss WRITE2(sc, ALI_CPR_ADDR, reg);
399 1.1 augustss if (auacer_ready_codec(sc, ALI_CSPSR_READ_OK))
400 1.1 augustss return EIO;
401 1.1 augustss *val = READ2(sc, ALI_SPR);
402 1.1 augustss
403 1.1 augustss DPRINTF(ALI_DEBUG_CODECIO, ("auacer_read_codec: reg=0x%x val=0x%x\n",
404 1.1 augustss reg, *val));
405 1.1 augustss
406 1.1 augustss return 0;
407 1.1 augustss }
408 1.1 augustss
409 1.1 augustss int
410 1.7 kent auacer_write_codec(void *v, uint8_t reg, uint16_t val)
411 1.1 augustss {
412 1.7 kent struct auacer_softc *sc;
413 1.1 augustss
414 1.1 augustss DPRINTF(ALI_DEBUG_CODECIO, ("auacer_write_codec: reg=0x%x val=0x%x\n",
415 1.1 augustss reg, val));
416 1.7 kent sc = v;
417 1.1 augustss if (auacer_sema_codec(sc))
418 1.1 augustss return EIO;
419 1.1 augustss WRITE2(sc, ALI_CPR, val);
420 1.1 augustss #if 0
421 1.1 augustss if (ac97->num)
422 1.1 augustss reg |= ALI_CPR_ADDR_SECONDARY;
423 1.1 augustss #endif
424 1.1 augustss WRITE2(sc, ALI_CPR_ADDR, reg);
425 1.1 augustss auacer_ready_codec(sc, ALI_CSPSR_WRITE_OK);
426 1.1 augustss return 0;
427 1.1 augustss }
428 1.1 augustss
429 1.10 thorpej static int
430 1.1 augustss auacer_attach_codec(void *v, struct ac97_codec_if *cif)
431 1.1 augustss {
432 1.7 kent struct auacer_softc *sc;
433 1.1 augustss
434 1.7 kent sc = v;
435 1.1 augustss sc->codec_if = cif;
436 1.1 augustss return 0;
437 1.1 augustss }
438 1.1 augustss
439 1.10 thorpej static int
440 1.1 augustss auacer_reset_codec(void *v)
441 1.1 augustss {
442 1.7 kent struct auacer_softc *sc;
443 1.7 kent uint32_t reg;
444 1.7 kent int i;
445 1.1 augustss
446 1.7 kent sc = v;
447 1.7 kent i = 0;
448 1.1 augustss reg = READ4(sc, ALI_SCR);
449 1.1 augustss if ((reg & 2) == 0) /* Cold required */
450 1.1 augustss reg |= 2;
451 1.1 augustss else
452 1.1 augustss reg |= 1; /* Warm */
453 1.1 augustss reg &= ~0x80000000; /* ACLink on */
454 1.1 augustss WRITE4(sc, ALI_SCR, reg);
455 1.1 augustss
456 1.1 augustss while (i < 10) {
457 1.1 augustss if ((READ4(sc, ALI_INTERRUPTSR) & ALI_INT_GPIO) == 0)
458 1.1 augustss break;
459 1.1 augustss delay(50000); /* XXX */
460 1.1 augustss i++;
461 1.1 augustss }
462 1.1 augustss if (i == 10) {
463 1.1 augustss return EIO;
464 1.1 augustss }
465 1.1 augustss
466 1.1 augustss for (i = 0; i < 10; i++) {
467 1.1 augustss reg = READ4(sc, ALI_RTSR);
468 1.1 augustss if (reg & 0x80) /* primary codec */
469 1.1 augustss break;
470 1.1 augustss WRITE4(sc, ALI_RTSR, reg | 0x80);
471 1.1 augustss delay(50000); /* XXX */
472 1.1 augustss }
473 1.1 augustss
474 1.1 augustss return 0;
475 1.1 augustss }
476 1.1 augustss
477 1.1 augustss static void
478 1.1 augustss auacer_reset(struct auacer_softc *sc)
479 1.1 augustss {
480 1.1 augustss WRITE4(sc, ALI_SCR, ALI_SCR_RESET);
481 1.1 augustss WRITE4(sc, ALI_FIFOCR1, 0x83838383);
482 1.1 augustss WRITE4(sc, ALI_FIFOCR2, 0x83838383);
483 1.1 augustss WRITE4(sc, ALI_FIFOCR3, 0x83838383);
484 1.1 augustss WRITE4(sc, ALI_INTERFACECR, ALI_IF_PO); /* XXX pcm out only */
485 1.1 augustss WRITE4(sc, ALI_INTERRUPTCR, 0x00000000);
486 1.1 augustss WRITE4(sc, ALI_INTERRUPTSR, 0x00000000);
487 1.1 augustss }
488 1.1 augustss
489 1.10 thorpej static int
490 1.37 isaki auacer_query_format(void *v, audio_format_query_t *afp)
491 1.1 augustss {
492 1.4 kent struct auacer_softc *sc;
493 1.4 kent
494 1.37 isaki DPRINTF(ALI_DEBUG_API, ("%s\n", __func__));
495 1.4 kent sc = v;
496 1.37 isaki return audio_query_format(sc->sc_formats, AUACER_NFORMATS, afp);
497 1.1 augustss }
498 1.1 augustss
499 1.10 thorpej static int
500 1.6 kent auacer_set_rate(struct auacer_softc *sc, int mode, u_int srate)
501 1.1 augustss {
502 1.1 augustss int ret;
503 1.6 kent u_int ratetmp;
504 1.1 augustss
505 1.8 augustss DPRINTF(ALI_DEBUG_API, ("auacer_set_rate: srate=%u\n", srate));
506 1.1 augustss
507 1.1 augustss ratetmp = srate;
508 1.1 augustss if (mode == AUMODE_RECORD)
509 1.1 augustss return sc->codec_if->vtbl->set_rate(sc->codec_if,
510 1.1 augustss AC97_REG_PCM_LR_ADC_RATE, &ratetmp);
511 1.1 augustss ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
512 1.1 augustss AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp);
513 1.1 augustss if (ret)
514 1.1 augustss return ret;
515 1.1 augustss ratetmp = srate;
516 1.1 augustss ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
517 1.1 augustss AC97_REG_PCM_SURR_DAC_RATE, &ratetmp);
518 1.1 augustss if (ret)
519 1.1 augustss return ret;
520 1.1 augustss ratetmp = srate;
521 1.1 augustss ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
522 1.1 augustss AC97_REG_PCM_LFE_DAC_RATE, &ratetmp);
523 1.1 augustss return ret;
524 1.1 augustss }
525 1.1 augustss
526 1.10 thorpej static int
527 1.37 isaki auacer_set_format(void *v, int setmode,
528 1.37 isaki const audio_params_t *play, const audio_params_t *rec,
529 1.37 isaki audio_filter_reg_t *pfil, audio_filter_reg_t *rfil)
530 1.1 augustss {
531 1.7 kent struct auacer_softc *sc;
532 1.37 isaki const audio_params_t *p;
533 1.1 augustss uint32_t control;
534 1.4 kent int mode, index;
535 1.1 augustss
536 1.37 isaki DPRINTF(ALI_DEBUG_API, ("%s\n", __func__));
537 1.7 kent sc = v;
538 1.1 augustss for (mode = AUMODE_RECORD; mode != -1;
539 1.1 augustss mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) {
540 1.1 augustss if ((setmode & mode) == 0)
541 1.1 augustss continue;
542 1.1 augustss
543 1.1 augustss p = mode == AUMODE_PLAY ? play : rec;
544 1.1 augustss
545 1.37 isaki index = audio_indexof_format(sc->sc_formats, AUACER_NFORMATS,
546 1.37 isaki mode, p);
547 1.6 kent /* p points HW encoding */
548 1.4 kent if (sc->sc_formats[index].frequency_type != 1
549 1.6 kent && auacer_set_rate(sc, mode, p->sample_rate))
550 1.4 kent return EINVAL;
551 1.1 augustss if (mode == AUMODE_PLAY) {
552 1.1 augustss control = READ4(sc, ALI_SCR);
553 1.1 augustss control &= ~ALI_SCR_PCM_246_MASK;
554 1.1 augustss if (p->channels == 4)
555 1.1 augustss control |= ALI_SCR_PCM_4;
556 1.1 augustss else if (p->channels == 6)
557 1.1 augustss control |= ALI_SCR_PCM_6;
558 1.1 augustss WRITE4(sc, ALI_SCR, control);
559 1.1 augustss }
560 1.1 augustss }
561 1.1 augustss
562 1.37 isaki return 0;
563 1.1 augustss }
564 1.1 augustss
565 1.10 thorpej static int
566 1.15 christos auacer_round_blocksize(void *v, int blk, int mode,
567 1.15 christos const audio_params_t *param)
568 1.1 augustss {
569 1.1 augustss
570 1.7 kent return blk & ~0x3f; /* keep good alignment */
571 1.1 augustss }
572 1.1 augustss
573 1.1 augustss static void
574 1.1 augustss auacer_halt(struct auacer_softc *sc, struct auacer_chan *chan)
575 1.1 augustss {
576 1.1 augustss uint32_t val;
577 1.7 kent uint8_t port;
578 1.1 augustss uint32_t slot;
579 1.1 augustss
580 1.7 kent port = chan->port;
581 1.1 augustss DPRINTF(ALI_DEBUG_API, ("auacer_halt: port=0x%x\n", port));
582 1.1 augustss chan->intr = 0;
583 1.1 augustss
584 1.1 augustss slot = ALI_PORT2SLOT(port);
585 1.1 augustss
586 1.1 augustss val = READ4(sc, ALI_DMACR);
587 1.1 augustss val |= 1 << (slot+16); /* pause */
588 1.1 augustss val &= ~(1 << slot); /* no start */
589 1.1 augustss WRITE4(sc, ALI_DMACR, val);
590 1.1 augustss WRITE1(sc, port + ALI_OFF_CR, 0);
591 1.1 augustss while (READ1(sc, port + ALI_OFF_CR))
592 1.1 augustss ;
593 1.1 augustss /* reset whole DMA things */
594 1.1 augustss WRITE1(sc, port + ALI_OFF_CR, ALI_CR_RR);
595 1.1 augustss /* clear interrupts */
596 1.1 augustss WRITE1(sc, port + ALI_OFF_SR, READ1(sc, port+ALI_OFF_SR) | ALI_SR_W1TC);
597 1.1 augustss WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(port));
598 1.1 augustss }
599 1.1 augustss
600 1.10 thorpej static int
601 1.1 augustss auacer_halt_output(void *v)
602 1.1 augustss {
603 1.7 kent struct auacer_softc *sc;
604 1.1 augustss
605 1.1 augustss DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_output\n"));
606 1.7 kent sc = v;
607 1.1 augustss auacer_halt(sc, &sc->sc_pcmo);
608 1.1 augustss
609 1.7 kent return 0;
610 1.1 augustss }
611 1.1 augustss
612 1.10 thorpej static int
613 1.15 christos auacer_halt_input(void *v)
614 1.1 augustss {
615 1.1 augustss DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_input\n"));
616 1.1 augustss
617 1.7 kent return 0;
618 1.1 augustss }
619 1.1 augustss
620 1.10 thorpej static int
621 1.1 augustss auacer_getdev(void *v, struct audio_device *adp)
622 1.1 augustss {
623 1.7 kent struct auacer_softc *sc;
624 1.1 augustss
625 1.1 augustss DPRINTF(ALI_DEBUG_API, ("auacer_getdev\n"));
626 1.7 kent sc = v;
627 1.1 augustss *adp = sc->sc_audev;
628 1.7 kent return 0;
629 1.1 augustss }
630 1.1 augustss
631 1.10 thorpej static int
632 1.1 augustss auacer_set_port(void *v, mixer_ctrl_t *cp)
633 1.1 augustss {
634 1.7 kent struct auacer_softc *sc;
635 1.1 augustss
636 1.1 augustss DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_set_port\n"));
637 1.7 kent sc = v;
638 1.7 kent return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp);
639 1.1 augustss }
640 1.1 augustss
641 1.10 thorpej static int
642 1.1 augustss auacer_get_port(void *v, mixer_ctrl_t *cp)
643 1.1 augustss {
644 1.7 kent struct auacer_softc *sc;
645 1.1 augustss
646 1.1 augustss DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_get_port\n"));
647 1.7 kent sc = v;
648 1.7 kent return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp);
649 1.1 augustss }
650 1.1 augustss
651 1.10 thorpej static int
652 1.1 augustss auacer_query_devinfo(void *v, mixer_devinfo_t *dp)
653 1.1 augustss {
654 1.7 kent struct auacer_softc *sc;
655 1.1 augustss
656 1.1 augustss DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_query_devinfo\n"));
657 1.7 kent sc = v;
658 1.7 kent return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp);
659 1.1 augustss }
660 1.1 augustss
661 1.10 thorpej static void *
662 1.29 jmcneill auacer_allocm(void *v, int direction, size_t size)
663 1.1 augustss {
664 1.7 kent struct auacer_softc *sc;
665 1.1 augustss struct auacer_dma *p;
666 1.1 augustss int error;
667 1.1 augustss
668 1.1 augustss if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX))
669 1.7 kent return NULL;
670 1.1 augustss
671 1.29 jmcneill p = kmem_zalloc(sizeof(*p), KM_SLEEP);
672 1.7 kent sc = v;
673 1.1 augustss error = auacer_allocmem(sc, size, 0, p);
674 1.1 augustss if (error) {
675 1.29 jmcneill kmem_free(p, sizeof(*p));
676 1.7 kent return NULL;
677 1.1 augustss }
678 1.1 augustss
679 1.1 augustss p->next = sc->sc_dmas;
680 1.1 augustss sc->sc_dmas = p;
681 1.1 augustss
682 1.7 kent return KERNADDR(p);
683 1.1 augustss }
684 1.1 augustss
685 1.10 thorpej static void
686 1.29 jmcneill auacer_freem(void *v, void *ptr, size_t size)
687 1.1 augustss {
688 1.7 kent struct auacer_softc *sc;
689 1.1 augustss struct auacer_dma *p, **pp;
690 1.1 augustss
691 1.7 kent sc = v;
692 1.1 augustss for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) {
693 1.1 augustss if (KERNADDR(p) == ptr) {
694 1.1 augustss auacer_freemem(sc, p);
695 1.1 augustss *pp = p->next;
696 1.29 jmcneill kmem_free(p, sizeof(*p));
697 1.1 augustss return;
698 1.1 augustss }
699 1.1 augustss }
700 1.1 augustss }
701 1.1 augustss
702 1.10 thorpej static size_t
703 1.15 christos auacer_round_buffersize(void *v, int direction, size_t size)
704 1.1 augustss {
705 1.1 augustss
706 1.1 augustss if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX))
707 1.1 augustss size = ALI_DMALIST_MAX * ALI_DMASEG_MAX;
708 1.1 augustss
709 1.1 augustss return size;
710 1.1 augustss }
711 1.1 augustss
712 1.10 thorpej static int
713 1.1 augustss auacer_get_props(void *v)
714 1.1 augustss {
715 1.1 augustss
716 1.38 isaki return AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE |
717 1.38 isaki AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX;
718 1.1 augustss }
719 1.1 augustss
720 1.1 augustss static void
721 1.29 jmcneill auacer_get_locks(void *v, kmutex_t **intr, kmutex_t **proc)
722 1.29 jmcneill {
723 1.29 jmcneill struct auacer_softc *sc;
724 1.29 jmcneill
725 1.29 jmcneill sc = v;
726 1.29 jmcneill *intr = &sc->sc_intr_lock;
727 1.29 jmcneill *proc = &sc->sc_lock;
728 1.29 jmcneill }
729 1.29 jmcneill
730 1.29 jmcneill static void
731 1.1 augustss auacer_add_entry(struct auacer_chan *chan)
732 1.1 augustss {
733 1.1 augustss struct auacer_dmalist *q;
734 1.1 augustss
735 1.1 augustss q = &chan->dmalist[chan->ptr];
736 1.1 augustss
737 1.1 augustss DPRINTF(ALI_DEBUG_INTR,
738 1.1 augustss ("auacer_add_entry: %p = %x @ 0x%x\n",
739 1.1 augustss q, chan->blksize / 2, chan->p));
740 1.1 augustss
741 1.1 augustss q->base = htole32(chan->p);
742 1.1 augustss q->len = htole32((chan->blksize / ALI_SAMPLE_SIZE) | ALI_DMAF_IOC);
743 1.1 augustss chan->p += chan->blksize;
744 1.1 augustss if (chan->p >= chan->end)
745 1.1 augustss chan->p = chan->start;
746 1.7 kent
747 1.1 augustss if (++chan->ptr >= ALI_DMALIST_MAX)
748 1.1 augustss chan->ptr = 0;
749 1.1 augustss }
750 1.1 augustss
751 1.1 augustss static void
752 1.1 augustss auacer_upd_chan(struct auacer_softc *sc, struct auacer_chan *chan)
753 1.1 augustss {
754 1.1 augustss uint32_t sts;
755 1.1 augustss uint32_t civ;
756 1.1 augustss
757 1.1 augustss sts = READ2(sc, chan->port + ALI_OFF_SR);
758 1.1 augustss /* intr ack */
759 1.1 augustss WRITE2(sc, chan->port + ALI_OFF_SR, sts & ALI_SR_W1TC);
760 1.1 augustss WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(chan->port));
761 1.1 augustss
762 1.1 augustss DPRINTF(ALI_DEBUG_INTR, ("auacer_upd_chan: sts=0x%x\n", sts));
763 1.1 augustss
764 1.1 augustss if (sts & ALI_SR_DMA_INT_FIFO) {
765 1.1 augustss printf("%s: fifo underrun # %u\n",
766 1.31 chs device_xname(sc->sc_dev), ++chan->fifoe);
767 1.1 augustss }
768 1.1 augustss
769 1.1 augustss civ = READ1(sc, chan->port + ALI_OFF_CIV);
770 1.7 kent
771 1.1 augustss DPRINTF(ALI_DEBUG_INTR,("auacer_intr: civ=%u ptr=%u\n",civ,chan->ptr));
772 1.7 kent
773 1.1 augustss /* XXX */
774 1.1 augustss while (chan->ptr != civ) {
775 1.1 augustss auacer_add_entry(chan);
776 1.1 augustss }
777 1.1 augustss
778 1.1 augustss WRITE1(sc, chan->port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK);
779 1.1 augustss
780 1.1 augustss while (chan->ack != civ) {
781 1.1 augustss if (chan->intr) {
782 1.1 augustss DPRINTF(ALI_DEBUG_INTR,("auacer_upd_chan: callback\n"));
783 1.1 augustss chan->intr(chan->arg);
784 1.1 augustss }
785 1.1 augustss chan->ack++;
786 1.1 augustss if (chan->ack >= ALI_DMALIST_MAX)
787 1.1 augustss chan->ack = 0;
788 1.1 augustss }
789 1.1 augustss }
790 1.1 augustss
791 1.10 thorpej static int
792 1.1 augustss auacer_intr(void *v)
793 1.1 augustss {
794 1.7 kent struct auacer_softc *sc;
795 1.1 augustss int ret, intrs;
796 1.1 augustss
797 1.7 kent sc = v;
798 1.29 jmcneill
799 1.29 jmcneill DPRINTF(ALI_DEBUG_INTR, ("auacer_intr: intrs=0x%x\n",
800 1.29 jmcneill READ4(sc, ALI_INTERRUPTSR)));
801 1.29 jmcneill
802 1.29 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
803 1.1 augustss intrs = READ4(sc, ALI_INTERRUPTSR);
804 1.1 augustss ret = 0;
805 1.1 augustss if (intrs & ALI_INT_PCMOUT) {
806 1.1 augustss auacer_upd_chan(sc, &sc->sc_pcmo);
807 1.1 augustss ret++;
808 1.1 augustss }
809 1.29 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
810 1.1 augustss
811 1.1 augustss return ret != 0;
812 1.1 augustss }
813 1.1 augustss
814 1.1 augustss static void
815 1.1 augustss auacer_setup_chan(struct auacer_softc *sc, struct auacer_chan *chan,
816 1.1 augustss uint32_t start, uint32_t size, uint32_t blksize,
817 1.1 augustss void (*intr)(void *), void *arg)
818 1.1 augustss {
819 1.1 augustss uint32_t port, slot;
820 1.1 augustss uint32_t offs, val;
821 1.1 augustss
822 1.1 augustss chan->start = start;
823 1.1 augustss chan->ptr = 0;
824 1.1 augustss chan->p = chan->start;
825 1.1 augustss chan->end = chan->start + size;
826 1.1 augustss chan->blksize = blksize;
827 1.1 augustss chan->ack = 0;
828 1.1 augustss chan->intr = intr;
829 1.1 augustss chan->arg = arg;
830 1.1 augustss
831 1.1 augustss auacer_add_entry(chan);
832 1.1 augustss auacer_add_entry(chan);
833 1.1 augustss
834 1.1 augustss port = chan->port;
835 1.1 augustss slot = ALI_PORT2SLOT(port);
836 1.1 augustss
837 1.1 augustss WRITE1(sc, port + ALI_OFF_CIV, 0);
838 1.1 augustss WRITE1(sc, port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK);
839 1.1 augustss offs = (char *)chan->dmalist - (char *)sc->sc_cdata;
840 1.1 augustss WRITE4(sc, port + ALI_OFF_BDBAR, sc->sc_cddma + offs);
841 1.1 augustss WRITE1(sc, port + ALI_OFF_CR,
842 1.1 augustss ALI_CR_IOCE | ALI_CR_FEIE | ALI_CR_LVBIE | ALI_CR_RPBM);
843 1.1 augustss val = READ4(sc, ALI_DMACR);
844 1.1 augustss val &= ~(1 << (slot+16)); /* no pause */
845 1.1 augustss val |= 1 << slot; /* start */
846 1.1 augustss WRITE4(sc, ALI_DMACR, val);
847 1.1 augustss }
848 1.1 augustss
849 1.10 thorpej static int
850 1.1 augustss auacer_trigger_output(void *v, void *start, void *end, int blksize,
851 1.15 christos void (*intr)(void *), void *arg, const audio_params_t *param)
852 1.1 augustss {
853 1.7 kent struct auacer_softc *sc;
854 1.1 augustss struct auacer_dma *p;
855 1.1 augustss uint32_t size;
856 1.1 augustss
857 1.1 augustss DPRINTF(ALI_DEBUG_DMA,
858 1.1 augustss ("auacer_trigger_output(%p, %p, %d, %p, %p, %p)\n",
859 1.1 augustss start, end, blksize, intr, arg, param));
860 1.7 kent sc = v;
861 1.1 augustss for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next)
862 1.7 kent continue;
863 1.1 augustss if (!p) {
864 1.1 augustss printf("auacer_trigger_output: bad addr %p\n", start);
865 1.1 augustss return (EINVAL);
866 1.1 augustss }
867 1.1 augustss
868 1.1 augustss size = (char *)end - (char *)start;
869 1.1 augustss auacer_setup_chan(sc, &sc->sc_pcmo, DMAADDR(p), size, blksize,
870 1.1 augustss intr, arg);
871 1.1 augustss
872 1.1 augustss return 0;
873 1.1 augustss }
874 1.1 augustss
875 1.10 thorpej static int
876 1.15 christos auacer_trigger_input(void *v, void *start, void *end,
877 1.15 christos int blksize, void (*intr)(void *), void *arg,
878 1.15 christos const audio_params_t *param)
879 1.1 augustss {
880 1.7 kent return EINVAL;
881 1.1 augustss }
882 1.1 augustss
883 1.10 thorpej static int
884 1.1 augustss auacer_allocmem(struct auacer_softc *sc, size_t size, size_t align,
885 1.1 augustss struct auacer_dma *p)
886 1.1 augustss {
887 1.1 augustss int error;
888 1.1 augustss
889 1.1 augustss p->size = size;
890 1.1 augustss error = bus_dmamem_alloc(sc->dmat, p->size, align, 0,
891 1.1 augustss p->segs, sizeof(p->segs)/sizeof(p->segs[0]),
892 1.29 jmcneill &p->nsegs, BUS_DMA_WAITOK);
893 1.1 augustss if (error)
894 1.7 kent return error;
895 1.1 augustss
896 1.1 augustss error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size,
897 1.29 jmcneill &p->addr, BUS_DMA_WAITOK|sc->sc_dmamap_flags);
898 1.1 augustss if (error)
899 1.1 augustss goto free;
900 1.1 augustss
901 1.1 augustss error = bus_dmamap_create(sc->dmat, p->size, 1, p->size,
902 1.29 jmcneill 0, BUS_DMA_WAITOK, &p->map);
903 1.1 augustss if (error)
904 1.1 augustss goto unmap;
905 1.1 augustss
906 1.1 augustss error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL,
907 1.29 jmcneill BUS_DMA_WAITOK);
908 1.1 augustss if (error)
909 1.1 augustss goto destroy;
910 1.1 augustss return (0);
911 1.1 augustss
912 1.1 augustss destroy:
913 1.1 augustss bus_dmamap_destroy(sc->dmat, p->map);
914 1.1 augustss unmap:
915 1.1 augustss bus_dmamem_unmap(sc->dmat, p->addr, p->size);
916 1.1 augustss free:
917 1.1 augustss bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
918 1.7 kent return error;
919 1.1 augustss }
920 1.1 augustss
921 1.10 thorpej static int
922 1.1 augustss auacer_freemem(struct auacer_softc *sc, struct auacer_dma *p)
923 1.1 augustss {
924 1.1 augustss
925 1.1 augustss bus_dmamap_unload(sc->dmat, p->map);
926 1.1 augustss bus_dmamap_destroy(sc->dmat, p->map);
927 1.1 augustss bus_dmamem_unmap(sc->dmat, p->addr, p->size);
928 1.1 augustss bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
929 1.7 kent return 0;
930 1.1 augustss }
931 1.1 augustss
932 1.10 thorpej static int
933 1.1 augustss auacer_alloc_cdata(struct auacer_softc *sc)
934 1.1 augustss {
935 1.1 augustss bus_dma_segment_t seg;
936 1.1 augustss int error, rseg;
937 1.1 augustss
938 1.1 augustss /*
939 1.1 augustss * Allocate the control data structure, and create and load the
940 1.1 augustss * DMA map for it.
941 1.1 augustss */
942 1.1 augustss if ((error = bus_dmamem_alloc(sc->dmat,
943 1.1 augustss sizeof(struct auacer_cdata),
944 1.1 augustss PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) {
945 1.31 chs aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n",
946 1.20 cegger error);
947 1.1 augustss goto fail_0;
948 1.1 augustss }
949 1.1 augustss
950 1.1 augustss if ((error = bus_dmamem_map(sc->dmat, &seg, rseg,
951 1.1 augustss sizeof(struct auacer_cdata),
952 1.16 christos (void **) &sc->sc_cdata,
953 1.1 augustss sc->sc_dmamap_flags)) != 0) {
954 1.31 chs aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n",
955 1.20 cegger error);
956 1.1 augustss goto fail_1;
957 1.1 augustss }
958 1.1 augustss
959 1.1 augustss if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auacer_cdata), 1,
960 1.1 augustss sizeof(struct auacer_cdata), 0, 0,
961 1.1 augustss &sc->sc_cddmamap)) != 0) {
962 1.31 chs aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, "
963 1.20 cegger "error = %d\n", error);
964 1.1 augustss goto fail_2;
965 1.1 augustss }
966 1.1 augustss
967 1.1 augustss if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap,
968 1.1 augustss sc->sc_cdata, sizeof(struct auacer_cdata),
969 1.1 augustss NULL, 0)) != 0) {
970 1.31 chs aprint_error_dev(sc->sc_dev, "unable to load control data DMA map, "
971 1.20 cegger "error = %d\n", error);
972 1.1 augustss goto fail_3;
973 1.1 augustss }
974 1.1 augustss
975 1.7 kent return 0;
976 1.1 augustss
977 1.1 augustss fail_3:
978 1.1 augustss bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap);
979 1.1 augustss fail_2:
980 1.16 christos bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata,
981 1.1 augustss sizeof(struct auacer_cdata));
982 1.1 augustss fail_1:
983 1.1 augustss bus_dmamem_free(sc->dmat, &seg, rseg);
984 1.1 augustss fail_0:
985 1.7 kent return error;
986 1.1 augustss }
987 1.1 augustss
988 1.18 jmcneill static bool
989 1.27 dyoung auacer_resume(device_t dv, const pmf_qual_t *qual)
990 1.1 augustss {
991 1.18 jmcneill struct auacer_softc *sc = device_private(dv);
992 1.18 jmcneill
993 1.29 jmcneill mutex_enter(&sc->sc_lock);
994 1.29 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
995 1.18 jmcneill auacer_reset_codec(sc);
996 1.29 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
997 1.18 jmcneill delay(1000);
998 1.18 jmcneill sc->codec_if->vtbl->restore_ports(sc->codec_if);
999 1.29 jmcneill mutex_exit(&sc->sc_lock);
1000 1.1 augustss
1001 1.18 jmcneill return true;
1002 1.1 augustss }
1003