auacer.c revision 1.9 1 1.9 christos /* $NetBSD: auacer.c,v 1.9 2005/05/30 04:35:22 christos Exp $ */
2 1.1 augustss
3 1.1 augustss /*-
4 1.1 augustss * Copyright (c) 2004 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.1 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.1 augustss * by Lennart Augustsson.
9 1.1 augustss *
10 1.1 augustss * Redistribution and use in source and binary forms, with or without
11 1.1 augustss * modification, are permitted provided that the following conditions
12 1.1 augustss * are met:
13 1.1 augustss * 1. Redistributions of source code must retain the above copyright
14 1.1 augustss * notice, this list of conditions and the following disclaimer.
15 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 augustss * notice, this list of conditions and the following disclaimer in the
17 1.1 augustss * documentation and/or other materials provided with the distribution.
18 1.1 augustss * 3. All advertising materials mentioning features or use of this software
19 1.1 augustss * must display the following acknowledgement:
20 1.1 augustss * This product includes software developed by the NetBSD
21 1.1 augustss * Foundation, Inc. and its contributors.
22 1.1 augustss * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 augustss * contributors may be used to endorse or promote products derived
24 1.1 augustss * from this software without specific prior written permission.
25 1.1 augustss *
26 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
37 1.1 augustss */
38 1.1 augustss
39 1.1 augustss /*
40 1.1 augustss * Acer Labs M5455 audio driver
41 1.1 augustss *
42 1.5 augustss * Acer provides data sheets after signing an NDA, so this is guess work.
43 1.1 augustss * The chip behaves somewhat like the Intel i8x0, so this driver
44 1.1 augustss * is loosely based on the auich driver. Additional information taken from
45 1.1 augustss * the ALSA intel8x0.c driver (which handles M5455 as well).
46 1.1 augustss *
47 1.1 augustss * As an historical note one can observe that the auich driver borrows
48 1.1 augustss * lot from the first NetBSD PCI audio driver, the eap driver. But this
49 1.1 augustss * is not attributed anywhere.
50 1.1 augustss */
51 1.1 augustss
52 1.1 augustss
53 1.1 augustss #include <sys/cdefs.h>
54 1.9 christos __KERNEL_RCSID(0, "$NetBSD: auacer.c,v 1.9 2005/05/30 04:35:22 christos Exp $");
55 1.1 augustss
56 1.1 augustss #include <sys/param.h>
57 1.1 augustss #include <sys/systm.h>
58 1.1 augustss #include <sys/kernel.h>
59 1.1 augustss #include <sys/malloc.h>
60 1.1 augustss #include <sys/device.h>
61 1.1 augustss #include <sys/fcntl.h>
62 1.1 augustss #include <sys/proc.h>
63 1.1 augustss
64 1.1 augustss #include <uvm/uvm_extern.h> /* for PAGE_SIZE */
65 1.1 augustss
66 1.1 augustss #include <dev/pci/pcidevs.h>
67 1.1 augustss #include <dev/pci/pcivar.h>
68 1.1 augustss #include <dev/pci/auacerreg.h>
69 1.1 augustss
70 1.1 augustss #include <sys/audioio.h>
71 1.1 augustss #include <dev/audio_if.h>
72 1.1 augustss #include <dev/mulaw.h>
73 1.1 augustss #include <dev/auconv.h>
74 1.1 augustss
75 1.1 augustss #include <machine/bus.h>
76 1.1 augustss
77 1.1 augustss #include <dev/ic/ac97reg.h>
78 1.1 augustss #include <dev/ic/ac97var.h>
79 1.1 augustss
80 1.1 augustss struct auacer_dma {
81 1.1 augustss bus_dmamap_t map;
82 1.1 augustss caddr_t addr;
83 1.1 augustss bus_dma_segment_t segs[1];
84 1.1 augustss int nsegs;
85 1.1 augustss size_t size;
86 1.1 augustss struct auacer_dma *next;
87 1.1 augustss };
88 1.1 augustss
89 1.1 augustss #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr)
90 1.1 augustss #define KERNADDR(p) ((void *)((p)->addr))
91 1.1 augustss
92 1.1 augustss struct auacer_cdata {
93 1.1 augustss struct auacer_dmalist ic_dmalist_pcmo[ALI_DMALIST_MAX];
94 1.1 augustss };
95 1.1 augustss
96 1.1 augustss struct auacer_chan {
97 1.1 augustss uint32_t ptr;
98 1.1 augustss uint32_t start, p, end;
99 1.1 augustss uint32_t blksize, fifoe;
100 1.1 augustss uint32_t ack;
101 1.1 augustss uint32_t port;
102 1.1 augustss struct auacer_dmalist *dmalist;
103 1.1 augustss void (*intr)(void *);
104 1.1 augustss void *arg;
105 1.1 augustss };
106 1.1 augustss
107 1.1 augustss struct auacer_softc {
108 1.1 augustss struct device sc_dev;
109 1.1 augustss void *sc_ih;
110 1.1 augustss
111 1.1 augustss audio_device_t sc_audev;
112 1.1 augustss
113 1.1 augustss bus_space_tag_t iot;
114 1.1 augustss bus_space_handle_t mix_ioh;
115 1.1 augustss bus_space_handle_t aud_ioh;
116 1.1 augustss bus_dma_tag_t dmat;
117 1.1 augustss
118 1.1 augustss struct ac97_codec_if *codec_if;
119 1.1 augustss struct ac97_host_if host_if;
120 1.1 augustss
121 1.1 augustss /* DMA scatter-gather lists. */
122 1.1 augustss bus_dmamap_t sc_cddmamap;
123 1.1 augustss #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
124 1.1 augustss
125 1.1 augustss struct auacer_cdata *sc_cdata;
126 1.1 augustss
127 1.1 augustss struct auacer_chan sc_pcmo;
128 1.1 augustss
129 1.1 augustss struct auacer_dma *sc_dmas;
130 1.1 augustss
131 1.1 augustss pci_chipset_tag_t sc_pc;
132 1.1 augustss pcitag_t sc_pt;
133 1.1 augustss
134 1.1 augustss int sc_dmamap_flags;
135 1.1 augustss
136 1.1 augustss /* Power Management */
137 1.1 augustss void *sc_powerhook;
138 1.1 augustss int sc_suspend;
139 1.4 kent
140 1.4 kent #define AUACER_NFORMATS 3
141 1.4 kent struct audio_format sc_formats[AUACER_NFORMATS];
142 1.4 kent struct audio_encoding_set *sc_encodings;
143 1.1 augustss };
144 1.1 augustss
145 1.1 augustss #define READ1(sc, a) bus_space_read_1(sc->iot, sc->aud_ioh, a)
146 1.1 augustss #define READ2(sc, a) bus_space_read_2(sc->iot, sc->aud_ioh, a)
147 1.1 augustss #define READ4(sc, a) bus_space_read_4(sc->iot, sc->aud_ioh, a)
148 1.1 augustss #define WRITE1(sc, a, v) bus_space_write_1(sc->iot, sc->aud_ioh, a, v)
149 1.1 augustss #define WRITE2(sc, a, v) bus_space_write_2(sc->iot, sc->aud_ioh, a, v)
150 1.1 augustss #define WRITE4(sc, a, v) bus_space_write_4(sc->iot, sc->aud_ioh, a, v)
151 1.1 augustss
152 1.1 augustss /* Debug */
153 1.1 augustss #ifdef AUACER_DEBUG
154 1.1 augustss #define DPRINTF(l,x) do { if (auacer_debug & (l)) printf x; } while(0)
155 1.1 augustss int auacer_debug = 0;
156 1.1 augustss #define ALI_DEBUG_CODECIO 0x0001
157 1.1 augustss #define ALI_DEBUG_DMA 0x0002
158 1.1 augustss #define ALI_DEBUG_INTR 0x0004
159 1.1 augustss #define ALI_DEBUG_API 0x0008
160 1.1 augustss #define ALI_DEBUG_MIXERAPI 0x0010
161 1.1 augustss #else
162 1.1 augustss #define DPRINTF(x,y) /* nothing */
163 1.1 augustss #endif
164 1.1 augustss
165 1.1 augustss int auacer_match(struct device *, struct cfdata *, void *);
166 1.1 augustss void auacer_attach(struct device *, struct device *, void *);
167 1.1 augustss int auacer_intr(void *);
168 1.1 augustss
169 1.1 augustss CFATTACH_DECL(auacer, sizeof(struct auacer_softc),
170 1.1 augustss auacer_match, auacer_attach, NULL, NULL);
171 1.1 augustss
172 1.1 augustss int auacer_query_encoding(void *, struct audio_encoding *);
173 1.6 kent int auacer_set_params(void *, int, int, audio_params_t *, audio_params_t *,
174 1.6 kent stream_filter_list_t *, stream_filter_list_t *);
175 1.6 kent int auacer_round_blocksize(void *, int, int, const audio_params_t *);
176 1.1 augustss int auacer_halt_output(void *);
177 1.1 augustss int auacer_halt_input(void *);
178 1.1 augustss int auacer_getdev(void *, struct audio_device *);
179 1.1 augustss int auacer_set_port(void *, mixer_ctrl_t *);
180 1.1 augustss int auacer_get_port(void *, mixer_ctrl_t *);
181 1.1 augustss int auacer_query_devinfo(void *, mixer_devinfo_t *);
182 1.1 augustss void *auacer_allocm(void *, int, size_t, struct malloc_type *, int);
183 1.1 augustss void auacer_freem(void *, void *, struct malloc_type *);
184 1.1 augustss size_t auacer_round_buffersize(void *, int, size_t);
185 1.1 augustss paddr_t auacer_mappage(void *, void *, off_t, int);
186 1.1 augustss int auacer_get_props(void *);
187 1.1 augustss int auacer_trigger_output(void *, void *, void *, int, void (*)(void *),
188 1.6 kent void *, const audio_params_t *);
189 1.1 augustss int auacer_trigger_input(void *, void *, void *, int, void (*)(void *),
190 1.6 kent void *, const audio_params_t *);
191 1.1 augustss
192 1.1 augustss int auacer_alloc_cdata(struct auacer_softc *);
193 1.1 augustss
194 1.1 augustss int auacer_allocmem(struct auacer_softc *, size_t, size_t,
195 1.1 augustss struct auacer_dma *);
196 1.1 augustss int auacer_freemem(struct auacer_softc *, struct auacer_dma *);
197 1.1 augustss
198 1.1 augustss void auacer_powerhook(int, void *);
199 1.6 kent int auacer_set_rate(struct auacer_softc *, int, u_int);
200 1.1 augustss void auacer_finish_attach(struct device *);
201 1.1 augustss
202 1.1 augustss static void auacer_reset(struct auacer_softc *sc);
203 1.1 augustss
204 1.1 augustss struct audio_hw_if auacer_hw_if = {
205 1.6 kent NULL, /* open */
206 1.6 kent NULL, /* close */
207 1.1 augustss NULL, /* drain */
208 1.1 augustss auacer_query_encoding,
209 1.1 augustss auacer_set_params,
210 1.1 augustss auacer_round_blocksize,
211 1.1 augustss NULL, /* commit_setting */
212 1.1 augustss NULL, /* init_output */
213 1.1 augustss NULL, /* init_input */
214 1.1 augustss NULL, /* start_output */
215 1.1 augustss NULL, /* start_input */
216 1.1 augustss auacer_halt_output,
217 1.1 augustss auacer_halt_input,
218 1.1 augustss NULL, /* speaker_ctl */
219 1.1 augustss auacer_getdev,
220 1.1 augustss NULL, /* getfd */
221 1.1 augustss auacer_set_port,
222 1.1 augustss auacer_get_port,
223 1.1 augustss auacer_query_devinfo,
224 1.1 augustss auacer_allocm,
225 1.1 augustss auacer_freem,
226 1.1 augustss auacer_round_buffersize,
227 1.1 augustss auacer_mappage,
228 1.1 augustss auacer_get_props,
229 1.1 augustss auacer_trigger_output,
230 1.1 augustss auacer_trigger_input,
231 1.1 augustss NULL, /* dev_ioctl */
232 1.1 augustss };
233 1.1 augustss
234 1.4 kent #define AUACER_FORMATS_4CH 1
235 1.4 kent #define AUACER_FORMATS_6CH 2
236 1.4 kent static const struct audio_format auacer_formats[AUACER_NFORMATS] = {
237 1.5 augustss {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
238 1.4 kent 2, AUFMT_STEREO, 0, {8000, 48000}},
239 1.4 kent {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
240 1.4 kent 4, AUFMT_SURROUND4, 0, {8000, 48000}},
241 1.4 kent {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
242 1.4 kent 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}},
243 1.4 kent };
244 1.4 kent
245 1.1 augustss int auacer_attach_codec(void *, struct ac97_codec_if *);
246 1.7 kent int auacer_read_codec(void *, uint8_t, uint16_t *);
247 1.7 kent int auacer_write_codec(void *, uint8_t, uint16_t);
248 1.1 augustss int auacer_reset_codec(void *);
249 1.1 augustss
250 1.1 augustss int
251 1.1 augustss auacer_match(struct device *parent, struct cfdata *match, void *aux)
252 1.1 augustss {
253 1.7 kent struct pci_attach_args *pa;
254 1.1 augustss
255 1.7 kent pa = (struct pci_attach_args *)aux;
256 1.1 augustss if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI &&
257 1.1 augustss PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M5455)
258 1.1 augustss return 1;
259 1.1 augustss return 0;
260 1.1 augustss }
261 1.1 augustss
262 1.1 augustss void
263 1.1 augustss auacer_attach(struct device *parent, struct device *self, void *aux)
264 1.1 augustss {
265 1.7 kent struct auacer_softc *sc;
266 1.7 kent struct pci_attach_args *pa;
267 1.1 augustss pci_intr_handle_t ih;
268 1.1 augustss bus_size_t aud_size;
269 1.1 augustss pcireg_t v;
270 1.1 augustss const char *intrstr;
271 1.4 kent int i;
272 1.1 augustss
273 1.7 kent sc = (struct auacer_softc *)self;
274 1.7 kent pa = aux;
275 1.1 augustss aprint_normal(": Acer Labs M5455 Audio controller\n");
276 1.1 augustss
277 1.1 augustss if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, &sc->iot,
278 1.1 augustss &sc->aud_ioh, NULL, &aud_size)) {
279 1.1 augustss aprint_error(": can't map i/o space\n");
280 1.1 augustss return;
281 1.1 augustss }
282 1.1 augustss
283 1.1 augustss sc->sc_pc = pa->pa_pc;
284 1.1 augustss sc->sc_pt = pa->pa_tag;
285 1.1 augustss sc->dmat = pa->pa_dmat;
286 1.1 augustss
287 1.1 augustss sc->sc_dmamap_flags = BUS_DMA_COHERENT; /* XXX remove */
288 1.1 augustss
289 1.1 augustss /* enable bus mastering */
290 1.1 augustss v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
291 1.1 augustss pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
292 1.1 augustss v | PCI_COMMAND_MASTER_ENABLE);
293 1.1 augustss
294 1.1 augustss /* Map and establish the interrupt. */
295 1.1 augustss if (pci_intr_map(pa, &ih)) {
296 1.1 augustss aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname);
297 1.1 augustss return;
298 1.1 augustss }
299 1.1 augustss intrstr = pci_intr_string(pa->pa_pc, ih);
300 1.1 augustss sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO,
301 1.1 augustss auacer_intr, sc);
302 1.1 augustss if (sc->sc_ih == NULL) {
303 1.1 augustss aprint_error("%s: can't establish interrupt",
304 1.1 augustss sc->sc_dev.dv_xname);
305 1.1 augustss if (intrstr != NULL)
306 1.1 augustss aprint_normal(" at %s", intrstr);
307 1.1 augustss aprint_normal("\n");
308 1.1 augustss return;
309 1.1 augustss }
310 1.1 augustss aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
311 1.1 augustss
312 1.1 augustss strlcpy(sc->sc_audev.name, "M5455 AC97", MAX_AUDIO_DEV_LEN);
313 1.1 augustss snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN,
314 1.1 augustss "0x%02x", PCI_REVISION(pa->pa_class));
315 1.1 augustss strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN);
316 1.1 augustss
317 1.1 augustss /* Set up DMA lists. */
318 1.1 augustss auacer_alloc_cdata(sc);
319 1.1 augustss sc->sc_pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo;
320 1.1 augustss sc->sc_pcmo.ptr = 0;
321 1.1 augustss sc->sc_pcmo.port = ALI_BASE_PO;
322 1.1 augustss
323 1.1 augustss DPRINTF(ALI_DEBUG_DMA, ("auacer_attach: lists %p\n",
324 1.1 augustss sc->sc_pcmo.dmalist));
325 1.1 augustss
326 1.1 augustss sc->host_if.arg = sc;
327 1.1 augustss sc->host_if.attach = auacer_attach_codec;
328 1.1 augustss sc->host_if.read = auacer_read_codec;
329 1.1 augustss sc->host_if.write = auacer_write_codec;
330 1.1 augustss sc->host_if.reset = auacer_reset_codec;
331 1.1 augustss
332 1.6 kent if (ac97_attach(&sc->host_if, self) != 0)
333 1.1 augustss return;
334 1.1 augustss
335 1.4 kent /* setup audio_format */
336 1.4 kent memcpy(sc->sc_formats, auacer_formats, sizeof(auacer_formats));
337 1.4 kent if (!AC97_IS_4CH(sc->codec_if))
338 1.4 kent AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_4CH]);
339 1.4 kent if (!AC97_IS_6CH(sc->codec_if))
340 1.4 kent AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_6CH]);
341 1.4 kent if (AC97_IS_FIXED_RATE(sc->codec_if)) {
342 1.4 kent for (i = 0; i < AUACER_NFORMATS; i++) {
343 1.4 kent sc->sc_formats[i].frequency_type = 1;
344 1.4 kent sc->sc_formats[i].frequency[0] = 48000;
345 1.4 kent }
346 1.4 kent }
347 1.4 kent
348 1.4 kent if (0 != auconv_create_encodings(sc->sc_formats, AUACER_NFORMATS,
349 1.4 kent &sc->sc_encodings)) {
350 1.4 kent return;
351 1.4 kent }
352 1.4 kent
353 1.1 augustss /* Watch for power change */
354 1.1 augustss sc->sc_suspend = PWR_RESUME;
355 1.1 augustss sc->sc_powerhook = powerhook_establish(auacer_powerhook, sc);
356 1.1 augustss
357 1.1 augustss audio_attach_mi(&auacer_hw_if, sc, &sc->sc_dev);
358 1.1 augustss
359 1.1 augustss auacer_reset(sc);
360 1.1 augustss }
361 1.1 augustss
362 1.1 augustss static int
363 1.1 augustss auacer_ready_codec(struct auacer_softc *sc, int mask)
364 1.1 augustss {
365 1.7 kent int count;
366 1.1 augustss
367 1.1 augustss for (count = 0; count < 0x7f; count++) {
368 1.1 augustss int val = READ1(sc, ALI_CSPSR);
369 1.1 augustss if (val & mask)
370 1.1 augustss return 0;
371 1.1 augustss }
372 1.1 augustss
373 1.1 augustss aprint_normal("auacer_ready_codec: AC97 codec ready timeout.\n");
374 1.1 augustss return EBUSY;
375 1.1 augustss }
376 1.1 augustss
377 1.1 augustss static int
378 1.1 augustss auacer_sema_codec(struct auacer_softc *sc)
379 1.1 augustss {
380 1.9 christos int ttime;
381 1.1 augustss
382 1.9 christos ttime = 100;
383 1.9 christos while (ttime-- && (READ4(sc, ALI_CAS) & ALI_CAS_SEM_BUSY))
384 1.1 augustss delay(1);
385 1.9 christos if (!ttime)
386 1.1 augustss aprint_normal("auacer_sema_codec: timeout\n");
387 1.1 augustss return auacer_ready_codec(sc, ALI_CSPSR_CODEC_READY);
388 1.1 augustss }
389 1.1 augustss
390 1.1 augustss int
391 1.7 kent auacer_read_codec(void *v, uint8_t reg, uint16_t *val)
392 1.1 augustss {
393 1.7 kent struct auacer_softc *sc;
394 1.1 augustss
395 1.7 kent sc = v;
396 1.1 augustss if (auacer_sema_codec(sc))
397 1.1 augustss return EIO;
398 1.1 augustss
399 1.1 augustss reg |= ALI_CPR_ADDR_READ;
400 1.1 augustss #if 0
401 1.1 augustss if (ac97->num)
402 1.1 augustss reg |= ALI_CPR_ADDR_SECONDARY;
403 1.1 augustss #endif
404 1.1 augustss WRITE2(sc, ALI_CPR_ADDR, reg);
405 1.1 augustss if (auacer_ready_codec(sc, ALI_CSPSR_READ_OK))
406 1.1 augustss return EIO;
407 1.1 augustss *val = READ2(sc, ALI_SPR);
408 1.1 augustss
409 1.1 augustss DPRINTF(ALI_DEBUG_CODECIO, ("auacer_read_codec: reg=0x%x val=0x%x\n",
410 1.1 augustss reg, *val));
411 1.1 augustss
412 1.1 augustss return 0;
413 1.1 augustss }
414 1.1 augustss
415 1.1 augustss int
416 1.7 kent auacer_write_codec(void *v, uint8_t reg, uint16_t val)
417 1.1 augustss {
418 1.7 kent struct auacer_softc *sc;
419 1.1 augustss
420 1.1 augustss DPRINTF(ALI_DEBUG_CODECIO, ("auacer_write_codec: reg=0x%x val=0x%x\n",
421 1.1 augustss reg, val));
422 1.7 kent sc = v;
423 1.1 augustss if (auacer_sema_codec(sc))
424 1.1 augustss return EIO;
425 1.1 augustss WRITE2(sc, ALI_CPR, val);
426 1.1 augustss #if 0
427 1.1 augustss if (ac97->num)
428 1.1 augustss reg |= ALI_CPR_ADDR_SECONDARY;
429 1.1 augustss #endif
430 1.1 augustss WRITE2(sc, ALI_CPR_ADDR, reg);
431 1.1 augustss auacer_ready_codec(sc, ALI_CSPSR_WRITE_OK);
432 1.1 augustss return 0;
433 1.1 augustss }
434 1.1 augustss
435 1.1 augustss int
436 1.1 augustss auacer_attach_codec(void *v, struct ac97_codec_if *cif)
437 1.1 augustss {
438 1.7 kent struct auacer_softc *sc;
439 1.1 augustss
440 1.7 kent sc = v;
441 1.1 augustss sc->codec_if = cif;
442 1.1 augustss return 0;
443 1.1 augustss }
444 1.1 augustss
445 1.1 augustss int
446 1.1 augustss auacer_reset_codec(void *v)
447 1.1 augustss {
448 1.7 kent struct auacer_softc *sc;
449 1.7 kent uint32_t reg;
450 1.7 kent int i;
451 1.1 augustss
452 1.7 kent sc = v;
453 1.7 kent i = 0;
454 1.1 augustss reg = READ4(sc, ALI_SCR);
455 1.1 augustss if ((reg & 2) == 0) /* Cold required */
456 1.1 augustss reg |= 2;
457 1.1 augustss else
458 1.1 augustss reg |= 1; /* Warm */
459 1.1 augustss reg &= ~0x80000000; /* ACLink on */
460 1.1 augustss WRITE4(sc, ALI_SCR, reg);
461 1.1 augustss
462 1.1 augustss while (i < 10) {
463 1.1 augustss if ((READ4(sc, ALI_INTERRUPTSR) & ALI_INT_GPIO) == 0)
464 1.1 augustss break;
465 1.1 augustss delay(50000); /* XXX */
466 1.1 augustss i++;
467 1.1 augustss }
468 1.1 augustss if (i == 10) {
469 1.1 augustss return EIO;
470 1.1 augustss }
471 1.1 augustss
472 1.1 augustss for (i = 0; i < 10; i++) {
473 1.1 augustss reg = READ4(sc, ALI_RTSR);
474 1.1 augustss if (reg & 0x80) /* primary codec */
475 1.1 augustss break;
476 1.1 augustss WRITE4(sc, ALI_RTSR, reg | 0x80);
477 1.1 augustss delay(50000); /* XXX */
478 1.1 augustss }
479 1.1 augustss
480 1.1 augustss return 0;
481 1.1 augustss }
482 1.1 augustss
483 1.1 augustss static void
484 1.1 augustss auacer_reset(struct auacer_softc *sc)
485 1.1 augustss {
486 1.1 augustss WRITE4(sc, ALI_SCR, ALI_SCR_RESET);
487 1.1 augustss WRITE4(sc, ALI_FIFOCR1, 0x83838383);
488 1.1 augustss WRITE4(sc, ALI_FIFOCR2, 0x83838383);
489 1.1 augustss WRITE4(sc, ALI_FIFOCR3, 0x83838383);
490 1.1 augustss WRITE4(sc, ALI_INTERFACECR, ALI_IF_PO); /* XXX pcm out only */
491 1.1 augustss WRITE4(sc, ALI_INTERRUPTCR, 0x00000000);
492 1.1 augustss WRITE4(sc, ALI_INTERRUPTSR, 0x00000000);
493 1.1 augustss }
494 1.1 augustss
495 1.1 augustss int
496 1.1 augustss auacer_query_encoding(void *v, struct audio_encoding *aep)
497 1.1 augustss {
498 1.4 kent struct auacer_softc *sc;
499 1.4 kent
500 1.1 augustss DPRINTF(ALI_DEBUG_API, ("auacer_query_encoding\n"));
501 1.4 kent sc = v;
502 1.4 kent return auconv_query_encoding(sc->sc_encodings, aep);
503 1.1 augustss }
504 1.1 augustss
505 1.1 augustss int
506 1.6 kent auacer_set_rate(struct auacer_softc *sc, int mode, u_int srate)
507 1.1 augustss {
508 1.1 augustss int ret;
509 1.6 kent u_int ratetmp;
510 1.1 augustss
511 1.8 augustss DPRINTF(ALI_DEBUG_API, ("auacer_set_rate: srate=%u\n", srate));
512 1.1 augustss
513 1.1 augustss ratetmp = srate;
514 1.1 augustss if (mode == AUMODE_RECORD)
515 1.1 augustss return sc->codec_if->vtbl->set_rate(sc->codec_if,
516 1.1 augustss AC97_REG_PCM_LR_ADC_RATE, &ratetmp);
517 1.1 augustss ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
518 1.1 augustss AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp);
519 1.1 augustss if (ret)
520 1.1 augustss return ret;
521 1.1 augustss ratetmp = srate;
522 1.1 augustss ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
523 1.1 augustss AC97_REG_PCM_SURR_DAC_RATE, &ratetmp);
524 1.1 augustss if (ret)
525 1.1 augustss return ret;
526 1.1 augustss ratetmp = srate;
527 1.1 augustss ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
528 1.1 augustss AC97_REG_PCM_LFE_DAC_RATE, &ratetmp);
529 1.1 augustss return ret;
530 1.1 augustss }
531 1.1 augustss
532 1.1 augustss int
533 1.6 kent auacer_set_params(void *v, int setmode, int usemode, audio_params_t *play,
534 1.6 kent audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil)
535 1.1 augustss {
536 1.7 kent struct auacer_softc *sc;
537 1.1 augustss struct audio_params *p;
538 1.6 kent stream_filter_list_t *fil;
539 1.1 augustss uint32_t control;
540 1.4 kent int mode, index;
541 1.1 augustss
542 1.1 augustss DPRINTF(ALI_DEBUG_API, ("auacer_set_params\n"));
543 1.7 kent sc = v;
544 1.1 augustss for (mode = AUMODE_RECORD; mode != -1;
545 1.1 augustss mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) {
546 1.1 augustss if ((setmode & mode) == 0)
547 1.1 augustss continue;
548 1.1 augustss
549 1.1 augustss p = mode == AUMODE_PLAY ? play : rec;
550 1.1 augustss if (p == NULL)
551 1.1 augustss continue;
552 1.1 augustss
553 1.1 augustss if ((p->sample_rate != 8000) &&
554 1.1 augustss (p->sample_rate != 11025) &&
555 1.1 augustss (p->sample_rate != 12000) &&
556 1.1 augustss (p->sample_rate != 16000) &&
557 1.1 augustss (p->sample_rate != 22050) &&
558 1.1 augustss (p->sample_rate != 24000) &&
559 1.1 augustss (p->sample_rate != 32000) &&
560 1.1 augustss (p->sample_rate != 44100) &&
561 1.1 augustss (p->sample_rate != 48000))
562 1.1 augustss return (EINVAL);
563 1.1 augustss
564 1.6 kent fil = mode == AUMODE_PLAY ? pfil : rfil;
565 1.4 kent index = auconv_set_converter(sc->sc_formats, AUACER_NFORMATS,
566 1.6 kent mode, p, TRUE, fil);
567 1.4 kent if (index < 0)
568 1.4 kent return EINVAL;
569 1.6 kent if (fil->req_size > 0)
570 1.6 kent p = &fil->filters[0].param;
571 1.6 kent /* p points HW encoding */
572 1.4 kent if (sc->sc_formats[index].frequency_type != 1
573 1.6 kent && auacer_set_rate(sc, mode, p->sample_rate))
574 1.4 kent return EINVAL;
575 1.1 augustss if (mode == AUMODE_PLAY) {
576 1.1 augustss control = READ4(sc, ALI_SCR);
577 1.1 augustss control &= ~ALI_SCR_PCM_246_MASK;
578 1.1 augustss if (p->channels == 4)
579 1.1 augustss control |= ALI_SCR_PCM_4;
580 1.1 augustss else if (p->channels == 6)
581 1.1 augustss control |= ALI_SCR_PCM_6;
582 1.1 augustss WRITE4(sc, ALI_SCR, control);
583 1.1 augustss }
584 1.1 augustss }
585 1.1 augustss
586 1.1 augustss return (0);
587 1.1 augustss }
588 1.1 augustss
589 1.1 augustss int
590 1.6 kent auacer_round_blocksize(void *v, int blk, int mode, const audio_params_t *param)
591 1.1 augustss {
592 1.1 augustss
593 1.7 kent return blk & ~0x3f; /* keep good alignment */
594 1.1 augustss }
595 1.1 augustss
596 1.1 augustss static void
597 1.1 augustss auacer_halt(struct auacer_softc *sc, struct auacer_chan *chan)
598 1.1 augustss {
599 1.1 augustss uint32_t val;
600 1.7 kent uint8_t port;
601 1.1 augustss uint32_t slot;
602 1.1 augustss
603 1.7 kent port = chan->port;
604 1.1 augustss DPRINTF(ALI_DEBUG_API, ("auacer_halt: port=0x%x\n", port));
605 1.1 augustss chan->intr = 0;
606 1.1 augustss
607 1.1 augustss slot = ALI_PORT2SLOT(port);
608 1.1 augustss
609 1.1 augustss val = READ4(sc, ALI_DMACR);
610 1.1 augustss val |= 1 << (slot+16); /* pause */
611 1.1 augustss val &= ~(1 << slot); /* no start */
612 1.1 augustss WRITE4(sc, ALI_DMACR, val);
613 1.1 augustss WRITE1(sc, port + ALI_OFF_CR, 0);
614 1.1 augustss while (READ1(sc, port + ALI_OFF_CR))
615 1.1 augustss ;
616 1.1 augustss /* reset whole DMA things */
617 1.1 augustss WRITE1(sc, port + ALI_OFF_CR, ALI_CR_RR);
618 1.1 augustss /* clear interrupts */
619 1.1 augustss WRITE1(sc, port + ALI_OFF_SR, READ1(sc, port+ALI_OFF_SR) | ALI_SR_W1TC);
620 1.1 augustss WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(port));
621 1.1 augustss }
622 1.1 augustss
623 1.1 augustss int
624 1.1 augustss auacer_halt_output(void *v)
625 1.1 augustss {
626 1.7 kent struct auacer_softc *sc;
627 1.1 augustss
628 1.1 augustss DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_output\n"));
629 1.7 kent sc = v;
630 1.1 augustss auacer_halt(sc, &sc->sc_pcmo);
631 1.1 augustss
632 1.7 kent return 0;
633 1.1 augustss }
634 1.1 augustss
635 1.1 augustss int
636 1.1 augustss auacer_halt_input(void *v)
637 1.1 augustss {
638 1.1 augustss /*struct auacer_softc *sc = v;*/
639 1.1 augustss
640 1.1 augustss DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_input\n"));
641 1.1 augustss
642 1.7 kent return 0;
643 1.1 augustss }
644 1.1 augustss
645 1.1 augustss int
646 1.1 augustss auacer_getdev(void *v, struct audio_device *adp)
647 1.1 augustss {
648 1.7 kent struct auacer_softc *sc;
649 1.1 augustss
650 1.1 augustss DPRINTF(ALI_DEBUG_API, ("auacer_getdev\n"));
651 1.7 kent sc = v;
652 1.1 augustss *adp = sc->sc_audev;
653 1.7 kent return 0;
654 1.1 augustss }
655 1.1 augustss
656 1.1 augustss int
657 1.1 augustss auacer_set_port(void *v, mixer_ctrl_t *cp)
658 1.1 augustss {
659 1.7 kent struct auacer_softc *sc;
660 1.1 augustss
661 1.1 augustss DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_set_port\n"));
662 1.7 kent sc = v;
663 1.7 kent return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp);
664 1.1 augustss }
665 1.1 augustss
666 1.1 augustss int
667 1.1 augustss auacer_get_port(void *v, mixer_ctrl_t *cp)
668 1.1 augustss {
669 1.7 kent struct auacer_softc *sc;
670 1.1 augustss
671 1.1 augustss DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_get_port\n"));
672 1.7 kent sc = v;
673 1.7 kent return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp);
674 1.1 augustss }
675 1.1 augustss
676 1.1 augustss int
677 1.1 augustss auacer_query_devinfo(void *v, mixer_devinfo_t *dp)
678 1.1 augustss {
679 1.7 kent struct auacer_softc *sc;
680 1.1 augustss
681 1.1 augustss DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_query_devinfo\n"));
682 1.7 kent sc = v;
683 1.7 kent return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp);
684 1.1 augustss }
685 1.1 augustss
686 1.1 augustss void *
687 1.1 augustss auacer_allocm(void *v, int direction, size_t size, struct malloc_type *pool,
688 1.1 augustss int flags)
689 1.1 augustss {
690 1.7 kent struct auacer_softc *sc;
691 1.1 augustss struct auacer_dma *p;
692 1.1 augustss int error;
693 1.1 augustss
694 1.1 augustss if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX))
695 1.7 kent return NULL;
696 1.1 augustss
697 1.1 augustss p = malloc(sizeof(*p), pool, flags | M_ZERO);
698 1.1 augustss if (p == NULL)
699 1.7 kent return NULL;
700 1.7 kent sc = v;
701 1.1 augustss error = auacer_allocmem(sc, size, 0, p);
702 1.1 augustss if (error) {
703 1.1 augustss free(p, pool);
704 1.7 kent return NULL;
705 1.1 augustss }
706 1.1 augustss
707 1.1 augustss p->next = sc->sc_dmas;
708 1.1 augustss sc->sc_dmas = p;
709 1.1 augustss
710 1.7 kent return KERNADDR(p);
711 1.1 augustss }
712 1.1 augustss
713 1.1 augustss void
714 1.1 augustss auacer_freem(void *v, void *ptr, struct malloc_type *pool)
715 1.1 augustss {
716 1.7 kent struct auacer_softc *sc;
717 1.1 augustss struct auacer_dma *p, **pp;
718 1.1 augustss
719 1.7 kent sc = v;
720 1.1 augustss for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) {
721 1.1 augustss if (KERNADDR(p) == ptr) {
722 1.1 augustss auacer_freemem(sc, p);
723 1.1 augustss *pp = p->next;
724 1.1 augustss free(p, pool);
725 1.1 augustss return;
726 1.1 augustss }
727 1.1 augustss }
728 1.1 augustss }
729 1.1 augustss
730 1.1 augustss size_t
731 1.1 augustss auacer_round_buffersize(void *v, int direction, size_t size)
732 1.1 augustss {
733 1.1 augustss
734 1.1 augustss if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX))
735 1.1 augustss size = ALI_DMALIST_MAX * ALI_DMASEG_MAX;
736 1.1 augustss
737 1.1 augustss return size;
738 1.1 augustss }
739 1.1 augustss
740 1.1 augustss paddr_t
741 1.1 augustss auacer_mappage(void *v, void *mem, off_t off, int prot)
742 1.1 augustss {
743 1.7 kent struct auacer_softc *sc;
744 1.1 augustss struct auacer_dma *p;
745 1.1 augustss
746 1.1 augustss if (off < 0)
747 1.7 kent return -1;
748 1.7 kent sc = v;
749 1.1 augustss for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next)
750 1.7 kent continue;
751 1.7 kent if (p == NULL)
752 1.7 kent return -1;
753 1.7 kent return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs,
754 1.7 kent off, prot, BUS_DMA_WAITOK);
755 1.1 augustss }
756 1.1 augustss
757 1.1 augustss int
758 1.1 augustss auacer_get_props(void *v)
759 1.1 augustss {
760 1.7 kent struct auacer_softc *sc;
761 1.1 augustss int props;
762 1.1 augustss
763 1.7 kent sc = v;
764 1.1 augustss props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX;
765 1.1 augustss /*
766 1.1 augustss * Even if the codec is fixed-rate, set_param() succeeds for any sample
767 1.1 augustss * rate because of aurateconv. Applications can't know what rate the
768 1.1 augustss * device can process in the case of mmap().
769 1.1 augustss */
770 1.3 kent if (!AC97_IS_FIXED_RATE(sc->codec_if))
771 1.1 augustss props |= AUDIO_PROP_MMAP;
772 1.1 augustss return props;
773 1.1 augustss }
774 1.1 augustss
775 1.1 augustss static void
776 1.1 augustss auacer_add_entry(struct auacer_chan *chan)
777 1.1 augustss {
778 1.1 augustss struct auacer_dmalist *q;
779 1.1 augustss
780 1.1 augustss q = &chan->dmalist[chan->ptr];
781 1.1 augustss
782 1.1 augustss DPRINTF(ALI_DEBUG_INTR,
783 1.1 augustss ("auacer_add_entry: %p = %x @ 0x%x\n",
784 1.1 augustss q, chan->blksize / 2, chan->p));
785 1.1 augustss
786 1.1 augustss q->base = htole32(chan->p);
787 1.1 augustss q->len = htole32((chan->blksize / ALI_SAMPLE_SIZE) | ALI_DMAF_IOC);
788 1.1 augustss chan->p += chan->blksize;
789 1.1 augustss if (chan->p >= chan->end)
790 1.1 augustss chan->p = chan->start;
791 1.7 kent
792 1.1 augustss if (++chan->ptr >= ALI_DMALIST_MAX)
793 1.1 augustss chan->ptr = 0;
794 1.1 augustss }
795 1.1 augustss
796 1.1 augustss static void
797 1.1 augustss auacer_upd_chan(struct auacer_softc *sc, struct auacer_chan *chan)
798 1.1 augustss {
799 1.1 augustss uint32_t sts;
800 1.1 augustss uint32_t civ;
801 1.1 augustss
802 1.1 augustss sts = READ2(sc, chan->port + ALI_OFF_SR);
803 1.1 augustss /* intr ack */
804 1.1 augustss WRITE2(sc, chan->port + ALI_OFF_SR, sts & ALI_SR_W1TC);
805 1.1 augustss WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(chan->port));
806 1.1 augustss
807 1.1 augustss DPRINTF(ALI_DEBUG_INTR, ("auacer_upd_chan: sts=0x%x\n", sts));
808 1.1 augustss
809 1.1 augustss if (sts & ALI_SR_DMA_INT_FIFO) {
810 1.1 augustss printf("%s: fifo underrun # %u\n",
811 1.1 augustss sc->sc_dev.dv_xname, ++chan->fifoe);
812 1.1 augustss }
813 1.1 augustss
814 1.1 augustss civ = READ1(sc, chan->port + ALI_OFF_CIV);
815 1.7 kent
816 1.1 augustss DPRINTF(ALI_DEBUG_INTR,("auacer_intr: civ=%u ptr=%u\n",civ,chan->ptr));
817 1.7 kent
818 1.1 augustss /* XXX */
819 1.1 augustss while (chan->ptr != civ) {
820 1.1 augustss auacer_add_entry(chan);
821 1.1 augustss }
822 1.1 augustss
823 1.1 augustss WRITE1(sc, chan->port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK);
824 1.1 augustss
825 1.1 augustss while (chan->ack != civ) {
826 1.1 augustss if (chan->intr) {
827 1.1 augustss DPRINTF(ALI_DEBUG_INTR,("auacer_upd_chan: callback\n"));
828 1.1 augustss chan->intr(chan->arg);
829 1.1 augustss }
830 1.1 augustss chan->ack++;
831 1.1 augustss if (chan->ack >= ALI_DMALIST_MAX)
832 1.1 augustss chan->ack = 0;
833 1.1 augustss }
834 1.1 augustss }
835 1.1 augustss
836 1.1 augustss int
837 1.1 augustss auacer_intr(void *v)
838 1.1 augustss {
839 1.7 kent struct auacer_softc *sc;
840 1.1 augustss int ret, intrs;
841 1.1 augustss
842 1.7 kent sc = v;
843 1.1 augustss intrs = READ4(sc, ALI_INTERRUPTSR);
844 1.1 augustss DPRINTF(ALI_DEBUG_INTR, ("auacer_intr: intrs=0x%x\n", intrs));
845 1.1 augustss
846 1.1 augustss ret = 0;
847 1.1 augustss if (intrs & ALI_INT_PCMOUT) {
848 1.1 augustss auacer_upd_chan(sc, &sc->sc_pcmo);
849 1.1 augustss ret++;
850 1.1 augustss }
851 1.1 augustss
852 1.1 augustss return ret != 0;
853 1.1 augustss }
854 1.1 augustss
855 1.1 augustss static void
856 1.1 augustss auacer_setup_chan(struct auacer_softc *sc, struct auacer_chan *chan,
857 1.1 augustss uint32_t start, uint32_t size, uint32_t blksize,
858 1.1 augustss void (*intr)(void *), void *arg)
859 1.1 augustss {
860 1.1 augustss uint32_t port, slot;
861 1.1 augustss uint32_t offs, val;
862 1.1 augustss
863 1.1 augustss chan->start = start;
864 1.1 augustss chan->ptr = 0;
865 1.1 augustss chan->p = chan->start;
866 1.1 augustss chan->end = chan->start + size;
867 1.1 augustss chan->blksize = blksize;
868 1.1 augustss chan->ack = 0;
869 1.1 augustss chan->intr = intr;
870 1.1 augustss chan->arg = arg;
871 1.1 augustss
872 1.1 augustss auacer_add_entry(chan);
873 1.1 augustss auacer_add_entry(chan);
874 1.1 augustss
875 1.1 augustss port = chan->port;
876 1.1 augustss slot = ALI_PORT2SLOT(port);
877 1.1 augustss
878 1.1 augustss WRITE1(sc, port + ALI_OFF_CIV, 0);
879 1.1 augustss WRITE1(sc, port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK);
880 1.1 augustss offs = (char *)chan->dmalist - (char *)sc->sc_cdata;
881 1.1 augustss WRITE4(sc, port + ALI_OFF_BDBAR, sc->sc_cddma + offs);
882 1.1 augustss WRITE1(sc, port + ALI_OFF_CR,
883 1.1 augustss ALI_CR_IOCE | ALI_CR_FEIE | ALI_CR_LVBIE | ALI_CR_RPBM);
884 1.1 augustss val = READ4(sc, ALI_DMACR);
885 1.1 augustss val &= ~(1 << (slot+16)); /* no pause */
886 1.1 augustss val |= 1 << slot; /* start */
887 1.1 augustss WRITE4(sc, ALI_DMACR, val);
888 1.1 augustss }
889 1.1 augustss
890 1.1 augustss int
891 1.1 augustss auacer_trigger_output(void *v, void *start, void *end, int blksize,
892 1.6 kent void (*intr)(void *), void *arg, const audio_params_t *param)
893 1.1 augustss {
894 1.7 kent struct auacer_softc *sc;
895 1.1 augustss struct auacer_dma *p;
896 1.1 augustss uint32_t size;
897 1.1 augustss
898 1.1 augustss DPRINTF(ALI_DEBUG_DMA,
899 1.1 augustss ("auacer_trigger_output(%p, %p, %d, %p, %p, %p)\n",
900 1.1 augustss start, end, blksize, intr, arg, param));
901 1.7 kent sc = v;
902 1.1 augustss for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next)
903 1.7 kent continue;
904 1.1 augustss if (!p) {
905 1.1 augustss printf("auacer_trigger_output: bad addr %p\n", start);
906 1.1 augustss return (EINVAL);
907 1.1 augustss }
908 1.1 augustss
909 1.1 augustss size = (char *)end - (char *)start;
910 1.1 augustss auacer_setup_chan(sc, &sc->sc_pcmo, DMAADDR(p), size, blksize,
911 1.1 augustss intr, arg);
912 1.1 augustss
913 1.1 augustss return 0;
914 1.1 augustss }
915 1.1 augustss
916 1.1 augustss int
917 1.1 augustss auacer_trigger_input(void *v, void *start, void *end, int blksize,
918 1.1 augustss void (*intr)(void *), void *arg,
919 1.6 kent const audio_params_t *param)
920 1.1 augustss {
921 1.7 kent return EINVAL;
922 1.1 augustss }
923 1.1 augustss
924 1.1 augustss int
925 1.1 augustss auacer_allocmem(struct auacer_softc *sc, size_t size, size_t align,
926 1.1 augustss struct auacer_dma *p)
927 1.1 augustss {
928 1.1 augustss int error;
929 1.1 augustss
930 1.1 augustss p->size = size;
931 1.1 augustss error = bus_dmamem_alloc(sc->dmat, p->size, align, 0,
932 1.1 augustss p->segs, sizeof(p->segs)/sizeof(p->segs[0]),
933 1.1 augustss &p->nsegs, BUS_DMA_NOWAIT);
934 1.1 augustss if (error)
935 1.7 kent return error;
936 1.1 augustss
937 1.1 augustss error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size,
938 1.1 augustss &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags);
939 1.1 augustss if (error)
940 1.1 augustss goto free;
941 1.1 augustss
942 1.1 augustss error = bus_dmamap_create(sc->dmat, p->size, 1, p->size,
943 1.1 augustss 0, BUS_DMA_NOWAIT, &p->map);
944 1.1 augustss if (error)
945 1.1 augustss goto unmap;
946 1.1 augustss
947 1.1 augustss error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL,
948 1.1 augustss BUS_DMA_NOWAIT);
949 1.1 augustss if (error)
950 1.1 augustss goto destroy;
951 1.1 augustss return (0);
952 1.1 augustss
953 1.1 augustss destroy:
954 1.1 augustss bus_dmamap_destroy(sc->dmat, p->map);
955 1.1 augustss unmap:
956 1.1 augustss bus_dmamem_unmap(sc->dmat, p->addr, p->size);
957 1.1 augustss free:
958 1.1 augustss bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
959 1.7 kent return error;
960 1.1 augustss }
961 1.1 augustss
962 1.1 augustss int
963 1.1 augustss auacer_freemem(struct auacer_softc *sc, struct auacer_dma *p)
964 1.1 augustss {
965 1.1 augustss
966 1.1 augustss bus_dmamap_unload(sc->dmat, p->map);
967 1.1 augustss bus_dmamap_destroy(sc->dmat, p->map);
968 1.1 augustss bus_dmamem_unmap(sc->dmat, p->addr, p->size);
969 1.1 augustss bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
970 1.7 kent return 0;
971 1.1 augustss }
972 1.1 augustss
973 1.1 augustss int
974 1.1 augustss auacer_alloc_cdata(struct auacer_softc *sc)
975 1.1 augustss {
976 1.1 augustss bus_dma_segment_t seg;
977 1.1 augustss int error, rseg;
978 1.1 augustss
979 1.1 augustss /*
980 1.1 augustss * Allocate the control data structure, and create and load the
981 1.1 augustss * DMA map for it.
982 1.1 augustss */
983 1.1 augustss if ((error = bus_dmamem_alloc(sc->dmat,
984 1.1 augustss sizeof(struct auacer_cdata),
985 1.1 augustss PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) {
986 1.1 augustss printf("%s: unable to allocate control data, error = %d\n",
987 1.1 augustss sc->sc_dev.dv_xname, error);
988 1.1 augustss goto fail_0;
989 1.1 augustss }
990 1.1 augustss
991 1.1 augustss if ((error = bus_dmamem_map(sc->dmat, &seg, rseg,
992 1.1 augustss sizeof(struct auacer_cdata),
993 1.1 augustss (caddr_t *) &sc->sc_cdata,
994 1.1 augustss sc->sc_dmamap_flags)) != 0) {
995 1.1 augustss printf("%s: unable to map control data, error = %d\n",
996 1.1 augustss sc->sc_dev.dv_xname, error);
997 1.1 augustss goto fail_1;
998 1.1 augustss }
999 1.1 augustss
1000 1.1 augustss if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auacer_cdata), 1,
1001 1.1 augustss sizeof(struct auacer_cdata), 0, 0,
1002 1.1 augustss &sc->sc_cddmamap)) != 0) {
1003 1.1 augustss printf("%s: unable to create control data DMA map, "
1004 1.1 augustss "error = %d\n", sc->sc_dev.dv_xname, error);
1005 1.1 augustss goto fail_2;
1006 1.1 augustss }
1007 1.1 augustss
1008 1.1 augustss if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap,
1009 1.1 augustss sc->sc_cdata, sizeof(struct auacer_cdata),
1010 1.1 augustss NULL, 0)) != 0) {
1011 1.5 augustss printf("%s: unable to load control data DMA map, "
1012 1.1 augustss "error = %d\n", sc->sc_dev.dv_xname, error);
1013 1.1 augustss goto fail_3;
1014 1.1 augustss }
1015 1.1 augustss
1016 1.7 kent return 0;
1017 1.1 augustss
1018 1.1 augustss fail_3:
1019 1.1 augustss bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap);
1020 1.1 augustss fail_2:
1021 1.1 augustss bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata,
1022 1.1 augustss sizeof(struct auacer_cdata));
1023 1.1 augustss fail_1:
1024 1.1 augustss bus_dmamem_free(sc->dmat, &seg, rseg);
1025 1.1 augustss fail_0:
1026 1.7 kent return error;
1027 1.1 augustss }
1028 1.1 augustss
1029 1.1 augustss void
1030 1.1 augustss auacer_powerhook(int why, void *addr)
1031 1.1 augustss {
1032 1.7 kent struct auacer_softc *sc;
1033 1.1 augustss
1034 1.7 kent sc = (struct auacer_softc *)addr;
1035 1.1 augustss switch (why) {
1036 1.1 augustss case PWR_SUSPEND:
1037 1.1 augustss case PWR_STANDBY:
1038 1.1 augustss /* Power down */
1039 1.1 augustss DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname));
1040 1.1 augustss sc->sc_suspend = why;
1041 1.1 augustss break;
1042 1.1 augustss
1043 1.1 augustss case PWR_RESUME:
1044 1.1 augustss /* Wake up */
1045 1.1 augustss DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname));
1046 1.1 augustss if (sc->sc_suspend == PWR_RESUME) {
1047 1.1 augustss printf("%s: resume without suspend.\n",
1048 1.1 augustss sc->sc_dev.dv_xname);
1049 1.1 augustss sc->sc_suspend = why;
1050 1.1 augustss return;
1051 1.1 augustss }
1052 1.1 augustss sc->sc_suspend = why;
1053 1.1 augustss auacer_reset_codec(sc);
1054 1.1 augustss delay(1000);
1055 1.1 augustss sc->codec_if->vtbl->restore_ports(sc->codec_if);
1056 1.1 augustss break;
1057 1.1 augustss
1058 1.1 augustss case PWR_SOFTSUSPEND:
1059 1.1 augustss case PWR_SOFTSTANDBY:
1060 1.1 augustss case PWR_SOFTRESUME:
1061 1.1 augustss break;
1062 1.1 augustss }
1063 1.1 augustss }
1064