auacer.c revision 1.10
1 /* $NetBSD: auacer.c,v 1.10 2005/06/28 00:28:41 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Acer Labs M5455 audio driver 41 * 42 * Acer provides data sheets after signing an NDA, so this is guess work. 43 * The chip behaves somewhat like the Intel i8x0, so this driver 44 * is loosely based on the auich driver. Additional information taken from 45 * the ALSA intel8x0.c driver (which handles M5455 as well). 46 * 47 * As an historical note one can observe that the auich driver borrows 48 * lot from the first NetBSD PCI audio driver, the eap driver. But this 49 * is not attributed anywhere. 50 */ 51 52 53 #include <sys/cdefs.h> 54 __KERNEL_RCSID(0, "$NetBSD: auacer.c,v 1.10 2005/06/28 00:28:41 thorpej Exp $"); 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/malloc.h> 60 #include <sys/device.h> 61 #include <sys/fcntl.h> 62 #include <sys/proc.h> 63 64 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 65 66 #include <dev/pci/pcidevs.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/auacerreg.h> 69 70 #include <sys/audioio.h> 71 #include <dev/audio_if.h> 72 #include <dev/mulaw.h> 73 #include <dev/auconv.h> 74 75 #include <machine/bus.h> 76 77 #include <dev/ic/ac97reg.h> 78 #include <dev/ic/ac97var.h> 79 80 struct auacer_dma { 81 bus_dmamap_t map; 82 caddr_t addr; 83 bus_dma_segment_t segs[1]; 84 int nsegs; 85 size_t size; 86 struct auacer_dma *next; 87 }; 88 89 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 90 #define KERNADDR(p) ((void *)((p)->addr)) 91 92 struct auacer_cdata { 93 struct auacer_dmalist ic_dmalist_pcmo[ALI_DMALIST_MAX]; 94 }; 95 96 struct auacer_chan { 97 uint32_t ptr; 98 uint32_t start, p, end; 99 uint32_t blksize, fifoe; 100 uint32_t ack; 101 uint32_t port; 102 struct auacer_dmalist *dmalist; 103 void (*intr)(void *); 104 void *arg; 105 }; 106 107 struct auacer_softc { 108 struct device sc_dev; 109 void *sc_ih; 110 111 audio_device_t sc_audev; 112 113 bus_space_tag_t iot; 114 bus_space_handle_t mix_ioh; 115 bus_space_handle_t aud_ioh; 116 bus_dma_tag_t dmat; 117 118 struct ac97_codec_if *codec_if; 119 struct ac97_host_if host_if; 120 121 /* DMA scatter-gather lists. */ 122 bus_dmamap_t sc_cddmamap; 123 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 124 125 struct auacer_cdata *sc_cdata; 126 127 struct auacer_chan sc_pcmo; 128 129 struct auacer_dma *sc_dmas; 130 131 pci_chipset_tag_t sc_pc; 132 pcitag_t sc_pt; 133 134 int sc_dmamap_flags; 135 136 /* Power Management */ 137 void *sc_powerhook; 138 int sc_suspend; 139 140 #define AUACER_NFORMATS 3 141 struct audio_format sc_formats[AUACER_NFORMATS]; 142 struct audio_encoding_set *sc_encodings; 143 }; 144 145 #define READ1(sc, a) bus_space_read_1(sc->iot, sc->aud_ioh, a) 146 #define READ2(sc, a) bus_space_read_2(sc->iot, sc->aud_ioh, a) 147 #define READ4(sc, a) bus_space_read_4(sc->iot, sc->aud_ioh, a) 148 #define WRITE1(sc, a, v) bus_space_write_1(sc->iot, sc->aud_ioh, a, v) 149 #define WRITE2(sc, a, v) bus_space_write_2(sc->iot, sc->aud_ioh, a, v) 150 #define WRITE4(sc, a, v) bus_space_write_4(sc->iot, sc->aud_ioh, a, v) 151 152 /* Debug */ 153 #ifdef AUACER_DEBUG 154 #define DPRINTF(l,x) do { if (auacer_debug & (l)) printf x; } while(0) 155 int auacer_debug = 0; 156 #define ALI_DEBUG_CODECIO 0x0001 157 #define ALI_DEBUG_DMA 0x0002 158 #define ALI_DEBUG_INTR 0x0004 159 #define ALI_DEBUG_API 0x0008 160 #define ALI_DEBUG_MIXERAPI 0x0010 161 #else 162 #define DPRINTF(x,y) /* nothing */ 163 #endif 164 165 static int auacer_intr(void *); 166 167 static int auacer_query_encoding(void *, struct audio_encoding *); 168 static int auacer_set_params(void *, int, int, audio_params_t *, 169 audio_params_t *, stream_filter_list_t *, 170 stream_filter_list_t *); 171 static int auacer_round_blocksize(void *, int, int, 172 const audio_params_t *); 173 static int auacer_halt_output(void *); 174 static int auacer_halt_input(void *); 175 static int auacer_getdev(void *, struct audio_device *); 176 static int auacer_set_port(void *, mixer_ctrl_t *); 177 static int auacer_get_port(void *, mixer_ctrl_t *); 178 static int auacer_query_devinfo(void *, mixer_devinfo_t *); 179 static void *auacer_allocm(void *, int, size_t, struct malloc_type *, int); 180 static void auacer_freem(void *, void *, struct malloc_type *); 181 static size_t auacer_round_buffersize(void *, int, size_t); 182 static paddr_t auacer_mappage(void *, void *, off_t, int); 183 static int auacer_get_props(void *); 184 static int auacer_trigger_output(void *, void *, void *, int, 185 void (*)(void *), void *, 186 const audio_params_t *); 187 static int auacer_trigger_input(void *, void *, void *, int, 188 void (*)(void *), void *, 189 const audio_params_t *); 190 191 static int auacer_alloc_cdata(struct auacer_softc *); 192 193 static int auacer_allocmem(struct auacer_softc *, size_t, size_t, 194 struct auacer_dma *); 195 static int auacer_freemem(struct auacer_softc *, struct auacer_dma *); 196 197 static void auacer_powerhook(int, void *); 198 static int auacer_set_rate(struct auacer_softc *, int, u_int); 199 200 static void auacer_reset(struct auacer_softc *sc); 201 202 static struct audio_hw_if auacer_hw_if = { 203 NULL, /* open */ 204 NULL, /* close */ 205 NULL, /* drain */ 206 auacer_query_encoding, 207 auacer_set_params, 208 auacer_round_blocksize, 209 NULL, /* commit_setting */ 210 NULL, /* init_output */ 211 NULL, /* init_input */ 212 NULL, /* start_output */ 213 NULL, /* start_input */ 214 auacer_halt_output, 215 auacer_halt_input, 216 NULL, /* speaker_ctl */ 217 auacer_getdev, 218 NULL, /* getfd */ 219 auacer_set_port, 220 auacer_get_port, 221 auacer_query_devinfo, 222 auacer_allocm, 223 auacer_freem, 224 auacer_round_buffersize, 225 auacer_mappage, 226 auacer_get_props, 227 auacer_trigger_output, 228 auacer_trigger_input, 229 NULL, /* dev_ioctl */ 230 }; 231 232 #define AUACER_FORMATS_4CH 1 233 #define AUACER_FORMATS_6CH 2 234 static const struct audio_format auacer_formats[AUACER_NFORMATS] = { 235 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 236 2, AUFMT_STEREO, 0, {8000, 48000}}, 237 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 238 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 239 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 240 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 241 }; 242 243 static int auacer_attach_codec(void *, struct ac97_codec_if *); 244 static int auacer_read_codec(void *, uint8_t, uint16_t *); 245 static int auacer_write_codec(void *, uint8_t, uint16_t); 246 static int auacer_reset_codec(void *); 247 248 static int 249 auacer_match(struct device *parent, struct cfdata *match, void *aux) 250 { 251 struct pci_attach_args *pa; 252 253 pa = (struct pci_attach_args *)aux; 254 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 255 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M5455) 256 return 1; 257 return 0; 258 } 259 260 static void 261 auacer_attach(struct device *parent, struct device *self, void *aux) 262 { 263 struct auacer_softc *sc; 264 struct pci_attach_args *pa; 265 pci_intr_handle_t ih; 266 bus_size_t aud_size; 267 pcireg_t v; 268 const char *intrstr; 269 int i; 270 271 sc = (struct auacer_softc *)self; 272 pa = aux; 273 aprint_normal(": Acer Labs M5455 Audio controller\n"); 274 275 if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, &sc->iot, 276 &sc->aud_ioh, NULL, &aud_size)) { 277 aprint_error(": can't map i/o space\n"); 278 return; 279 } 280 281 sc->sc_pc = pa->pa_pc; 282 sc->sc_pt = pa->pa_tag; 283 sc->dmat = pa->pa_dmat; 284 285 sc->sc_dmamap_flags = BUS_DMA_COHERENT; /* XXX remove */ 286 287 /* enable bus mastering */ 288 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 289 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 290 v | PCI_COMMAND_MASTER_ENABLE); 291 292 /* Map and establish the interrupt. */ 293 if (pci_intr_map(pa, &ih)) { 294 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 295 return; 296 } 297 intrstr = pci_intr_string(pa->pa_pc, ih); 298 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 299 auacer_intr, sc); 300 if (sc->sc_ih == NULL) { 301 aprint_error("%s: can't establish interrupt", 302 sc->sc_dev.dv_xname); 303 if (intrstr != NULL) 304 aprint_normal(" at %s", intrstr); 305 aprint_normal("\n"); 306 return; 307 } 308 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 309 310 strlcpy(sc->sc_audev.name, "M5455 AC97", MAX_AUDIO_DEV_LEN); 311 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 312 "0x%02x", PCI_REVISION(pa->pa_class)); 313 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 314 315 /* Set up DMA lists. */ 316 auacer_alloc_cdata(sc); 317 sc->sc_pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 318 sc->sc_pcmo.ptr = 0; 319 sc->sc_pcmo.port = ALI_BASE_PO; 320 321 DPRINTF(ALI_DEBUG_DMA, ("auacer_attach: lists %p\n", 322 sc->sc_pcmo.dmalist)); 323 324 sc->host_if.arg = sc; 325 sc->host_if.attach = auacer_attach_codec; 326 sc->host_if.read = auacer_read_codec; 327 sc->host_if.write = auacer_write_codec; 328 sc->host_if.reset = auacer_reset_codec; 329 330 if (ac97_attach(&sc->host_if, self) != 0) 331 return; 332 333 /* setup audio_format */ 334 memcpy(sc->sc_formats, auacer_formats, sizeof(auacer_formats)); 335 if (!AC97_IS_4CH(sc->codec_if)) 336 AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_4CH]); 337 if (!AC97_IS_6CH(sc->codec_if)) 338 AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_6CH]); 339 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 340 for (i = 0; i < AUACER_NFORMATS; i++) { 341 sc->sc_formats[i].frequency_type = 1; 342 sc->sc_formats[i].frequency[0] = 48000; 343 } 344 } 345 346 if (0 != auconv_create_encodings(sc->sc_formats, AUACER_NFORMATS, 347 &sc->sc_encodings)) { 348 return; 349 } 350 351 /* Watch for power change */ 352 sc->sc_suspend = PWR_RESUME; 353 sc->sc_powerhook = powerhook_establish(auacer_powerhook, sc); 354 355 audio_attach_mi(&auacer_hw_if, sc, &sc->sc_dev); 356 357 auacer_reset(sc); 358 } 359 360 CFATTACH_DECL(auacer, sizeof(struct auacer_softc), 361 auacer_match, auacer_attach, NULL, NULL); 362 363 static int 364 auacer_ready_codec(struct auacer_softc *sc, int mask) 365 { 366 int count; 367 368 for (count = 0; count < 0x7f; count++) { 369 int val = READ1(sc, ALI_CSPSR); 370 if (val & mask) 371 return 0; 372 } 373 374 aprint_normal("auacer_ready_codec: AC97 codec ready timeout.\n"); 375 return EBUSY; 376 } 377 378 static int 379 auacer_sema_codec(struct auacer_softc *sc) 380 { 381 int ttime; 382 383 ttime = 100; 384 while (ttime-- && (READ4(sc, ALI_CAS) & ALI_CAS_SEM_BUSY)) 385 delay(1); 386 if (!ttime) 387 aprint_normal("auacer_sema_codec: timeout\n"); 388 return auacer_ready_codec(sc, ALI_CSPSR_CODEC_READY); 389 } 390 391 static int 392 auacer_read_codec(void *v, uint8_t reg, uint16_t *val) 393 { 394 struct auacer_softc *sc; 395 396 sc = v; 397 if (auacer_sema_codec(sc)) 398 return EIO; 399 400 reg |= ALI_CPR_ADDR_READ; 401 #if 0 402 if (ac97->num) 403 reg |= ALI_CPR_ADDR_SECONDARY; 404 #endif 405 WRITE2(sc, ALI_CPR_ADDR, reg); 406 if (auacer_ready_codec(sc, ALI_CSPSR_READ_OK)) 407 return EIO; 408 *val = READ2(sc, ALI_SPR); 409 410 DPRINTF(ALI_DEBUG_CODECIO, ("auacer_read_codec: reg=0x%x val=0x%x\n", 411 reg, *val)); 412 413 return 0; 414 } 415 416 int 417 auacer_write_codec(void *v, uint8_t reg, uint16_t val) 418 { 419 struct auacer_softc *sc; 420 421 DPRINTF(ALI_DEBUG_CODECIO, ("auacer_write_codec: reg=0x%x val=0x%x\n", 422 reg, val)); 423 sc = v; 424 if (auacer_sema_codec(sc)) 425 return EIO; 426 WRITE2(sc, ALI_CPR, val); 427 #if 0 428 if (ac97->num) 429 reg |= ALI_CPR_ADDR_SECONDARY; 430 #endif 431 WRITE2(sc, ALI_CPR_ADDR, reg); 432 auacer_ready_codec(sc, ALI_CSPSR_WRITE_OK); 433 return 0; 434 } 435 436 static int 437 auacer_attach_codec(void *v, struct ac97_codec_if *cif) 438 { 439 struct auacer_softc *sc; 440 441 sc = v; 442 sc->codec_if = cif; 443 return 0; 444 } 445 446 static int 447 auacer_reset_codec(void *v) 448 { 449 struct auacer_softc *sc; 450 uint32_t reg; 451 int i; 452 453 sc = v; 454 i = 0; 455 reg = READ4(sc, ALI_SCR); 456 if ((reg & 2) == 0) /* Cold required */ 457 reg |= 2; 458 else 459 reg |= 1; /* Warm */ 460 reg &= ~0x80000000; /* ACLink on */ 461 WRITE4(sc, ALI_SCR, reg); 462 463 while (i < 10) { 464 if ((READ4(sc, ALI_INTERRUPTSR) & ALI_INT_GPIO) == 0) 465 break; 466 delay(50000); /* XXX */ 467 i++; 468 } 469 if (i == 10) { 470 return EIO; 471 } 472 473 for (i = 0; i < 10; i++) { 474 reg = READ4(sc, ALI_RTSR); 475 if (reg & 0x80) /* primary codec */ 476 break; 477 WRITE4(sc, ALI_RTSR, reg | 0x80); 478 delay(50000); /* XXX */ 479 } 480 481 return 0; 482 } 483 484 static void 485 auacer_reset(struct auacer_softc *sc) 486 { 487 WRITE4(sc, ALI_SCR, ALI_SCR_RESET); 488 WRITE4(sc, ALI_FIFOCR1, 0x83838383); 489 WRITE4(sc, ALI_FIFOCR2, 0x83838383); 490 WRITE4(sc, ALI_FIFOCR3, 0x83838383); 491 WRITE4(sc, ALI_INTERFACECR, ALI_IF_PO); /* XXX pcm out only */ 492 WRITE4(sc, ALI_INTERRUPTCR, 0x00000000); 493 WRITE4(sc, ALI_INTERRUPTSR, 0x00000000); 494 } 495 496 static int 497 auacer_query_encoding(void *v, struct audio_encoding *aep) 498 { 499 struct auacer_softc *sc; 500 501 DPRINTF(ALI_DEBUG_API, ("auacer_query_encoding\n")); 502 sc = v; 503 return auconv_query_encoding(sc->sc_encodings, aep); 504 } 505 506 static int 507 auacer_set_rate(struct auacer_softc *sc, int mode, u_int srate) 508 { 509 int ret; 510 u_int ratetmp; 511 512 DPRINTF(ALI_DEBUG_API, ("auacer_set_rate: srate=%u\n", srate)); 513 514 ratetmp = srate; 515 if (mode == AUMODE_RECORD) 516 return sc->codec_if->vtbl->set_rate(sc->codec_if, 517 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 518 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 519 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 520 if (ret) 521 return ret; 522 ratetmp = srate; 523 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 524 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 525 if (ret) 526 return ret; 527 ratetmp = srate; 528 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 529 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 530 return ret; 531 } 532 533 static int 534 auacer_set_params(void *v, int setmode, int usemode, audio_params_t *play, 535 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 536 { 537 struct auacer_softc *sc; 538 struct audio_params *p; 539 stream_filter_list_t *fil; 540 uint32_t control; 541 int mode, index; 542 543 DPRINTF(ALI_DEBUG_API, ("auacer_set_params\n")); 544 sc = v; 545 for (mode = AUMODE_RECORD; mode != -1; 546 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 547 if ((setmode & mode) == 0) 548 continue; 549 550 p = mode == AUMODE_PLAY ? play : rec; 551 if (p == NULL) 552 continue; 553 554 if ((p->sample_rate != 8000) && 555 (p->sample_rate != 11025) && 556 (p->sample_rate != 12000) && 557 (p->sample_rate != 16000) && 558 (p->sample_rate != 22050) && 559 (p->sample_rate != 24000) && 560 (p->sample_rate != 32000) && 561 (p->sample_rate != 44100) && 562 (p->sample_rate != 48000)) 563 return (EINVAL); 564 565 fil = mode == AUMODE_PLAY ? pfil : rfil; 566 index = auconv_set_converter(sc->sc_formats, AUACER_NFORMATS, 567 mode, p, TRUE, fil); 568 if (index < 0) 569 return EINVAL; 570 if (fil->req_size > 0) 571 p = &fil->filters[0].param; 572 /* p points HW encoding */ 573 if (sc->sc_formats[index].frequency_type != 1 574 && auacer_set_rate(sc, mode, p->sample_rate)) 575 return EINVAL; 576 if (mode == AUMODE_PLAY) { 577 control = READ4(sc, ALI_SCR); 578 control &= ~ALI_SCR_PCM_246_MASK; 579 if (p->channels == 4) 580 control |= ALI_SCR_PCM_4; 581 else if (p->channels == 6) 582 control |= ALI_SCR_PCM_6; 583 WRITE4(sc, ALI_SCR, control); 584 } 585 } 586 587 return (0); 588 } 589 590 static int 591 auacer_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 592 { 593 594 return blk & ~0x3f; /* keep good alignment */ 595 } 596 597 static void 598 auacer_halt(struct auacer_softc *sc, struct auacer_chan *chan) 599 { 600 uint32_t val; 601 uint8_t port; 602 uint32_t slot; 603 604 port = chan->port; 605 DPRINTF(ALI_DEBUG_API, ("auacer_halt: port=0x%x\n", port)); 606 chan->intr = 0; 607 608 slot = ALI_PORT2SLOT(port); 609 610 val = READ4(sc, ALI_DMACR); 611 val |= 1 << (slot+16); /* pause */ 612 val &= ~(1 << slot); /* no start */ 613 WRITE4(sc, ALI_DMACR, val); 614 WRITE1(sc, port + ALI_OFF_CR, 0); 615 while (READ1(sc, port + ALI_OFF_CR)) 616 ; 617 /* reset whole DMA things */ 618 WRITE1(sc, port + ALI_OFF_CR, ALI_CR_RR); 619 /* clear interrupts */ 620 WRITE1(sc, port + ALI_OFF_SR, READ1(sc, port+ALI_OFF_SR) | ALI_SR_W1TC); 621 WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(port)); 622 } 623 624 static int 625 auacer_halt_output(void *v) 626 { 627 struct auacer_softc *sc; 628 629 DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_output\n")); 630 sc = v; 631 auacer_halt(sc, &sc->sc_pcmo); 632 633 return 0; 634 } 635 636 static int 637 auacer_halt_input(void *v) 638 { 639 /*struct auacer_softc *sc = v;*/ 640 641 DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_input\n")); 642 643 return 0; 644 } 645 646 static int 647 auacer_getdev(void *v, struct audio_device *adp) 648 { 649 struct auacer_softc *sc; 650 651 DPRINTF(ALI_DEBUG_API, ("auacer_getdev\n")); 652 sc = v; 653 *adp = sc->sc_audev; 654 return 0; 655 } 656 657 static int 658 auacer_set_port(void *v, mixer_ctrl_t *cp) 659 { 660 struct auacer_softc *sc; 661 662 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_set_port\n")); 663 sc = v; 664 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 665 } 666 667 static int 668 auacer_get_port(void *v, mixer_ctrl_t *cp) 669 { 670 struct auacer_softc *sc; 671 672 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_get_port\n")); 673 sc = v; 674 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 675 } 676 677 static int 678 auacer_query_devinfo(void *v, mixer_devinfo_t *dp) 679 { 680 struct auacer_softc *sc; 681 682 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_query_devinfo\n")); 683 sc = v; 684 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 685 } 686 687 static void * 688 auacer_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 689 int flags) 690 { 691 struct auacer_softc *sc; 692 struct auacer_dma *p; 693 int error; 694 695 if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX)) 696 return NULL; 697 698 p = malloc(sizeof(*p), pool, flags | M_ZERO); 699 if (p == NULL) 700 return NULL; 701 sc = v; 702 error = auacer_allocmem(sc, size, 0, p); 703 if (error) { 704 free(p, pool); 705 return NULL; 706 } 707 708 p->next = sc->sc_dmas; 709 sc->sc_dmas = p; 710 711 return KERNADDR(p); 712 } 713 714 static void 715 auacer_freem(void *v, void *ptr, struct malloc_type *pool) 716 { 717 struct auacer_softc *sc; 718 struct auacer_dma *p, **pp; 719 720 sc = v; 721 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 722 if (KERNADDR(p) == ptr) { 723 auacer_freemem(sc, p); 724 *pp = p->next; 725 free(p, pool); 726 return; 727 } 728 } 729 } 730 731 static size_t 732 auacer_round_buffersize(void *v, int direction, size_t size) 733 { 734 735 if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX)) 736 size = ALI_DMALIST_MAX * ALI_DMASEG_MAX; 737 738 return size; 739 } 740 741 static paddr_t 742 auacer_mappage(void *v, void *mem, off_t off, int prot) 743 { 744 struct auacer_softc *sc; 745 struct auacer_dma *p; 746 747 if (off < 0) 748 return -1; 749 sc = v; 750 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 751 continue; 752 if (p == NULL) 753 return -1; 754 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 755 off, prot, BUS_DMA_WAITOK); 756 } 757 758 static int 759 auacer_get_props(void *v) 760 { 761 struct auacer_softc *sc; 762 int props; 763 764 sc = v; 765 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 766 /* 767 * Even if the codec is fixed-rate, set_param() succeeds for any sample 768 * rate because of aurateconv. Applications can't know what rate the 769 * device can process in the case of mmap(). 770 */ 771 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 772 props |= AUDIO_PROP_MMAP; 773 return props; 774 } 775 776 static void 777 auacer_add_entry(struct auacer_chan *chan) 778 { 779 struct auacer_dmalist *q; 780 781 q = &chan->dmalist[chan->ptr]; 782 783 DPRINTF(ALI_DEBUG_INTR, 784 ("auacer_add_entry: %p = %x @ 0x%x\n", 785 q, chan->blksize / 2, chan->p)); 786 787 q->base = htole32(chan->p); 788 q->len = htole32((chan->blksize / ALI_SAMPLE_SIZE) | ALI_DMAF_IOC); 789 chan->p += chan->blksize; 790 if (chan->p >= chan->end) 791 chan->p = chan->start; 792 793 if (++chan->ptr >= ALI_DMALIST_MAX) 794 chan->ptr = 0; 795 } 796 797 static void 798 auacer_upd_chan(struct auacer_softc *sc, struct auacer_chan *chan) 799 { 800 uint32_t sts; 801 uint32_t civ; 802 803 sts = READ2(sc, chan->port + ALI_OFF_SR); 804 /* intr ack */ 805 WRITE2(sc, chan->port + ALI_OFF_SR, sts & ALI_SR_W1TC); 806 WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(chan->port)); 807 808 DPRINTF(ALI_DEBUG_INTR, ("auacer_upd_chan: sts=0x%x\n", sts)); 809 810 if (sts & ALI_SR_DMA_INT_FIFO) { 811 printf("%s: fifo underrun # %u\n", 812 sc->sc_dev.dv_xname, ++chan->fifoe); 813 } 814 815 civ = READ1(sc, chan->port + ALI_OFF_CIV); 816 817 DPRINTF(ALI_DEBUG_INTR,("auacer_intr: civ=%u ptr=%u\n",civ,chan->ptr)); 818 819 /* XXX */ 820 while (chan->ptr != civ) { 821 auacer_add_entry(chan); 822 } 823 824 WRITE1(sc, chan->port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK); 825 826 while (chan->ack != civ) { 827 if (chan->intr) { 828 DPRINTF(ALI_DEBUG_INTR,("auacer_upd_chan: callback\n")); 829 chan->intr(chan->arg); 830 } 831 chan->ack++; 832 if (chan->ack >= ALI_DMALIST_MAX) 833 chan->ack = 0; 834 } 835 } 836 837 static int 838 auacer_intr(void *v) 839 { 840 struct auacer_softc *sc; 841 int ret, intrs; 842 843 sc = v; 844 intrs = READ4(sc, ALI_INTERRUPTSR); 845 DPRINTF(ALI_DEBUG_INTR, ("auacer_intr: intrs=0x%x\n", intrs)); 846 847 ret = 0; 848 if (intrs & ALI_INT_PCMOUT) { 849 auacer_upd_chan(sc, &sc->sc_pcmo); 850 ret++; 851 } 852 853 return ret != 0; 854 } 855 856 static void 857 auacer_setup_chan(struct auacer_softc *sc, struct auacer_chan *chan, 858 uint32_t start, uint32_t size, uint32_t blksize, 859 void (*intr)(void *), void *arg) 860 { 861 uint32_t port, slot; 862 uint32_t offs, val; 863 864 chan->start = start; 865 chan->ptr = 0; 866 chan->p = chan->start; 867 chan->end = chan->start + size; 868 chan->blksize = blksize; 869 chan->ack = 0; 870 chan->intr = intr; 871 chan->arg = arg; 872 873 auacer_add_entry(chan); 874 auacer_add_entry(chan); 875 876 port = chan->port; 877 slot = ALI_PORT2SLOT(port); 878 879 WRITE1(sc, port + ALI_OFF_CIV, 0); 880 WRITE1(sc, port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK); 881 offs = (char *)chan->dmalist - (char *)sc->sc_cdata; 882 WRITE4(sc, port + ALI_OFF_BDBAR, sc->sc_cddma + offs); 883 WRITE1(sc, port + ALI_OFF_CR, 884 ALI_CR_IOCE | ALI_CR_FEIE | ALI_CR_LVBIE | ALI_CR_RPBM); 885 val = READ4(sc, ALI_DMACR); 886 val &= ~(1 << (slot+16)); /* no pause */ 887 val |= 1 << slot; /* start */ 888 WRITE4(sc, ALI_DMACR, val); 889 } 890 891 static int 892 auacer_trigger_output(void *v, void *start, void *end, int blksize, 893 void (*intr)(void *), void *arg, const audio_params_t *param) 894 { 895 struct auacer_softc *sc; 896 struct auacer_dma *p; 897 uint32_t size; 898 899 DPRINTF(ALI_DEBUG_DMA, 900 ("auacer_trigger_output(%p, %p, %d, %p, %p, %p)\n", 901 start, end, blksize, intr, arg, param)); 902 sc = v; 903 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 904 continue; 905 if (!p) { 906 printf("auacer_trigger_output: bad addr %p\n", start); 907 return (EINVAL); 908 } 909 910 size = (char *)end - (char *)start; 911 auacer_setup_chan(sc, &sc->sc_pcmo, DMAADDR(p), size, blksize, 912 intr, arg); 913 914 return 0; 915 } 916 917 static int 918 auacer_trigger_input(void *v, void *start, void *end, int blksize, 919 void (*intr)(void *), void *arg, 920 const audio_params_t *param) 921 { 922 return EINVAL; 923 } 924 925 static int 926 auacer_allocmem(struct auacer_softc *sc, size_t size, size_t align, 927 struct auacer_dma *p) 928 { 929 int error; 930 931 p->size = size; 932 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 933 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 934 &p->nsegs, BUS_DMA_NOWAIT); 935 if (error) 936 return error; 937 938 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 939 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 940 if (error) 941 goto free; 942 943 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 944 0, BUS_DMA_NOWAIT, &p->map); 945 if (error) 946 goto unmap; 947 948 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 949 BUS_DMA_NOWAIT); 950 if (error) 951 goto destroy; 952 return (0); 953 954 destroy: 955 bus_dmamap_destroy(sc->dmat, p->map); 956 unmap: 957 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 958 free: 959 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 960 return error; 961 } 962 963 static int 964 auacer_freemem(struct auacer_softc *sc, struct auacer_dma *p) 965 { 966 967 bus_dmamap_unload(sc->dmat, p->map); 968 bus_dmamap_destroy(sc->dmat, p->map); 969 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 970 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 971 return 0; 972 } 973 974 static int 975 auacer_alloc_cdata(struct auacer_softc *sc) 976 { 977 bus_dma_segment_t seg; 978 int error, rseg; 979 980 /* 981 * Allocate the control data structure, and create and load the 982 * DMA map for it. 983 */ 984 if ((error = bus_dmamem_alloc(sc->dmat, 985 sizeof(struct auacer_cdata), 986 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 987 printf("%s: unable to allocate control data, error = %d\n", 988 sc->sc_dev.dv_xname, error); 989 goto fail_0; 990 } 991 992 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 993 sizeof(struct auacer_cdata), 994 (caddr_t *) &sc->sc_cdata, 995 sc->sc_dmamap_flags)) != 0) { 996 printf("%s: unable to map control data, error = %d\n", 997 sc->sc_dev.dv_xname, error); 998 goto fail_1; 999 } 1000 1001 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auacer_cdata), 1, 1002 sizeof(struct auacer_cdata), 0, 0, 1003 &sc->sc_cddmamap)) != 0) { 1004 printf("%s: unable to create control data DMA map, " 1005 "error = %d\n", sc->sc_dev.dv_xname, error); 1006 goto fail_2; 1007 } 1008 1009 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1010 sc->sc_cdata, sizeof(struct auacer_cdata), 1011 NULL, 0)) != 0) { 1012 printf("%s: unable to load control data DMA map, " 1013 "error = %d\n", sc->sc_dev.dv_xname, error); 1014 goto fail_3; 1015 } 1016 1017 return 0; 1018 1019 fail_3: 1020 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1021 fail_2: 1022 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1023 sizeof(struct auacer_cdata)); 1024 fail_1: 1025 bus_dmamem_free(sc->dmat, &seg, rseg); 1026 fail_0: 1027 return error; 1028 } 1029 1030 static void 1031 auacer_powerhook(int why, void *addr) 1032 { 1033 struct auacer_softc *sc; 1034 1035 sc = (struct auacer_softc *)addr; 1036 switch (why) { 1037 case PWR_SUSPEND: 1038 case PWR_STANDBY: 1039 /* Power down */ 1040 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1041 sc->sc_suspend = why; 1042 break; 1043 1044 case PWR_RESUME: 1045 /* Wake up */ 1046 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1047 if (sc->sc_suspend == PWR_RESUME) { 1048 printf("%s: resume without suspend.\n", 1049 sc->sc_dev.dv_xname); 1050 sc->sc_suspend = why; 1051 return; 1052 } 1053 sc->sc_suspend = why; 1054 auacer_reset_codec(sc); 1055 delay(1000); 1056 sc->codec_if->vtbl->restore_ports(sc->codec_if); 1057 break; 1058 1059 case PWR_SOFTSUSPEND: 1060 case PWR_SOFTSTANDBY: 1061 case PWR_SOFTRESUME: 1062 break; 1063 } 1064 } 1065
Indexes created Fri Oct 03 17:10:05 GMT 2025