auacer.c revision 1.12
1 /* $NetBSD: auacer.c,v 1.12 2006/08/27 23:53:10 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Acer Labs M5455 audio driver 41 * 42 * Acer provides data sheets after signing an NDA, so this is guess work. 43 * The chip behaves somewhat like the Intel i8x0, so this driver 44 * is loosely based on the auich driver. Additional information taken from 45 * the ALSA intel8x0.c driver (which handles M5455 as well). 46 * 47 * As an historical note one can observe that the auich driver borrows 48 * lot from the first NetBSD PCI audio driver, the eap driver. But this 49 * is not attributed anywhere. 50 */ 51 52 53 #include <sys/cdefs.h> 54 __KERNEL_RCSID(0, "$NetBSD: auacer.c,v 1.12 2006/08/27 23:53:10 christos Exp $"); 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/malloc.h> 60 #include <sys/device.h> 61 #include <sys/fcntl.h> 62 #include <sys/proc.h> 63 64 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 65 66 #include <dev/pci/pcidevs.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/auacerreg.h> 69 70 #include <sys/audioio.h> 71 #include <dev/audio_if.h> 72 #include <dev/mulaw.h> 73 #include <dev/auconv.h> 74 75 #include <machine/bus.h> 76 77 #include <dev/ic/ac97reg.h> 78 #include <dev/ic/ac97var.h> 79 80 struct auacer_dma { 81 bus_dmamap_t map; 82 caddr_t addr; 83 bus_dma_segment_t segs[1]; 84 int nsegs; 85 size_t size; 86 struct auacer_dma *next; 87 }; 88 89 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 90 #define KERNADDR(p) ((void *)((p)->addr)) 91 92 struct auacer_cdata { 93 struct auacer_dmalist ic_dmalist_pcmo[ALI_DMALIST_MAX]; 94 }; 95 96 struct auacer_chan { 97 uint32_t ptr; 98 uint32_t start, p, end; 99 uint32_t blksize, fifoe; 100 uint32_t ack; 101 uint32_t port; 102 struct auacer_dmalist *dmalist; 103 void (*intr)(void *); 104 void *arg; 105 }; 106 107 struct auacer_softc { 108 struct device sc_dev; 109 void *sc_ih; 110 111 audio_device_t sc_audev; 112 113 bus_space_tag_t iot; 114 bus_space_handle_t mix_ioh; 115 bus_space_handle_t aud_ioh; 116 bus_dma_tag_t dmat; 117 118 struct ac97_codec_if *codec_if; 119 struct ac97_host_if host_if; 120 121 /* DMA scatter-gather lists. */ 122 bus_dmamap_t sc_cddmamap; 123 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 124 125 struct auacer_cdata *sc_cdata; 126 127 struct auacer_chan sc_pcmo; 128 129 struct auacer_dma *sc_dmas; 130 131 pci_chipset_tag_t sc_pc; 132 pcitag_t sc_pt; 133 134 int sc_dmamap_flags; 135 136 /* Power Management */ 137 void *sc_powerhook; 138 int sc_suspend; 139 140 #define AUACER_NFORMATS 3 141 struct audio_format sc_formats[AUACER_NFORMATS]; 142 struct audio_encoding_set *sc_encodings; 143 }; 144 145 #define READ1(sc, a) bus_space_read_1(sc->iot, sc->aud_ioh, a) 146 #define READ2(sc, a) bus_space_read_2(sc->iot, sc->aud_ioh, a) 147 #define READ4(sc, a) bus_space_read_4(sc->iot, sc->aud_ioh, a) 148 #define WRITE1(sc, a, v) bus_space_write_1(sc->iot, sc->aud_ioh, a, v) 149 #define WRITE2(sc, a, v) bus_space_write_2(sc->iot, sc->aud_ioh, a, v) 150 #define WRITE4(sc, a, v) bus_space_write_4(sc->iot, sc->aud_ioh, a, v) 151 152 /* Debug */ 153 #ifdef AUACER_DEBUG 154 #define DPRINTF(l,x) do { if (auacer_debug & (l)) printf x; } while(0) 155 int auacer_debug = 0; 156 #define ALI_DEBUG_CODECIO 0x0001 157 #define ALI_DEBUG_DMA 0x0002 158 #define ALI_DEBUG_INTR 0x0004 159 #define ALI_DEBUG_API 0x0008 160 #define ALI_DEBUG_MIXERAPI 0x0010 161 #else 162 #define DPRINTF(x,y) /* nothing */ 163 #endif 164 165 static int auacer_intr(void *); 166 167 static int auacer_query_encoding(void *, struct audio_encoding *); 168 static int auacer_set_params(void *, int, int, audio_params_t *, 169 audio_params_t *, stream_filter_list_t *, 170 stream_filter_list_t *); 171 static int auacer_round_blocksize(void *, int, int, 172 const audio_params_t *); 173 static int auacer_halt_output(void *); 174 static int auacer_halt_input(void *); 175 static int auacer_getdev(void *, struct audio_device *); 176 static int auacer_set_port(void *, mixer_ctrl_t *); 177 static int auacer_get_port(void *, mixer_ctrl_t *); 178 static int auacer_query_devinfo(void *, mixer_devinfo_t *); 179 static void *auacer_allocm(void *, int, size_t, struct malloc_type *, int); 180 static void auacer_freem(void *, void *, struct malloc_type *); 181 static size_t auacer_round_buffersize(void *, int, size_t); 182 static paddr_t auacer_mappage(void *, void *, off_t, int); 183 static int auacer_get_props(void *); 184 static int auacer_trigger_output(void *, void *, void *, int, 185 void (*)(void *), void *, 186 const audio_params_t *); 187 static int auacer_trigger_input(void *, void *, void *, int, 188 void (*)(void *), void *, 189 const audio_params_t *); 190 191 static int auacer_alloc_cdata(struct auacer_softc *); 192 193 static int auacer_allocmem(struct auacer_softc *, size_t, size_t, 194 struct auacer_dma *); 195 static int auacer_freemem(struct auacer_softc *, struct auacer_dma *); 196 197 static void auacer_powerhook(int, void *); 198 static int auacer_set_rate(struct auacer_softc *, int, u_int); 199 200 static void auacer_reset(struct auacer_softc *sc); 201 202 static struct audio_hw_if auacer_hw_if = { 203 NULL, /* open */ 204 NULL, /* close */ 205 NULL, /* drain */ 206 auacer_query_encoding, 207 auacer_set_params, 208 auacer_round_blocksize, 209 NULL, /* commit_setting */ 210 NULL, /* init_output */ 211 NULL, /* init_input */ 212 NULL, /* start_output */ 213 NULL, /* start_input */ 214 auacer_halt_output, 215 auacer_halt_input, 216 NULL, /* speaker_ctl */ 217 auacer_getdev, 218 NULL, /* getfd */ 219 auacer_set_port, 220 auacer_get_port, 221 auacer_query_devinfo, 222 auacer_allocm, 223 auacer_freem, 224 auacer_round_buffersize, 225 auacer_mappage, 226 auacer_get_props, 227 auacer_trigger_output, 228 auacer_trigger_input, 229 NULL, /* dev_ioctl */ 230 NULL, /* powerstate */ 231 }; 232 233 #define AUACER_FORMATS_4CH 1 234 #define AUACER_FORMATS_6CH 2 235 static const struct audio_format auacer_formats[AUACER_NFORMATS] = { 236 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 237 2, AUFMT_STEREO, 0, {8000, 48000}}, 238 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 239 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 240 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 241 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 242 }; 243 244 static int auacer_attach_codec(void *, struct ac97_codec_if *); 245 static int auacer_read_codec(void *, uint8_t, uint16_t *); 246 static int auacer_write_codec(void *, uint8_t, uint16_t); 247 static int auacer_reset_codec(void *); 248 249 static int 250 auacer_match(struct device *parent, struct cfdata *match, void *aux) 251 { 252 struct pci_attach_args *pa; 253 254 pa = (struct pci_attach_args *)aux; 255 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 256 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M5455) 257 return 1; 258 return 0; 259 } 260 261 static void 262 auacer_attach(struct device *parent, struct device *self, void *aux) 263 { 264 struct auacer_softc *sc; 265 struct pci_attach_args *pa; 266 pci_intr_handle_t ih; 267 bus_size_t aud_size; 268 pcireg_t v; 269 const char *intrstr; 270 int i; 271 272 sc = (struct auacer_softc *)self; 273 pa = aux; 274 aprint_normal(": Acer Labs M5455 Audio controller\n"); 275 276 if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, &sc->iot, 277 &sc->aud_ioh, NULL, &aud_size)) { 278 aprint_error(": can't map i/o space\n"); 279 return; 280 } 281 282 sc->sc_pc = pa->pa_pc; 283 sc->sc_pt = pa->pa_tag; 284 sc->dmat = pa->pa_dmat; 285 286 sc->sc_dmamap_flags = BUS_DMA_COHERENT; /* XXX remove */ 287 288 /* enable bus mastering */ 289 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 290 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 291 v | PCI_COMMAND_MASTER_ENABLE); 292 293 /* Map and establish the interrupt. */ 294 if (pci_intr_map(pa, &ih)) { 295 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 296 return; 297 } 298 intrstr = pci_intr_string(pa->pa_pc, ih); 299 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 300 auacer_intr, sc); 301 if (sc->sc_ih == NULL) { 302 aprint_error("%s: can't establish interrupt", 303 sc->sc_dev.dv_xname); 304 if (intrstr != NULL) 305 aprint_normal(" at %s", intrstr); 306 aprint_normal("\n"); 307 return; 308 } 309 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 310 311 strlcpy(sc->sc_audev.name, "M5455 AC97", MAX_AUDIO_DEV_LEN); 312 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 313 "0x%02x", PCI_REVISION(pa->pa_class)); 314 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 315 316 /* Set up DMA lists. */ 317 auacer_alloc_cdata(sc); 318 sc->sc_pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 319 sc->sc_pcmo.ptr = 0; 320 sc->sc_pcmo.port = ALI_BASE_PO; 321 322 DPRINTF(ALI_DEBUG_DMA, ("auacer_attach: lists %p\n", 323 sc->sc_pcmo.dmalist)); 324 325 sc->host_if.arg = sc; 326 sc->host_if.attach = auacer_attach_codec; 327 sc->host_if.read = auacer_read_codec; 328 sc->host_if.write = auacer_write_codec; 329 sc->host_if.reset = auacer_reset_codec; 330 331 if (ac97_attach(&sc->host_if, self) != 0) 332 return; 333 334 /* setup audio_format */ 335 memcpy(sc->sc_formats, auacer_formats, sizeof(auacer_formats)); 336 if (!AC97_IS_4CH(sc->codec_if)) 337 AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_4CH]); 338 if (!AC97_IS_6CH(sc->codec_if)) 339 AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_6CH]); 340 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 341 for (i = 0; i < AUACER_NFORMATS; i++) { 342 sc->sc_formats[i].frequency_type = 1; 343 sc->sc_formats[i].frequency[0] = 48000; 344 } 345 } 346 347 if (0 != auconv_create_encodings(sc->sc_formats, AUACER_NFORMATS, 348 &sc->sc_encodings)) { 349 return; 350 } 351 352 /* Watch for power change */ 353 sc->sc_suspend = PWR_RESUME; 354 sc->sc_powerhook = powerhook_establish(auacer_powerhook, sc); 355 356 audio_attach_mi(&auacer_hw_if, sc, &sc->sc_dev); 357 358 auacer_reset(sc); 359 } 360 361 CFATTACH_DECL(auacer, sizeof(struct auacer_softc), 362 auacer_match, auacer_attach, NULL, NULL); 363 364 static int 365 auacer_ready_codec(struct auacer_softc *sc, int mask) 366 { 367 int count; 368 369 for (count = 0; count < 0x7f; count++) { 370 int val = READ1(sc, ALI_CSPSR); 371 if (val & mask) 372 return 0; 373 } 374 375 aprint_normal("auacer_ready_codec: AC97 codec ready timeout.\n"); 376 return EBUSY; 377 } 378 379 static int 380 auacer_sema_codec(struct auacer_softc *sc) 381 { 382 int ttime; 383 384 ttime = 100; 385 while (ttime-- && (READ4(sc, ALI_CAS) & ALI_CAS_SEM_BUSY)) 386 delay(1); 387 if (!ttime) 388 aprint_normal("auacer_sema_codec: timeout\n"); 389 return auacer_ready_codec(sc, ALI_CSPSR_CODEC_READY); 390 } 391 392 static int 393 auacer_read_codec(void *v, uint8_t reg, uint16_t *val) 394 { 395 struct auacer_softc *sc; 396 397 sc = v; 398 if (auacer_sema_codec(sc)) 399 return EIO; 400 401 reg |= ALI_CPR_ADDR_READ; 402 #if 0 403 if (ac97->num) 404 reg |= ALI_CPR_ADDR_SECONDARY; 405 #endif 406 WRITE2(sc, ALI_CPR_ADDR, reg); 407 if (auacer_ready_codec(sc, ALI_CSPSR_READ_OK)) 408 return EIO; 409 *val = READ2(sc, ALI_SPR); 410 411 DPRINTF(ALI_DEBUG_CODECIO, ("auacer_read_codec: reg=0x%x val=0x%x\n", 412 reg, *val)); 413 414 return 0; 415 } 416 417 int 418 auacer_write_codec(void *v, uint8_t reg, uint16_t val) 419 { 420 struct auacer_softc *sc; 421 422 DPRINTF(ALI_DEBUG_CODECIO, ("auacer_write_codec: reg=0x%x val=0x%x\n", 423 reg, val)); 424 sc = v; 425 if (auacer_sema_codec(sc)) 426 return EIO; 427 WRITE2(sc, ALI_CPR, val); 428 #if 0 429 if (ac97->num) 430 reg |= ALI_CPR_ADDR_SECONDARY; 431 #endif 432 WRITE2(sc, ALI_CPR_ADDR, reg); 433 auacer_ready_codec(sc, ALI_CSPSR_WRITE_OK); 434 return 0; 435 } 436 437 static int 438 auacer_attach_codec(void *v, struct ac97_codec_if *cif) 439 { 440 struct auacer_softc *sc; 441 442 sc = v; 443 sc->codec_if = cif; 444 return 0; 445 } 446 447 static int 448 auacer_reset_codec(void *v) 449 { 450 struct auacer_softc *sc; 451 uint32_t reg; 452 int i; 453 454 sc = v; 455 i = 0; 456 reg = READ4(sc, ALI_SCR); 457 if ((reg & 2) == 0) /* Cold required */ 458 reg |= 2; 459 else 460 reg |= 1; /* Warm */ 461 reg &= ~0x80000000; /* ACLink on */ 462 WRITE4(sc, ALI_SCR, reg); 463 464 while (i < 10) { 465 if ((READ4(sc, ALI_INTERRUPTSR) & ALI_INT_GPIO) == 0) 466 break; 467 delay(50000); /* XXX */ 468 i++; 469 } 470 if (i == 10) { 471 return EIO; 472 } 473 474 for (i = 0; i < 10; i++) { 475 reg = READ4(sc, ALI_RTSR); 476 if (reg & 0x80) /* primary codec */ 477 break; 478 WRITE4(sc, ALI_RTSR, reg | 0x80); 479 delay(50000); /* XXX */ 480 } 481 482 return 0; 483 } 484 485 static void 486 auacer_reset(struct auacer_softc *sc) 487 { 488 WRITE4(sc, ALI_SCR, ALI_SCR_RESET); 489 WRITE4(sc, ALI_FIFOCR1, 0x83838383); 490 WRITE4(sc, ALI_FIFOCR2, 0x83838383); 491 WRITE4(sc, ALI_FIFOCR3, 0x83838383); 492 WRITE4(sc, ALI_INTERFACECR, ALI_IF_PO); /* XXX pcm out only */ 493 WRITE4(sc, ALI_INTERRUPTCR, 0x00000000); 494 WRITE4(sc, ALI_INTERRUPTSR, 0x00000000); 495 } 496 497 static int 498 auacer_query_encoding(void *v, struct audio_encoding *aep) 499 { 500 struct auacer_softc *sc; 501 502 DPRINTF(ALI_DEBUG_API, ("auacer_query_encoding\n")); 503 sc = v; 504 return auconv_query_encoding(sc->sc_encodings, aep); 505 } 506 507 static int 508 auacer_set_rate(struct auacer_softc *sc, int mode, u_int srate) 509 { 510 int ret; 511 u_int ratetmp; 512 513 DPRINTF(ALI_DEBUG_API, ("auacer_set_rate: srate=%u\n", srate)); 514 515 ratetmp = srate; 516 if (mode == AUMODE_RECORD) 517 return sc->codec_if->vtbl->set_rate(sc->codec_if, 518 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 519 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 520 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 521 if (ret) 522 return ret; 523 ratetmp = srate; 524 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 525 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 526 if (ret) 527 return ret; 528 ratetmp = srate; 529 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 530 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 531 return ret; 532 } 533 534 static int 535 auacer_set_params(void *v, int setmode, int usemode, audio_params_t *play, 536 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 537 { 538 struct auacer_softc *sc; 539 struct audio_params *p; 540 stream_filter_list_t *fil; 541 uint32_t control; 542 int mode, index; 543 544 DPRINTF(ALI_DEBUG_API, ("auacer_set_params\n")); 545 sc = v; 546 for (mode = AUMODE_RECORD; mode != -1; 547 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 548 if ((setmode & mode) == 0) 549 continue; 550 551 p = mode == AUMODE_PLAY ? play : rec; 552 if (p == NULL) 553 continue; 554 555 if ((p->sample_rate != 8000) && 556 (p->sample_rate != 11025) && 557 (p->sample_rate != 12000) && 558 (p->sample_rate != 16000) && 559 (p->sample_rate != 22050) && 560 (p->sample_rate != 24000) && 561 (p->sample_rate != 32000) && 562 (p->sample_rate != 44100) && 563 (p->sample_rate != 48000)) 564 return (EINVAL); 565 566 fil = mode == AUMODE_PLAY ? pfil : rfil; 567 index = auconv_set_converter(sc->sc_formats, AUACER_NFORMATS, 568 mode, p, TRUE, fil); 569 if (index < 0) 570 return EINVAL; 571 if (fil->req_size > 0) 572 p = &fil->filters[0].param; 573 /* p points HW encoding */ 574 if (sc->sc_formats[index].frequency_type != 1 575 && auacer_set_rate(sc, mode, p->sample_rate)) 576 return EINVAL; 577 if (mode == AUMODE_PLAY) { 578 control = READ4(sc, ALI_SCR); 579 control &= ~ALI_SCR_PCM_246_MASK; 580 if (p->channels == 4) 581 control |= ALI_SCR_PCM_4; 582 else if (p->channels == 6) 583 control |= ALI_SCR_PCM_6; 584 WRITE4(sc, ALI_SCR, control); 585 } 586 } 587 588 return (0); 589 } 590 591 static int 592 auacer_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 593 { 594 595 return blk & ~0x3f; /* keep good alignment */ 596 } 597 598 static void 599 auacer_halt(struct auacer_softc *sc, struct auacer_chan *chan) 600 { 601 uint32_t val; 602 uint8_t port; 603 uint32_t slot; 604 605 port = chan->port; 606 DPRINTF(ALI_DEBUG_API, ("auacer_halt: port=0x%x\n", port)); 607 chan->intr = 0; 608 609 slot = ALI_PORT2SLOT(port); 610 611 val = READ4(sc, ALI_DMACR); 612 val |= 1 << (slot+16); /* pause */ 613 val &= ~(1 << slot); /* no start */ 614 WRITE4(sc, ALI_DMACR, val); 615 WRITE1(sc, port + ALI_OFF_CR, 0); 616 while (READ1(sc, port + ALI_OFF_CR)) 617 ; 618 /* reset whole DMA things */ 619 WRITE1(sc, port + ALI_OFF_CR, ALI_CR_RR); 620 /* clear interrupts */ 621 WRITE1(sc, port + ALI_OFF_SR, READ1(sc, port+ALI_OFF_SR) | ALI_SR_W1TC); 622 WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(port)); 623 } 624 625 static int 626 auacer_halt_output(void *v) 627 { 628 struct auacer_softc *sc; 629 630 DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_output\n")); 631 sc = v; 632 auacer_halt(sc, &sc->sc_pcmo); 633 634 return 0; 635 } 636 637 static int 638 auacer_halt_input(void *v) 639 { 640 /*struct auacer_softc *sc = v;*/ 641 642 DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_input\n")); 643 644 return 0; 645 } 646 647 static int 648 auacer_getdev(void *v, struct audio_device *adp) 649 { 650 struct auacer_softc *sc; 651 652 DPRINTF(ALI_DEBUG_API, ("auacer_getdev\n")); 653 sc = v; 654 *adp = sc->sc_audev; 655 return 0; 656 } 657 658 static int 659 auacer_set_port(void *v, mixer_ctrl_t *cp) 660 { 661 struct auacer_softc *sc; 662 663 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_set_port\n")); 664 sc = v; 665 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 666 } 667 668 static int 669 auacer_get_port(void *v, mixer_ctrl_t *cp) 670 { 671 struct auacer_softc *sc; 672 673 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_get_port\n")); 674 sc = v; 675 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 676 } 677 678 static int 679 auacer_query_devinfo(void *v, mixer_devinfo_t *dp) 680 { 681 struct auacer_softc *sc; 682 683 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_query_devinfo\n")); 684 sc = v; 685 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 686 } 687 688 static void * 689 auacer_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 690 int flags) 691 { 692 struct auacer_softc *sc; 693 struct auacer_dma *p; 694 int error; 695 696 if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX)) 697 return NULL; 698 699 p = malloc(sizeof(*p), pool, flags | M_ZERO); 700 if (p == NULL) 701 return NULL; 702 sc = v; 703 error = auacer_allocmem(sc, size, 0, p); 704 if (error) { 705 free(p, pool); 706 return NULL; 707 } 708 709 p->next = sc->sc_dmas; 710 sc->sc_dmas = p; 711 712 return KERNADDR(p); 713 } 714 715 static void 716 auacer_freem(void *v, void *ptr, struct malloc_type *pool) 717 { 718 struct auacer_softc *sc; 719 struct auacer_dma *p, **pp; 720 721 sc = v; 722 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 723 if (KERNADDR(p) == ptr) { 724 auacer_freemem(sc, p); 725 *pp = p->next; 726 free(p, pool); 727 return; 728 } 729 } 730 } 731 732 static size_t 733 auacer_round_buffersize(void *v, int direction, size_t size) 734 { 735 736 if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX)) 737 size = ALI_DMALIST_MAX * ALI_DMASEG_MAX; 738 739 return size; 740 } 741 742 static paddr_t 743 auacer_mappage(void *v, void *mem, off_t off, int prot) 744 { 745 struct auacer_softc *sc; 746 struct auacer_dma *p; 747 748 if (off < 0) 749 return -1; 750 sc = v; 751 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 752 continue; 753 if (p == NULL) 754 return -1; 755 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 756 off, prot, BUS_DMA_WAITOK); 757 } 758 759 static int 760 auacer_get_props(void *v) 761 { 762 struct auacer_softc *sc; 763 int props; 764 765 sc = v; 766 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 767 /* 768 * Even if the codec is fixed-rate, set_param() succeeds for any sample 769 * rate because of aurateconv. Applications can't know what rate the 770 * device can process in the case of mmap(). 771 */ 772 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 773 props |= AUDIO_PROP_MMAP; 774 return props; 775 } 776 777 static void 778 auacer_add_entry(struct auacer_chan *chan) 779 { 780 struct auacer_dmalist *q; 781 782 q = &chan->dmalist[chan->ptr]; 783 784 DPRINTF(ALI_DEBUG_INTR, 785 ("auacer_add_entry: %p = %x @ 0x%x\n", 786 q, chan->blksize / 2, chan->p)); 787 788 q->base = htole32(chan->p); 789 q->len = htole32((chan->blksize / ALI_SAMPLE_SIZE) | ALI_DMAF_IOC); 790 chan->p += chan->blksize; 791 if (chan->p >= chan->end) 792 chan->p = chan->start; 793 794 if (++chan->ptr >= ALI_DMALIST_MAX) 795 chan->ptr = 0; 796 } 797 798 static void 799 auacer_upd_chan(struct auacer_softc *sc, struct auacer_chan *chan) 800 { 801 uint32_t sts; 802 uint32_t civ; 803 804 sts = READ2(sc, chan->port + ALI_OFF_SR); 805 /* intr ack */ 806 WRITE2(sc, chan->port + ALI_OFF_SR, sts & ALI_SR_W1TC); 807 WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(chan->port)); 808 809 DPRINTF(ALI_DEBUG_INTR, ("auacer_upd_chan: sts=0x%x\n", sts)); 810 811 if (sts & ALI_SR_DMA_INT_FIFO) { 812 printf("%s: fifo underrun # %u\n", 813 sc->sc_dev.dv_xname, ++chan->fifoe); 814 } 815 816 civ = READ1(sc, chan->port + ALI_OFF_CIV); 817 818 DPRINTF(ALI_DEBUG_INTR,("auacer_intr: civ=%u ptr=%u\n",civ,chan->ptr)); 819 820 /* XXX */ 821 while (chan->ptr != civ) { 822 auacer_add_entry(chan); 823 } 824 825 WRITE1(sc, chan->port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK); 826 827 while (chan->ack != civ) { 828 if (chan->intr) { 829 DPRINTF(ALI_DEBUG_INTR,("auacer_upd_chan: callback\n")); 830 chan->intr(chan->arg); 831 } 832 chan->ack++; 833 if (chan->ack >= ALI_DMALIST_MAX) 834 chan->ack = 0; 835 } 836 } 837 838 static int 839 auacer_intr(void *v) 840 { 841 struct auacer_softc *sc; 842 int ret, intrs; 843 844 sc = v; 845 intrs = READ4(sc, ALI_INTERRUPTSR); 846 DPRINTF(ALI_DEBUG_INTR, ("auacer_intr: intrs=0x%x\n", intrs)); 847 848 ret = 0; 849 if (intrs & ALI_INT_PCMOUT) { 850 auacer_upd_chan(sc, &sc->sc_pcmo); 851 ret++; 852 } 853 854 return ret != 0; 855 } 856 857 static void 858 auacer_setup_chan(struct auacer_softc *sc, struct auacer_chan *chan, 859 uint32_t start, uint32_t size, uint32_t blksize, 860 void (*intr)(void *), void *arg) 861 { 862 uint32_t port, slot; 863 uint32_t offs, val; 864 865 chan->start = start; 866 chan->ptr = 0; 867 chan->p = chan->start; 868 chan->end = chan->start + size; 869 chan->blksize = blksize; 870 chan->ack = 0; 871 chan->intr = intr; 872 chan->arg = arg; 873 874 auacer_add_entry(chan); 875 auacer_add_entry(chan); 876 877 port = chan->port; 878 slot = ALI_PORT2SLOT(port); 879 880 WRITE1(sc, port + ALI_OFF_CIV, 0); 881 WRITE1(sc, port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK); 882 offs = (char *)chan->dmalist - (char *)sc->sc_cdata; 883 WRITE4(sc, port + ALI_OFF_BDBAR, sc->sc_cddma + offs); 884 WRITE1(sc, port + ALI_OFF_CR, 885 ALI_CR_IOCE | ALI_CR_FEIE | ALI_CR_LVBIE | ALI_CR_RPBM); 886 val = READ4(sc, ALI_DMACR); 887 val &= ~(1 << (slot+16)); /* no pause */ 888 val |= 1 << slot; /* start */ 889 WRITE4(sc, ALI_DMACR, val); 890 } 891 892 static int 893 auacer_trigger_output(void *v, void *start, void *end, int blksize, 894 void (*intr)(void *), void *arg, const audio_params_t *param) 895 { 896 struct auacer_softc *sc; 897 struct auacer_dma *p; 898 uint32_t size; 899 900 DPRINTF(ALI_DEBUG_DMA, 901 ("auacer_trigger_output(%p, %p, %d, %p, %p, %p)\n", 902 start, end, blksize, intr, arg, param)); 903 sc = v; 904 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 905 continue; 906 if (!p) { 907 printf("auacer_trigger_output: bad addr %p\n", start); 908 return (EINVAL); 909 } 910 911 size = (char *)end - (char *)start; 912 auacer_setup_chan(sc, &sc->sc_pcmo, DMAADDR(p), size, blksize, 913 intr, arg); 914 915 return 0; 916 } 917 918 static int 919 auacer_trigger_input(void *v, void *start, void *end, int blksize, 920 void (*intr)(void *), void *arg, 921 const audio_params_t *param) 922 { 923 return EINVAL; 924 } 925 926 static int 927 auacer_allocmem(struct auacer_softc *sc, size_t size, size_t align, 928 struct auacer_dma *p) 929 { 930 int error; 931 932 p->size = size; 933 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 934 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 935 &p->nsegs, BUS_DMA_NOWAIT); 936 if (error) 937 return error; 938 939 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 940 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 941 if (error) 942 goto free; 943 944 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 945 0, BUS_DMA_NOWAIT, &p->map); 946 if (error) 947 goto unmap; 948 949 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 950 BUS_DMA_NOWAIT); 951 if (error) 952 goto destroy; 953 return (0); 954 955 destroy: 956 bus_dmamap_destroy(sc->dmat, p->map); 957 unmap: 958 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 959 free: 960 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 961 return error; 962 } 963 964 static int 965 auacer_freemem(struct auacer_softc *sc, struct auacer_dma *p) 966 { 967 968 bus_dmamap_unload(sc->dmat, p->map); 969 bus_dmamap_destroy(sc->dmat, p->map); 970 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 971 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 972 return 0; 973 } 974 975 static int 976 auacer_alloc_cdata(struct auacer_softc *sc) 977 { 978 bus_dma_segment_t seg; 979 int error, rseg; 980 981 /* 982 * Allocate the control data structure, and create and load the 983 * DMA map for it. 984 */ 985 if ((error = bus_dmamem_alloc(sc->dmat, 986 sizeof(struct auacer_cdata), 987 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 988 printf("%s: unable to allocate control data, error = %d\n", 989 sc->sc_dev.dv_xname, error); 990 goto fail_0; 991 } 992 993 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 994 sizeof(struct auacer_cdata), 995 (caddr_t *) &sc->sc_cdata, 996 sc->sc_dmamap_flags)) != 0) { 997 printf("%s: unable to map control data, error = %d\n", 998 sc->sc_dev.dv_xname, error); 999 goto fail_1; 1000 } 1001 1002 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auacer_cdata), 1, 1003 sizeof(struct auacer_cdata), 0, 0, 1004 &sc->sc_cddmamap)) != 0) { 1005 printf("%s: unable to create control data DMA map, " 1006 "error = %d\n", sc->sc_dev.dv_xname, error); 1007 goto fail_2; 1008 } 1009 1010 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1011 sc->sc_cdata, sizeof(struct auacer_cdata), 1012 NULL, 0)) != 0) { 1013 printf("%s: unable to load control data DMA map, " 1014 "error = %d\n", sc->sc_dev.dv_xname, error); 1015 goto fail_3; 1016 } 1017 1018 return 0; 1019 1020 fail_3: 1021 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1022 fail_2: 1023 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1024 sizeof(struct auacer_cdata)); 1025 fail_1: 1026 bus_dmamem_free(sc->dmat, &seg, rseg); 1027 fail_0: 1028 return error; 1029 } 1030 1031 static void 1032 auacer_powerhook(int why, void *addr) 1033 { 1034 struct auacer_softc *sc; 1035 1036 sc = (struct auacer_softc *)addr; 1037 switch (why) { 1038 case PWR_SUSPEND: 1039 case PWR_STANDBY: 1040 /* Power down */ 1041 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1042 sc->sc_suspend = why; 1043 break; 1044 1045 case PWR_RESUME: 1046 /* Wake up */ 1047 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1048 if (sc->sc_suspend == PWR_RESUME) { 1049 printf("%s: resume without suspend.\n", 1050 sc->sc_dev.dv_xname); 1051 sc->sc_suspend = why; 1052 return; 1053 } 1054 sc->sc_suspend = why; 1055 auacer_reset_codec(sc); 1056 delay(1000); 1057 sc->codec_if->vtbl->restore_ports(sc->codec_if); 1058 break; 1059 1060 case PWR_SOFTSUSPEND: 1061 case PWR_SOFTSTANDBY: 1062 case PWR_SOFTRESUME: 1063 break; 1064 } 1065 } 1066
Indexes created Fri Oct 03 02:09:57 GMT 2025