auacer.c revision 1.15.6.1
1 /* $NetBSD: auacer.c,v 1.15.6.1 2007/02/27 14:16:13 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Acer Labs M5455 audio driver 41 * 42 * Acer provides data sheets after signing an NDA, so this is guess work. 43 * The chip behaves somewhat like the Intel i8x0, so this driver 44 * is loosely based on the auich driver. Additional information taken from 45 * the ALSA intel8x0.c driver (which handles M5455 as well). 46 * 47 * As an historical note one can observe that the auich driver borrows 48 * lot from the first NetBSD PCI audio driver, the eap driver. But this 49 * is not attributed anywhere. 50 */ 51 52 53 #include <sys/cdefs.h> 54 __KERNEL_RCSID(0, "$NetBSD: auacer.c,v 1.15.6.1 2007/02/27 14:16:13 ad Exp $"); 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/malloc.h> 60 #include <sys/device.h> 61 #include <sys/fcntl.h> 62 #include <sys/proc.h> 63 64 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 65 66 #include <dev/pci/pcidevs.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/auacerreg.h> 69 70 #include <sys/audioio.h> 71 #include <dev/audio_if.h> 72 #include <dev/mulaw.h> 73 #include <dev/auconv.h> 74 75 #include <machine/bus.h> 76 77 #include <dev/ic/ac97reg.h> 78 #include <dev/ic/ac97var.h> 79 80 struct auacer_dma { 81 bus_dmamap_t map; 82 caddr_t addr; 83 bus_dma_segment_t segs[1]; 84 int nsegs; 85 size_t size; 86 struct auacer_dma *next; 87 }; 88 89 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 90 #define KERNADDR(p) ((void *)((p)->addr)) 91 92 struct auacer_cdata { 93 struct auacer_dmalist ic_dmalist_pcmo[ALI_DMALIST_MAX]; 94 }; 95 96 struct auacer_chan { 97 uint32_t ptr; 98 uint32_t start, p, end; 99 uint32_t blksize, fifoe; 100 uint32_t ack; 101 uint32_t port; 102 struct auacer_dmalist *dmalist; 103 void (*intr)(void *); 104 void *arg; 105 }; 106 107 struct auacer_softc { 108 struct device sc_dev; 109 void *sc_ih; 110 kmutex_t sc_lock; 111 kmutex_t sc_intr_lock; 112 113 audio_device_t sc_audev; 114 115 bus_space_tag_t iot; 116 bus_space_handle_t mix_ioh; 117 bus_space_handle_t aud_ioh; 118 bus_dma_tag_t dmat; 119 120 struct ac97_codec_if *codec_if; 121 struct ac97_host_if host_if; 122 123 /* DMA scatter-gather lists. */ 124 bus_dmamap_t sc_cddmamap; 125 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 126 127 struct auacer_cdata *sc_cdata; 128 129 struct auacer_chan sc_pcmo; 130 131 struct auacer_dma *sc_dmas; 132 133 pci_chipset_tag_t sc_pc; 134 pcitag_t sc_pt; 135 136 int sc_dmamap_flags; 137 138 /* Power Management */ 139 void *sc_powerhook; 140 int sc_suspend; 141 142 #define AUACER_NFORMATS 3 143 struct audio_format sc_formats[AUACER_NFORMATS]; 144 struct audio_encoding_set *sc_encodings; 145 }; 146 147 #define READ1(sc, a) bus_space_read_1(sc->iot, sc->aud_ioh, a) 148 #define READ2(sc, a) bus_space_read_2(sc->iot, sc->aud_ioh, a) 149 #define READ4(sc, a) bus_space_read_4(sc->iot, sc->aud_ioh, a) 150 #define WRITE1(sc, a, v) bus_space_write_1(sc->iot, sc->aud_ioh, a, v) 151 #define WRITE2(sc, a, v) bus_space_write_2(sc->iot, sc->aud_ioh, a, v) 152 #define WRITE4(sc, a, v) bus_space_write_4(sc->iot, sc->aud_ioh, a, v) 153 154 /* Debug */ 155 #ifdef AUACER_DEBUG 156 #define DPRINTF(l,x) do { if (auacer_debug & (l)) printf x; } while(0) 157 int auacer_debug = 0; 158 #define ALI_DEBUG_CODECIO 0x0001 159 #define ALI_DEBUG_DMA 0x0002 160 #define ALI_DEBUG_INTR 0x0004 161 #define ALI_DEBUG_API 0x0008 162 #define ALI_DEBUG_MIXERAPI 0x0010 163 #else 164 #define DPRINTF(x,y) /* nothing */ 165 #endif 166 167 static int auacer_intr(void *); 168 169 static int auacer_query_encoding(void *, struct audio_encoding *); 170 static int auacer_set_params(void *, int, int, audio_params_t *, 171 audio_params_t *, stream_filter_list_t *, 172 stream_filter_list_t *); 173 static int auacer_round_blocksize(void *, int, int, 174 const audio_params_t *); 175 static int auacer_halt_output(void *); 176 static int auacer_halt_input(void *); 177 static int auacer_getdev(void *, struct audio_device *); 178 static int auacer_set_port(void *, mixer_ctrl_t *); 179 static int auacer_get_port(void *, mixer_ctrl_t *); 180 static int auacer_query_devinfo(void *, mixer_devinfo_t *); 181 static void *auacer_allocm(void *, int, size_t, struct malloc_type *, int); 182 static void auacer_freem(void *, void *, struct malloc_type *); 183 static size_t auacer_round_buffersize(void *, int, size_t); 184 static paddr_t auacer_mappage(void *, void *, off_t, int); 185 static int auacer_get_props(void *); 186 static int auacer_trigger_output(void *, void *, void *, int, 187 void (*)(void *), void *, 188 const audio_params_t *); 189 static int auacer_trigger_input(void *, void *, void *, int, 190 void (*)(void *), void *, 191 const audio_params_t *); 192 193 static int auacer_alloc_cdata(struct auacer_softc *); 194 195 static int auacer_allocmem(struct auacer_softc *, size_t, size_t, 196 struct auacer_dma *); 197 static int auacer_freemem(struct auacer_softc *, struct auacer_dma *); 198 199 static void auacer_powerhook(int, void *); 200 static int auacer_set_rate(struct auacer_softc *, int, u_int); 201 static void auacer_get_locks(void *, kmutex_t **, kmutex_t **); 202 203 static void auacer_reset(struct auacer_softc *sc); 204 205 static struct audio_hw_if auacer_hw_if = { 206 NULL, /* open */ 207 NULL, /* close */ 208 NULL, /* drain */ 209 auacer_query_encoding, 210 auacer_set_params, 211 auacer_round_blocksize, 212 NULL, /* commit_setting */ 213 NULL, /* init_output */ 214 NULL, /* init_input */ 215 NULL, /* start_output */ 216 NULL, /* start_input */ 217 auacer_halt_output, 218 auacer_halt_input, 219 NULL, /* speaker_ctl */ 220 auacer_getdev, 221 NULL, /* getfd */ 222 auacer_set_port, 223 auacer_get_port, 224 auacer_query_devinfo, 225 auacer_allocm, 226 auacer_freem, 227 auacer_round_buffersize, 228 auacer_mappage, 229 auacer_get_props, 230 auacer_trigger_output, 231 auacer_trigger_input, 232 NULL, /* dev_ioctl */ 233 NULL, /* powerstate */ 234 auacer_get_locks, 235 }; 236 237 #define AUACER_FORMATS_4CH 1 238 #define AUACER_FORMATS_6CH 2 239 static const struct audio_format auacer_formats[AUACER_NFORMATS] = { 240 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 241 2, AUFMT_STEREO, 0, {8000, 48000}}, 242 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 243 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 244 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 245 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 246 }; 247 248 static int auacer_attach_codec(void *, struct ac97_codec_if *); 249 static int auacer_read_codec(void *, uint8_t, uint16_t *); 250 static int auacer_write_codec(void *, uint8_t, uint16_t); 251 static int auacer_reset_codec(void *); 252 253 static int 254 auacer_match(struct device *parent, struct cfdata *match, 255 void *aux) 256 { 257 struct pci_attach_args *pa; 258 259 pa = (struct pci_attach_args *)aux; 260 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 261 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M5455) 262 return 1; 263 return 0; 264 } 265 266 static void 267 auacer_attach(struct device *parent, struct device *self, void *aux) 268 { 269 struct auacer_softc *sc; 270 struct pci_attach_args *pa; 271 pci_intr_handle_t ih; 272 bus_size_t aud_size; 273 pcireg_t v; 274 const char *intrstr; 275 int i; 276 277 sc = (struct auacer_softc *)self; 278 pa = aux; 279 aprint_normal(": Acer Labs M5455 Audio controller\n"); 280 281 if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, &sc->iot, 282 &sc->aud_ioh, NULL, &aud_size)) { 283 aprint_error(": can't map i/o space\n"); 284 return; 285 } 286 287 sc->sc_pc = pa->pa_pc; 288 sc->sc_pt = pa->pa_tag; 289 sc->dmat = pa->pa_dmat; 290 291 sc->sc_dmamap_flags = BUS_DMA_COHERENT; /* XXX remove */ 292 293 /* enable bus mastering */ 294 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 295 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 296 v | PCI_COMMAND_MASTER_ENABLE); 297 298 mutex_init(&sc->sc_lock, MUTEX_DRIVER, IPL_NONE); 299 mutex_init(&sc->sc_intr_lock, MUTEX_DRIVER, IPL_AUDIO); 300 301 /* Map and establish the interrupt. */ 302 if (pci_intr_map(pa, &ih)) { 303 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 304 return; 305 } 306 intrstr = pci_intr_string(pa->pa_pc, ih); 307 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 308 auacer_intr, sc); 309 if (sc->sc_ih == NULL) { 310 aprint_error("%s: can't establish interrupt", 311 sc->sc_dev.dv_xname); 312 if (intrstr != NULL) 313 aprint_normal(" at %s", intrstr); 314 aprint_normal("\n"); 315 return; 316 } 317 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 318 319 strlcpy(sc->sc_audev.name, "M5455 AC97", MAX_AUDIO_DEV_LEN); 320 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 321 "0x%02x", PCI_REVISION(pa->pa_class)); 322 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 323 324 /* Set up DMA lists. */ 325 auacer_alloc_cdata(sc); 326 sc->sc_pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 327 sc->sc_pcmo.ptr = 0; 328 sc->sc_pcmo.port = ALI_BASE_PO; 329 330 DPRINTF(ALI_DEBUG_DMA, ("auacer_attach: lists %p\n", 331 sc->sc_pcmo.dmalist)); 332 333 sc->host_if.arg = sc; 334 sc->host_if.attach = auacer_attach_codec; 335 sc->host_if.read = auacer_read_codec; 336 sc->host_if.write = auacer_write_codec; 337 sc->host_if.reset = auacer_reset_codec; 338 339 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) 340 return; 341 342 /* setup audio_format */ 343 memcpy(sc->sc_formats, auacer_formats, sizeof(auacer_formats)); 344 if (!AC97_IS_4CH(sc->codec_if)) 345 AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_4CH]); 346 if (!AC97_IS_6CH(sc->codec_if)) 347 AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_6CH]); 348 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 349 for (i = 0; i < AUACER_NFORMATS; i++) { 350 sc->sc_formats[i].frequency_type = 1; 351 sc->sc_formats[i].frequency[0] = 48000; 352 } 353 } 354 355 if (0 != auconv_create_encodings(sc->sc_formats, AUACER_NFORMATS, 356 &sc->sc_encodings)) { 357 return; 358 } 359 360 /* Watch for power change */ 361 sc->sc_suspend = PWR_RESUME; 362 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 363 auacer_powerhook, sc); 364 365 audio_attach_mi(&auacer_hw_if, sc, &sc->sc_dev); 366 367 auacer_reset(sc); 368 } 369 370 CFATTACH_DECL(auacer, sizeof(struct auacer_softc), 371 auacer_match, auacer_attach, NULL, NULL); 372 373 static int 374 auacer_ready_codec(struct auacer_softc *sc, int mask) 375 { 376 int count; 377 378 for (count = 0; count < 0x7f; count++) { 379 int val = READ1(sc, ALI_CSPSR); 380 if (val & mask) 381 return 0; 382 } 383 384 aprint_normal("auacer_ready_codec: AC97 codec ready timeout.\n"); 385 return EBUSY; 386 } 387 388 static int 389 auacer_sema_codec(struct auacer_softc *sc) 390 { 391 int ttime; 392 393 ttime = 100; 394 while (ttime-- && (READ4(sc, ALI_CAS) & ALI_CAS_SEM_BUSY)) 395 delay(1); 396 if (!ttime) 397 aprint_normal("auacer_sema_codec: timeout\n"); 398 return auacer_ready_codec(sc, ALI_CSPSR_CODEC_READY); 399 } 400 401 static int 402 auacer_read_codec(void *v, uint8_t reg, uint16_t *val) 403 { 404 struct auacer_softc *sc; 405 406 sc = v; 407 if (auacer_sema_codec(sc)) 408 return EIO; 409 410 reg |= ALI_CPR_ADDR_READ; 411 #if 0 412 if (ac97->num) 413 reg |= ALI_CPR_ADDR_SECONDARY; 414 #endif 415 WRITE2(sc, ALI_CPR_ADDR, reg); 416 if (auacer_ready_codec(sc, ALI_CSPSR_READ_OK)) 417 return EIO; 418 *val = READ2(sc, ALI_SPR); 419 420 DPRINTF(ALI_DEBUG_CODECIO, ("auacer_read_codec: reg=0x%x val=0x%x\n", 421 reg, *val)); 422 423 return 0; 424 } 425 426 int 427 auacer_write_codec(void *v, uint8_t reg, uint16_t val) 428 { 429 struct auacer_softc *sc; 430 431 DPRINTF(ALI_DEBUG_CODECIO, ("auacer_write_codec: reg=0x%x val=0x%x\n", 432 reg, val)); 433 sc = v; 434 if (auacer_sema_codec(sc)) 435 return EIO; 436 WRITE2(sc, ALI_CPR, val); 437 #if 0 438 if (ac97->num) 439 reg |= ALI_CPR_ADDR_SECONDARY; 440 #endif 441 WRITE2(sc, ALI_CPR_ADDR, reg); 442 auacer_ready_codec(sc, ALI_CSPSR_WRITE_OK); 443 return 0; 444 } 445 446 static int 447 auacer_attach_codec(void *v, struct ac97_codec_if *cif) 448 { 449 struct auacer_softc *sc; 450 451 sc = v; 452 sc->codec_if = cif; 453 return 0; 454 } 455 456 static int 457 auacer_reset_codec(void *v) 458 { 459 struct auacer_softc *sc; 460 uint32_t reg; 461 int i; 462 463 sc = v; 464 i = 0; 465 reg = READ4(sc, ALI_SCR); 466 if ((reg & 2) == 0) /* Cold required */ 467 reg |= 2; 468 else 469 reg |= 1; /* Warm */ 470 reg &= ~0x80000000; /* ACLink on */ 471 WRITE4(sc, ALI_SCR, reg); 472 473 while (i < 10) { 474 if ((READ4(sc, ALI_INTERRUPTSR) & ALI_INT_GPIO) == 0) 475 break; 476 delay(50000); /* XXX */ 477 i++; 478 } 479 if (i == 10) { 480 return EIO; 481 } 482 483 for (i = 0; i < 10; i++) { 484 reg = READ4(sc, ALI_RTSR); 485 if (reg & 0x80) /* primary codec */ 486 break; 487 WRITE4(sc, ALI_RTSR, reg | 0x80); 488 delay(50000); /* XXX */ 489 } 490 491 return 0; 492 } 493 494 static void 495 auacer_reset(struct auacer_softc *sc) 496 { 497 WRITE4(sc, ALI_SCR, ALI_SCR_RESET); 498 WRITE4(sc, ALI_FIFOCR1, 0x83838383); 499 WRITE4(sc, ALI_FIFOCR2, 0x83838383); 500 WRITE4(sc, ALI_FIFOCR3, 0x83838383); 501 WRITE4(sc, ALI_INTERFACECR, ALI_IF_PO); /* XXX pcm out only */ 502 WRITE4(sc, ALI_INTERRUPTCR, 0x00000000); 503 WRITE4(sc, ALI_INTERRUPTSR, 0x00000000); 504 } 505 506 static int 507 auacer_query_encoding(void *v, struct audio_encoding *aep) 508 { 509 struct auacer_softc *sc; 510 511 DPRINTF(ALI_DEBUG_API, ("auacer_query_encoding\n")); 512 sc = v; 513 return auconv_query_encoding(sc->sc_encodings, aep); 514 } 515 516 static int 517 auacer_set_rate(struct auacer_softc *sc, int mode, u_int srate) 518 { 519 int ret; 520 u_int ratetmp; 521 522 DPRINTF(ALI_DEBUG_API, ("auacer_set_rate: srate=%u\n", srate)); 523 524 ratetmp = srate; 525 if (mode == AUMODE_RECORD) 526 return sc->codec_if->vtbl->set_rate(sc->codec_if, 527 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 528 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 529 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 530 if (ret) 531 return ret; 532 ratetmp = srate; 533 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 534 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 535 if (ret) 536 return ret; 537 ratetmp = srate; 538 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 539 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 540 return ret; 541 } 542 543 static int 544 auacer_set_params(void *v, int setmode, int usemode, 545 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 546 stream_filter_list_t *rfil) 547 { 548 struct auacer_softc *sc; 549 struct audio_params *p; 550 stream_filter_list_t *fil; 551 uint32_t control; 552 int mode, index; 553 554 DPRINTF(ALI_DEBUG_API, ("auacer_set_params\n")); 555 sc = v; 556 for (mode = AUMODE_RECORD; mode != -1; 557 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 558 if ((setmode & mode) == 0) 559 continue; 560 561 p = mode == AUMODE_PLAY ? play : rec; 562 if (p == NULL) 563 continue; 564 565 if ((p->sample_rate != 8000) && 566 (p->sample_rate != 11025) && 567 (p->sample_rate != 12000) && 568 (p->sample_rate != 16000) && 569 (p->sample_rate != 22050) && 570 (p->sample_rate != 24000) && 571 (p->sample_rate != 32000) && 572 (p->sample_rate != 44100) && 573 (p->sample_rate != 48000)) 574 return (EINVAL); 575 576 fil = mode == AUMODE_PLAY ? pfil : rfil; 577 index = auconv_set_converter(sc->sc_formats, AUACER_NFORMATS, 578 mode, p, TRUE, fil); 579 if (index < 0) 580 return EINVAL; 581 if (fil->req_size > 0) 582 p = &fil->filters[0].param; 583 /* p points HW encoding */ 584 if (sc->sc_formats[index].frequency_type != 1 585 && auacer_set_rate(sc, mode, p->sample_rate)) 586 return EINVAL; 587 if (mode == AUMODE_PLAY) { 588 control = READ4(sc, ALI_SCR); 589 control &= ~ALI_SCR_PCM_246_MASK; 590 if (p->channels == 4) 591 control |= ALI_SCR_PCM_4; 592 else if (p->channels == 6) 593 control |= ALI_SCR_PCM_6; 594 WRITE4(sc, ALI_SCR, control); 595 } 596 } 597 598 return (0); 599 } 600 601 static int 602 auacer_round_blocksize(void *v, int blk, int mode, 603 const audio_params_t *param) 604 { 605 606 return blk & ~0x3f; /* keep good alignment */ 607 } 608 609 static void 610 auacer_halt(struct auacer_softc *sc, struct auacer_chan *chan) 611 { 612 uint32_t val; 613 uint8_t port; 614 uint32_t slot; 615 616 port = chan->port; 617 DPRINTF(ALI_DEBUG_API, ("auacer_halt: port=0x%x\n", port)); 618 chan->intr = 0; 619 620 slot = ALI_PORT2SLOT(port); 621 622 val = READ4(sc, ALI_DMACR); 623 val |= 1 << (slot+16); /* pause */ 624 val &= ~(1 << slot); /* no start */ 625 WRITE4(sc, ALI_DMACR, val); 626 WRITE1(sc, port + ALI_OFF_CR, 0); 627 while (READ1(sc, port + ALI_OFF_CR)) 628 ; 629 /* reset whole DMA things */ 630 WRITE1(sc, port + ALI_OFF_CR, ALI_CR_RR); 631 /* clear interrupts */ 632 WRITE1(sc, port + ALI_OFF_SR, READ1(sc, port+ALI_OFF_SR) | ALI_SR_W1TC); 633 WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(port)); 634 } 635 636 static int 637 auacer_halt_output(void *v) 638 { 639 struct auacer_softc *sc; 640 641 DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_output\n")); 642 sc = v; 643 auacer_halt(sc, &sc->sc_pcmo); 644 645 return 0; 646 } 647 648 static int 649 auacer_halt_input(void *v) 650 { 651 DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_input\n")); 652 653 return 0; 654 } 655 656 static int 657 auacer_getdev(void *v, struct audio_device *adp) 658 { 659 struct auacer_softc *sc; 660 661 DPRINTF(ALI_DEBUG_API, ("auacer_getdev\n")); 662 sc = v; 663 *adp = sc->sc_audev; 664 return 0; 665 } 666 667 static int 668 auacer_set_port(void *v, mixer_ctrl_t *cp) 669 { 670 struct auacer_softc *sc; 671 672 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_set_port\n")); 673 sc = v; 674 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 675 } 676 677 static int 678 auacer_get_port(void *v, mixer_ctrl_t *cp) 679 { 680 struct auacer_softc *sc; 681 682 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_get_port\n")); 683 sc = v; 684 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 685 } 686 687 static int 688 auacer_query_devinfo(void *v, mixer_devinfo_t *dp) 689 { 690 struct auacer_softc *sc; 691 692 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_query_devinfo\n")); 693 sc = v; 694 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 695 } 696 697 static void * 698 auacer_allocm(void *v, int direction, size_t size, 699 struct malloc_type *pool, int flags) 700 { 701 struct auacer_softc *sc; 702 struct auacer_dma *p; 703 int error; 704 705 if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX)) 706 return NULL; 707 708 p = malloc(sizeof(*p), pool, flags | M_ZERO); 709 if (p == NULL) 710 return NULL; 711 sc = v; 712 error = auacer_allocmem(sc, size, 0, p); 713 if (error) { 714 free(p, pool); 715 return NULL; 716 } 717 718 p->next = sc->sc_dmas; 719 sc->sc_dmas = p; 720 721 return KERNADDR(p); 722 } 723 724 static void 725 auacer_freem(void *v, void *ptr, struct malloc_type *pool) 726 { 727 struct auacer_softc *sc; 728 struct auacer_dma *p, **pp; 729 730 sc = v; 731 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 732 if (KERNADDR(p) == ptr) { 733 auacer_freemem(sc, p); 734 *pp = p->next; 735 free(p, pool); 736 return; 737 } 738 } 739 } 740 741 static size_t 742 auacer_round_buffersize(void *v, int direction, size_t size) 743 { 744 745 if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX)) 746 size = ALI_DMALIST_MAX * ALI_DMASEG_MAX; 747 748 return size; 749 } 750 751 static paddr_t 752 auacer_mappage(void *v, void *mem, off_t off, int prot) 753 { 754 struct auacer_softc *sc; 755 struct auacer_dma *p; 756 paddr_t pa; 757 758 if (off < 0) 759 return -1; 760 sc = v; 761 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 762 continue; 763 if (p == NULL) 764 return -1; 765 766 mutex_exit(&sc->sc_lock); 767 pa = bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 768 off, prot, BUS_DMA_WAITOK); 769 mutex_enter(&sc->sc_lock); 770 771 return pa; 772 } 773 774 static int 775 auacer_get_props(void *v) 776 { 777 struct auacer_softc *sc; 778 int props; 779 780 sc = v; 781 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 782 /* 783 * Even if the codec is fixed-rate, set_param() succeeds for any sample 784 * rate because of aurateconv. Applications can't know what rate the 785 * device can process in the case of mmap(). 786 */ 787 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 788 props |= AUDIO_PROP_MMAP; 789 return props; 790 } 791 792 static void 793 auacer_add_entry(struct auacer_chan *chan) 794 { 795 struct auacer_dmalist *q; 796 797 q = &chan->dmalist[chan->ptr]; 798 799 DPRINTF(ALI_DEBUG_INTR, 800 ("auacer_add_entry: %p = %x @ 0x%x\n", 801 q, chan->blksize / 2, chan->p)); 802 803 q->base = htole32(chan->p); 804 q->len = htole32((chan->blksize / ALI_SAMPLE_SIZE) | ALI_DMAF_IOC); 805 chan->p += chan->blksize; 806 if (chan->p >= chan->end) 807 chan->p = chan->start; 808 809 if (++chan->ptr >= ALI_DMALIST_MAX) 810 chan->ptr = 0; 811 } 812 813 static void 814 auacer_upd_chan(struct auacer_softc *sc, struct auacer_chan *chan) 815 { 816 uint32_t sts; 817 uint32_t civ; 818 819 sts = READ2(sc, chan->port + ALI_OFF_SR); 820 /* intr ack */ 821 WRITE2(sc, chan->port + ALI_OFF_SR, sts & ALI_SR_W1TC); 822 WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(chan->port)); 823 824 DPRINTF(ALI_DEBUG_INTR, ("auacer_upd_chan: sts=0x%x\n", sts)); 825 826 if (sts & ALI_SR_DMA_INT_FIFO) { 827 printf("%s: fifo underrun # %u\n", 828 sc->sc_dev.dv_xname, ++chan->fifoe); 829 } 830 831 civ = READ1(sc, chan->port + ALI_OFF_CIV); 832 833 DPRINTF(ALI_DEBUG_INTR,("auacer_intr: civ=%u ptr=%u\n",civ,chan->ptr)); 834 835 /* XXX */ 836 while (chan->ptr != civ) { 837 auacer_add_entry(chan); 838 } 839 840 WRITE1(sc, chan->port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK); 841 842 while (chan->ack != civ) { 843 if (chan->intr) { 844 DPRINTF(ALI_DEBUG_INTR,("auacer_upd_chan: callback\n")); 845 chan->intr(chan->arg); 846 } 847 chan->ack++; 848 if (chan->ack >= ALI_DMALIST_MAX) 849 chan->ack = 0; 850 } 851 } 852 853 static int 854 auacer_intr(void *v) 855 { 856 struct auacer_softc *sc; 857 int ret, intrs; 858 859 sc = v; 860 861 mutex_enter(&sc->sc_intr_lock); 862 863 intrs = READ4(sc, ALI_INTERRUPTSR); 864 DPRINTF(ALI_DEBUG_INTR, ("auacer_intr: intrs=0x%x\n", intrs)); 865 866 ret = 0; 867 if (intrs & ALI_INT_PCMOUT) { 868 auacer_upd_chan(sc, &sc->sc_pcmo); 869 ret++; 870 } 871 872 mutex_exit(&sc->sc_intr_lock); 873 874 return ret != 0; 875 } 876 877 static void 878 auacer_setup_chan(struct auacer_softc *sc, struct auacer_chan *chan, 879 uint32_t start, uint32_t size, uint32_t blksize, 880 void (*intr)(void *), void *arg) 881 { 882 uint32_t port, slot; 883 uint32_t offs, val; 884 885 chan->start = start; 886 chan->ptr = 0; 887 chan->p = chan->start; 888 chan->end = chan->start + size; 889 chan->blksize = blksize; 890 chan->ack = 0; 891 chan->intr = intr; 892 chan->arg = arg; 893 894 auacer_add_entry(chan); 895 auacer_add_entry(chan); 896 897 port = chan->port; 898 slot = ALI_PORT2SLOT(port); 899 900 WRITE1(sc, port + ALI_OFF_CIV, 0); 901 WRITE1(sc, port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK); 902 offs = (char *)chan->dmalist - (char *)sc->sc_cdata; 903 WRITE4(sc, port + ALI_OFF_BDBAR, sc->sc_cddma + offs); 904 WRITE1(sc, port + ALI_OFF_CR, 905 ALI_CR_IOCE | ALI_CR_FEIE | ALI_CR_LVBIE | ALI_CR_RPBM); 906 val = READ4(sc, ALI_DMACR); 907 val &= ~(1 << (slot+16)); /* no pause */ 908 val |= 1 << slot; /* start */ 909 WRITE4(sc, ALI_DMACR, val); 910 } 911 912 static int 913 auacer_trigger_output(void *v, void *start, void *end, int blksize, 914 void (*intr)(void *), void *arg, const audio_params_t *param) 915 { 916 struct auacer_softc *sc; 917 struct auacer_dma *p; 918 uint32_t size; 919 920 DPRINTF(ALI_DEBUG_DMA, 921 ("auacer_trigger_output(%p, %p, %d, %p, %p, %p)\n", 922 start, end, blksize, intr, arg, param)); 923 sc = v; 924 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 925 continue; 926 if (!p) { 927 printf("auacer_trigger_output: bad addr %p\n", start); 928 return (EINVAL); 929 } 930 931 size = (char *)end - (char *)start; 932 auacer_setup_chan(sc, &sc->sc_pcmo, DMAADDR(p), size, blksize, 933 intr, arg); 934 935 return 0; 936 } 937 938 static int 939 auacer_trigger_input(void *v, void *start, void *end, 940 int blksize, void (*intr)(void *), void *arg, 941 const audio_params_t *param) 942 { 943 return EINVAL; 944 } 945 946 static int 947 auacer_allocmem(struct auacer_softc *sc, size_t size, size_t align, 948 struct auacer_dma *p) 949 { 950 int error; 951 952 p->size = size; 953 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 954 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 955 &p->nsegs, BUS_DMA_NOWAIT); 956 if (error) 957 return error; 958 959 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 960 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 961 if (error) 962 goto free; 963 964 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 965 0, BUS_DMA_NOWAIT, &p->map); 966 if (error) 967 goto unmap; 968 969 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 970 BUS_DMA_NOWAIT); 971 if (error) 972 goto destroy; 973 return (0); 974 975 destroy: 976 bus_dmamap_destroy(sc->dmat, p->map); 977 unmap: 978 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 979 free: 980 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 981 return error; 982 } 983 984 static int 985 auacer_freemem(struct auacer_softc *sc, struct auacer_dma *p) 986 { 987 988 bus_dmamap_unload(sc->dmat, p->map); 989 bus_dmamap_destroy(sc->dmat, p->map); 990 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 991 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 992 return 0; 993 } 994 995 static int 996 auacer_alloc_cdata(struct auacer_softc *sc) 997 { 998 bus_dma_segment_t seg; 999 int error, rseg; 1000 1001 /* 1002 * Allocate the control data structure, and create and load the 1003 * DMA map for it. 1004 */ 1005 if ((error = bus_dmamem_alloc(sc->dmat, 1006 sizeof(struct auacer_cdata), 1007 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1008 printf("%s: unable to allocate control data, error = %d\n", 1009 sc->sc_dev.dv_xname, error); 1010 goto fail_0; 1011 } 1012 1013 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1014 sizeof(struct auacer_cdata), 1015 (caddr_t *) &sc->sc_cdata, 1016 sc->sc_dmamap_flags)) != 0) { 1017 printf("%s: unable to map control data, error = %d\n", 1018 sc->sc_dev.dv_xname, error); 1019 goto fail_1; 1020 } 1021 1022 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auacer_cdata), 1, 1023 sizeof(struct auacer_cdata), 0, 0, 1024 &sc->sc_cddmamap)) != 0) { 1025 printf("%s: unable to create control data DMA map, " 1026 "error = %d\n", sc->sc_dev.dv_xname, error); 1027 goto fail_2; 1028 } 1029 1030 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1031 sc->sc_cdata, sizeof(struct auacer_cdata), 1032 NULL, 0)) != 0) { 1033 printf("%s: unable to load control data DMA map, " 1034 "error = %d\n", sc->sc_dev.dv_xname, error); 1035 goto fail_3; 1036 } 1037 1038 return 0; 1039 1040 fail_3: 1041 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1042 fail_2: 1043 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1044 sizeof(struct auacer_cdata)); 1045 fail_1: 1046 bus_dmamem_free(sc->dmat, &seg, rseg); 1047 fail_0: 1048 return error; 1049 } 1050 1051 static void 1052 auacer_powerhook(int why, void *addr) 1053 { 1054 struct auacer_softc *sc; 1055 1056 sc = (struct auacer_softc *)addr; 1057 1058 mutex_enter(&sc->sc_lock); 1059 1060 switch (why) { 1061 case PWR_SUSPEND: 1062 case PWR_STANDBY: 1063 /* Power down */ 1064 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1065 sc->sc_suspend = why; 1066 break; 1067 1068 case PWR_RESUME: 1069 /* Wake up */ 1070 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1071 if (sc->sc_suspend == PWR_RESUME) { 1072 printf("%s: resume without suspend.\n", 1073 sc->sc_dev.dv_xname); 1074 sc->sc_suspend = why; 1075 break; 1076 } 1077 sc->sc_suspend = why; 1078 auacer_reset_codec(sc); 1079 delay(1000); 1080 sc->codec_if->vtbl->restore_ports(sc->codec_if); 1081 break; 1082 1083 case PWR_SOFTSUSPEND: 1084 case PWR_SOFTSTANDBY: 1085 case PWR_SOFTRESUME: 1086 break; 1087 } 1088 1089 mutex_exit(&sc->sc_lock); 1090 } 1091 1092 static void 1093 auacer_get_locks(void *addr, kmutex_t **intr, kmutex_t **proc) 1094 { 1095 struct auacer_softc *sc; 1096 1097 sc = (struct auacer_softc *)addr; 1098 *intr = &sc->sc_intr_lock; 1099 *proc = &sc->sc_lock; 1100 } 1101
Indexes created Wed Oct 29 01:09:52 GMT 2025