auacer.c revision 1.21.12.3
1 /* $NetBSD: auacer.c,v 1.21.12.3 2008/12/13 13:38:00 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Acer Labs M5455 audio driver 34 * 35 * Acer provides data sheets after signing an NDA, so this is guess work. 36 * The chip behaves somewhat like the Intel i8x0, so this driver 37 * is loosely based on the auich driver. Additional information taken from 38 * the ALSA intel8x0.c driver (which handles M5455 as well). 39 * 40 * As an historical note one can observe that the auich driver borrows 41 * lot from the first NetBSD PCI audio driver, the eap driver. But this 42 * is not attributed anywhere. 43 */ 44 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: auacer.c,v 1.21.12.3 2008/12/13 13:38:00 ad Exp $"); 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/kmem.h> 53 #include <sys/device.h> 54 #include <sys/fcntl.h> 55 #include <sys/proc.h> 56 57 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 58 59 #include <dev/pci/pcidevs.h> 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/auacerreg.h> 62 63 #include <sys/audioio.h> 64 #include <dev/audio_if.h> 65 #include <dev/mulaw.h> 66 #include <dev/auconv.h> 67 68 #include <sys/bus.h> 69 70 #include <dev/ic/ac97reg.h> 71 #include <dev/ic/ac97var.h> 72 73 struct auacer_dma { 74 bus_dmamap_t map; 75 void *addr; 76 bus_dma_segment_t segs[1]; 77 int nsegs; 78 size_t size; 79 struct auacer_dma *next; 80 }; 81 82 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 83 #define KERNADDR(p) ((void *)((p)->addr)) 84 85 struct auacer_cdata { 86 struct auacer_dmalist ic_dmalist_pcmo[ALI_DMALIST_MAX]; 87 }; 88 89 struct auacer_chan { 90 uint32_t ptr; 91 uint32_t start, p, end; 92 uint32_t blksize, fifoe; 93 uint32_t ack; 94 uint32_t port; 95 struct auacer_dmalist *dmalist; 96 void (*intr)(void *); 97 void *arg; 98 }; 99 100 struct auacer_softc { 101 struct device sc_dev; 102 void *sc_ih; 103 kmutex_t sc_lock; 104 kmutex_t sc_intr_lock; 105 106 audio_device_t sc_audev; 107 108 bus_space_tag_t iot; 109 bus_space_handle_t mix_ioh; 110 bus_space_handle_t aud_ioh; 111 bus_dma_tag_t dmat; 112 113 struct ac97_codec_if *codec_if; 114 struct ac97_host_if host_if; 115 116 /* DMA scatter-gather lists. */ 117 bus_dmamap_t sc_cddmamap; 118 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 119 120 struct auacer_cdata *sc_cdata; 121 122 struct auacer_chan sc_pcmo; 123 124 struct auacer_dma *sc_dmas; 125 126 pci_chipset_tag_t sc_pc; 127 pcitag_t sc_pt; 128 129 int sc_dmamap_flags; 130 131 #define AUACER_NFORMATS 3 132 struct audio_format sc_formats[AUACER_NFORMATS]; 133 struct audio_encoding_set *sc_encodings; 134 }; 135 136 #define READ1(sc, a) bus_space_read_1(sc->iot, sc->aud_ioh, a) 137 #define READ2(sc, a) bus_space_read_2(sc->iot, sc->aud_ioh, a) 138 #define READ4(sc, a) bus_space_read_4(sc->iot, sc->aud_ioh, a) 139 #define WRITE1(sc, a, v) bus_space_write_1(sc->iot, sc->aud_ioh, a, v) 140 #define WRITE2(sc, a, v) bus_space_write_2(sc->iot, sc->aud_ioh, a, v) 141 #define WRITE4(sc, a, v) bus_space_write_4(sc->iot, sc->aud_ioh, a, v) 142 143 /* Debug */ 144 #ifdef AUACER_DEBUG 145 #define DPRINTF(l,x) do { if (auacer_debug & (l)) printf x; } while(0) 146 int auacer_debug = 0; 147 #define ALI_DEBUG_CODECIO 0x0001 148 #define ALI_DEBUG_DMA 0x0002 149 #define ALI_DEBUG_INTR 0x0004 150 #define ALI_DEBUG_API 0x0008 151 #define ALI_DEBUG_MIXERAPI 0x0010 152 #else 153 #define DPRINTF(x,y) /* nothing */ 154 #endif 155 156 static int auacer_intr(void *); 157 158 static int auacer_query_encoding(void *, struct audio_encoding *); 159 static int auacer_set_params(void *, int, int, audio_params_t *, 160 audio_params_t *, stream_filter_list_t *, 161 stream_filter_list_t *); 162 static int auacer_round_blocksize(void *, int, int, 163 const audio_params_t *); 164 static int auacer_halt_output(void *); 165 static int auacer_halt_input(void *); 166 static int auacer_getdev(void *, struct audio_device *); 167 static int auacer_set_port(void *, mixer_ctrl_t *); 168 static int auacer_get_port(void *, mixer_ctrl_t *); 169 static int auacer_query_devinfo(void *, mixer_devinfo_t *); 170 static void *auacer_allocm(void *, int, size_t); 171 static void auacer_freem(void *, void *, size_t); 172 static size_t auacer_round_buffersize(void *, int, size_t); 173 static paddr_t auacer_mappage(void *, void *, off_t, int); 174 static int auacer_get_props(void *); 175 static int auacer_trigger_output(void *, void *, void *, int, 176 void (*)(void *), void *, 177 const audio_params_t *); 178 static int auacer_trigger_input(void *, void *, void *, int, 179 void (*)(void *), void *, 180 const audio_params_t *); 181 182 static int auacer_alloc_cdata(struct auacer_softc *); 183 184 static int auacer_allocmem(struct auacer_softc *, size_t, size_t, 185 struct auacer_dma *); 186 static int auacer_freemem(struct auacer_softc *, struct auacer_dma *); 187 static void auacer_get_locks(void *, kmutex_t **, kmutex_t **); 188 189 static bool auacer_resume(device_t PMF_FN_PROTO); 190 static int auacer_set_rate(struct auacer_softc *, int, u_int); 191 192 static void auacer_reset(struct auacer_softc *sc); 193 194 static struct audio_hw_if auacer_hw_if = { 195 NULL, /* open */ 196 NULL, /* close */ 197 NULL, /* drain */ 198 auacer_query_encoding, 199 auacer_set_params, 200 auacer_round_blocksize, 201 NULL, /* commit_setting */ 202 NULL, /* init_output */ 203 NULL, /* init_input */ 204 NULL, /* start_output */ 205 NULL, /* start_input */ 206 auacer_halt_output, 207 auacer_halt_input, 208 NULL, /* speaker_ctl */ 209 auacer_getdev, 210 NULL, /* getfd */ 211 auacer_set_port, 212 auacer_get_port, 213 auacer_query_devinfo, 214 auacer_allocm, 215 auacer_freem, 216 auacer_round_buffersize, 217 auacer_mappage, 218 auacer_get_props, 219 auacer_trigger_output, 220 auacer_trigger_input, 221 NULL, /* dev_ioctl */ 222 NULL, /* powerstate */ 223 auacer_get_locks, 224 }; 225 226 #define AUACER_FORMATS_4CH 1 227 #define AUACER_FORMATS_6CH 2 228 static const struct audio_format auacer_formats[AUACER_NFORMATS] = { 229 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 230 2, AUFMT_STEREO, 0, {8000, 48000}}, 231 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 232 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 233 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 234 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 235 }; 236 237 static int auacer_attach_codec(void *, struct ac97_codec_if *); 238 static int auacer_read_codec(void *, uint8_t, uint16_t *); 239 static int auacer_write_codec(void *, uint8_t, uint16_t); 240 static int auacer_reset_codec(void *); 241 242 static int 243 auacer_match(struct device *parent, struct cfdata *match, 244 void *aux) 245 { 246 struct pci_attach_args *pa; 247 248 pa = (struct pci_attach_args *)aux; 249 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 250 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M5455) 251 return 1; 252 return 0; 253 } 254 255 static void 256 auacer_attach(struct device *parent, struct device *self, void *aux) 257 { 258 struct auacer_softc *sc; 259 struct pci_attach_args *pa; 260 pci_intr_handle_t ih; 261 bus_size_t aud_size; 262 pcireg_t v; 263 const char *intrstr; 264 int i; 265 266 sc = (struct auacer_softc *)self; 267 pa = aux; 268 aprint_normal(": Acer Labs M5455 Audio controller\n"); 269 270 if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, &sc->iot, 271 &sc->aud_ioh, NULL, &aud_size)) { 272 aprint_error(": can't map i/o space\n"); 273 return; 274 } 275 276 sc->sc_pc = pa->pa_pc; 277 sc->sc_pt = pa->pa_tag; 278 sc->dmat = pa->pa_dmat; 279 280 sc->sc_dmamap_flags = BUS_DMA_COHERENT; /* XXX remove */ 281 282 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 283 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SCHED); 284 285 /* enable bus mastering */ 286 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 287 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 288 v | PCI_COMMAND_MASTER_ENABLE); 289 290 /* Map and establish the interrupt. */ 291 if (pci_intr_map(pa, &ih)) { 292 aprint_error_dev(&sc->sc_dev, "can't map interrupt\n"); 293 mutex_destroy(&sc->sc_lock); 294 mutex_destroy(&sc->sc_intr_lock); 295 return; 296 } 297 intrstr = pci_intr_string(pa->pa_pc, ih); 298 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_SCHED, 299 auacer_intr, sc); 300 if (sc->sc_ih == NULL) { 301 aprint_error_dev(&sc->sc_dev, "can't establish interrupt"); 302 if (intrstr != NULL) 303 aprint_normal(" at %s", intrstr); 304 aprint_normal("\n"); 305 mutex_destroy(&sc->sc_lock); 306 mutex_destroy(&sc->sc_intr_lock); 307 return; 308 } 309 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 310 311 strlcpy(sc->sc_audev.name, "M5455 AC97", MAX_AUDIO_DEV_LEN); 312 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 313 "0x%02x", PCI_REVISION(pa->pa_class)); 314 strlcpy(sc->sc_audev.config, device_xname(&sc->sc_dev), MAX_AUDIO_DEV_LEN); 315 316 /* Set up DMA lists. */ 317 auacer_alloc_cdata(sc); 318 sc->sc_pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 319 sc->sc_pcmo.ptr = 0; 320 sc->sc_pcmo.port = ALI_BASE_PO; 321 322 DPRINTF(ALI_DEBUG_DMA, ("auacer_attach: lists %p\n", 323 sc->sc_pcmo.dmalist)); 324 325 sc->host_if.arg = sc; 326 sc->host_if.attach = auacer_attach_codec; 327 sc->host_if.read = auacer_read_codec; 328 sc->host_if.write = auacer_write_codec; 329 sc->host_if.reset = auacer_reset_codec; 330 331 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 332 mutex_destroy(&sc->sc_lock); 333 mutex_destroy(&sc->sc_intr_lock); 334 return; 335 } 336 337 /* setup audio_format */ 338 memcpy(sc->sc_formats, auacer_formats, sizeof(auacer_formats)); 339 mutex_enter(&sc->sc_lock); 340 if (!AC97_IS_4CH(sc->codec_if)) 341 AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_4CH]); 342 if (!AC97_IS_6CH(sc->codec_if)) 343 AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_6CH]); 344 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 345 for (i = 0; i < AUACER_NFORMATS; i++) { 346 sc->sc_formats[i].frequency_type = 1; 347 sc->sc_formats[i].frequency[0] = 48000; 348 } 349 } 350 mutex_exit(&sc->sc_lock); 351 352 if (0 != auconv_create_encodings(sc->sc_formats, AUACER_NFORMATS, 353 &sc->sc_encodings)) { 354 mutex_destroy(&sc->sc_lock); 355 mutex_destroy(&sc->sc_intr_lock); 356 return; 357 } 358 359 mutex_enter(&sc->sc_lock); 360 mutex_spin_enter(&sc->sc_intr_lock); 361 auacer_reset(sc); 362 mutex_spin_exit(&sc->sc_intr_lock); 363 mutex_exit(&sc->sc_lock); 364 365 audio_attach_mi(&auacer_hw_if, sc, &sc->sc_dev); 366 367 if (!pmf_device_register(self, NULL, auacer_resume)) 368 aprint_error_dev(self, "couldn't establish power handler\n"); 369 } 370 371 CFATTACH_DECL(auacer, sizeof(struct auacer_softc), 372 auacer_match, auacer_attach, NULL, NULL); 373 374 static int 375 auacer_ready_codec(struct auacer_softc *sc, int mask) 376 { 377 int count; 378 379 for (count = 0; count < 0x7f; count++) { 380 int val = READ1(sc, ALI_CSPSR); 381 if (val & mask) 382 return 0; 383 } 384 385 aprint_normal("auacer_ready_codec: AC97 codec ready timeout.\n"); 386 return EBUSY; 387 } 388 389 static int 390 auacer_sema_codec(struct auacer_softc *sc) 391 { 392 int ttime; 393 394 ttime = 100; 395 while (ttime-- && (READ4(sc, ALI_CAS) & ALI_CAS_SEM_BUSY)) 396 delay(1); 397 if (!ttime) 398 aprint_normal("auacer_sema_codec: timeout\n"); 399 return auacer_ready_codec(sc, ALI_CSPSR_CODEC_READY); 400 } 401 402 static int 403 auacer_read_codec(void *v, uint8_t reg, uint16_t *val) 404 { 405 struct auacer_softc *sc; 406 407 sc = v; 408 if (auacer_sema_codec(sc)) 409 return EIO; 410 411 reg |= ALI_CPR_ADDR_READ; 412 #if 0 413 if (ac97->num) 414 reg |= ALI_CPR_ADDR_SECONDARY; 415 #endif 416 WRITE2(sc, ALI_CPR_ADDR, reg); 417 if (auacer_ready_codec(sc, ALI_CSPSR_READ_OK)) 418 return EIO; 419 *val = READ2(sc, ALI_SPR); 420 421 DPRINTF(ALI_DEBUG_CODECIO, ("auacer_read_codec: reg=0x%x val=0x%x\n", 422 reg, *val)); 423 424 return 0; 425 } 426 427 int 428 auacer_write_codec(void *v, uint8_t reg, uint16_t val) 429 { 430 struct auacer_softc *sc; 431 432 DPRINTF(ALI_DEBUG_CODECIO, ("auacer_write_codec: reg=0x%x val=0x%x\n", 433 reg, val)); 434 sc = v; 435 if (auacer_sema_codec(sc)) 436 return EIO; 437 WRITE2(sc, ALI_CPR, val); 438 #if 0 439 if (ac97->num) 440 reg |= ALI_CPR_ADDR_SECONDARY; 441 #endif 442 WRITE2(sc, ALI_CPR_ADDR, reg); 443 auacer_ready_codec(sc, ALI_CSPSR_WRITE_OK); 444 return 0; 445 } 446 447 static int 448 auacer_attach_codec(void *v, struct ac97_codec_if *cif) 449 { 450 struct auacer_softc *sc; 451 452 sc = v; 453 sc->codec_if = cif; 454 return 0; 455 } 456 457 static int 458 auacer_reset_codec(void *v) 459 { 460 struct auacer_softc *sc; 461 uint32_t reg; 462 int i; 463 464 sc = v; 465 i = 0; 466 reg = READ4(sc, ALI_SCR); 467 if ((reg & 2) == 0) /* Cold required */ 468 reg |= 2; 469 else 470 reg |= 1; /* Warm */ 471 reg &= ~0x80000000; /* ACLink on */ 472 WRITE4(sc, ALI_SCR, reg); 473 474 while (i < 10) { 475 if ((READ4(sc, ALI_INTERRUPTSR) & ALI_INT_GPIO) == 0) 476 break; 477 delay(50000); /* XXX */ 478 i++; 479 } 480 if (i == 10) { 481 return EIO; 482 } 483 484 for (i = 0; i < 10; i++) { 485 reg = READ4(sc, ALI_RTSR); 486 if (reg & 0x80) /* primary codec */ 487 break; 488 WRITE4(sc, ALI_RTSR, reg | 0x80); 489 delay(50000); /* XXX */ 490 } 491 492 return 0; 493 } 494 495 static void 496 auacer_reset(struct auacer_softc *sc) 497 { 498 WRITE4(sc, ALI_SCR, ALI_SCR_RESET); 499 WRITE4(sc, ALI_FIFOCR1, 0x83838383); 500 WRITE4(sc, ALI_FIFOCR2, 0x83838383); 501 WRITE4(sc, ALI_FIFOCR3, 0x83838383); 502 WRITE4(sc, ALI_INTERFACECR, ALI_IF_PO); /* XXX pcm out only */ 503 WRITE4(sc, ALI_INTERRUPTCR, 0x00000000); 504 WRITE4(sc, ALI_INTERRUPTSR, 0x00000000); 505 } 506 507 static int 508 auacer_query_encoding(void *v, struct audio_encoding *aep) 509 { 510 struct auacer_softc *sc; 511 512 DPRINTF(ALI_DEBUG_API, ("auacer_query_encoding\n")); 513 sc = v; 514 return auconv_query_encoding(sc->sc_encodings, aep); 515 } 516 517 static int 518 auacer_set_rate(struct auacer_softc *sc, int mode, u_int srate) 519 { 520 int ret; 521 u_int ratetmp; 522 523 DPRINTF(ALI_DEBUG_API, ("auacer_set_rate: srate=%u\n", srate)); 524 525 ratetmp = srate; 526 if (mode == AUMODE_RECORD) 527 return sc->codec_if->vtbl->set_rate(sc->codec_if, 528 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 529 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 530 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 531 if (ret) 532 return ret; 533 ratetmp = srate; 534 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 535 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 536 if (ret) 537 return ret; 538 ratetmp = srate; 539 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 540 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 541 return ret; 542 } 543 544 static int 545 auacer_set_params(void *v, int setmode, int usemode, 546 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 547 stream_filter_list_t *rfil) 548 { 549 struct auacer_softc *sc; 550 struct audio_params *p; 551 stream_filter_list_t *fil; 552 uint32_t control; 553 int mode, index; 554 555 DPRINTF(ALI_DEBUG_API, ("auacer_set_params\n")); 556 sc = v; 557 for (mode = AUMODE_RECORD; mode != -1; 558 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 559 if ((setmode & mode) == 0) 560 continue; 561 562 p = mode == AUMODE_PLAY ? play : rec; 563 if (p == NULL) 564 continue; 565 566 if ((p->sample_rate != 8000) && 567 (p->sample_rate != 11025) && 568 (p->sample_rate != 12000) && 569 (p->sample_rate != 16000) && 570 (p->sample_rate != 22050) && 571 (p->sample_rate != 24000) && 572 (p->sample_rate != 32000) && 573 (p->sample_rate != 44100) && 574 (p->sample_rate != 48000)) 575 return (EINVAL); 576 577 fil = mode == AUMODE_PLAY ? pfil : rfil; 578 index = auconv_set_converter(sc->sc_formats, AUACER_NFORMATS, 579 mode, p, TRUE, fil); 580 if (index < 0) 581 return EINVAL; 582 if (fil->req_size > 0) 583 p = &fil->filters[0].param; 584 /* p points HW encoding */ 585 if (sc->sc_formats[index].frequency_type != 1 586 && auacer_set_rate(sc, mode, p->sample_rate)) 587 return EINVAL; 588 if (mode == AUMODE_PLAY) { 589 control = READ4(sc, ALI_SCR); 590 control &= ~ALI_SCR_PCM_246_MASK; 591 if (p->channels == 4) 592 control |= ALI_SCR_PCM_4; 593 else if (p->channels == 6) 594 control |= ALI_SCR_PCM_6; 595 WRITE4(sc, ALI_SCR, control); 596 } 597 } 598 599 return (0); 600 } 601 602 static int 603 auacer_round_blocksize(void *v, int blk, int mode, 604 const audio_params_t *param) 605 { 606 607 return blk & ~0x3f; /* keep good alignment */ 608 } 609 610 static void 611 auacer_halt(struct auacer_softc *sc, struct auacer_chan *chan) 612 { 613 uint32_t val; 614 uint8_t port; 615 uint32_t slot; 616 617 port = chan->port; 618 DPRINTF(ALI_DEBUG_API, ("auacer_halt: port=0x%x\n", port)); 619 chan->intr = 0; 620 621 slot = ALI_PORT2SLOT(port); 622 623 val = READ4(sc, ALI_DMACR); 624 val |= 1 << (slot+16); /* pause */ 625 val &= ~(1 << slot); /* no start */ 626 WRITE4(sc, ALI_DMACR, val); 627 WRITE1(sc, port + ALI_OFF_CR, 0); 628 while (READ1(sc, port + ALI_OFF_CR)) 629 ; 630 /* reset whole DMA things */ 631 WRITE1(sc, port + ALI_OFF_CR, ALI_CR_RR); 632 /* clear interrupts */ 633 WRITE1(sc, port + ALI_OFF_SR, READ1(sc, port+ALI_OFF_SR) | ALI_SR_W1TC); 634 WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(port)); 635 } 636 637 static int 638 auacer_halt_output(void *v) 639 { 640 struct auacer_softc *sc; 641 642 DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_output\n")); 643 sc = v; 644 auacer_halt(sc, &sc->sc_pcmo); 645 646 return 0; 647 } 648 649 static int 650 auacer_halt_input(void *v) 651 { 652 DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_input\n")); 653 654 return 0; 655 } 656 657 static int 658 auacer_getdev(void *v, struct audio_device *adp) 659 { 660 struct auacer_softc *sc; 661 662 DPRINTF(ALI_DEBUG_API, ("auacer_getdev\n")); 663 sc = v; 664 *adp = sc->sc_audev; 665 return 0; 666 } 667 668 static int 669 auacer_set_port(void *v, mixer_ctrl_t *cp) 670 { 671 struct auacer_softc *sc; 672 673 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_set_port\n")); 674 sc = v; 675 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 676 } 677 678 static int 679 auacer_get_port(void *v, mixer_ctrl_t *cp) 680 { 681 struct auacer_softc *sc; 682 683 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_get_port\n")); 684 sc = v; 685 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 686 } 687 688 static int 689 auacer_query_devinfo(void *v, mixer_devinfo_t *dp) 690 { 691 struct auacer_softc *sc; 692 693 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_query_devinfo\n")); 694 sc = v; 695 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 696 } 697 698 static void * 699 auacer_allocm(void *v, int direction, size_t size) 700 { 701 struct auacer_softc *sc; 702 struct auacer_dma *p; 703 int error; 704 705 if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX)) 706 return NULL; 707 708 p = kmem_zalloc(sizeof(*p), KM_SLEEP); 709 if (p == NULL) 710 return NULL; 711 sc = v; 712 error = auacer_allocmem(sc, size, 0, p); 713 if (error) { 714 kmem_free(p, sizeof(*p)); 715 return NULL; 716 } 717 718 p->next = sc->sc_dmas; 719 sc->sc_dmas = p; 720 721 return KERNADDR(p); 722 } 723 724 static void 725 auacer_freem(void *v, void *ptr, size_t size) 726 { 727 struct auacer_softc *sc; 728 struct auacer_dma *p, **pp; 729 730 sc = v; 731 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 732 if (KERNADDR(p) == ptr) { 733 auacer_freemem(sc, p); 734 *pp = p->next; 735 kmem_free(p, sizeof(*p)); 736 return; 737 } 738 } 739 } 740 741 static size_t 742 auacer_round_buffersize(void *v, int direction, size_t size) 743 { 744 745 if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX)) 746 size = ALI_DMALIST_MAX * ALI_DMASEG_MAX; 747 748 return size; 749 } 750 751 static paddr_t 752 auacer_mappage(void *v, void *mem, off_t off, int prot) 753 { 754 struct auacer_softc *sc; 755 struct auacer_dma *p; 756 757 if (off < 0) 758 return -1; 759 sc = v; 760 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 761 continue; 762 if (p == NULL) 763 return -1; 764 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 765 off, prot, BUS_DMA_WAITOK); 766 } 767 768 static int 769 auacer_get_props(void *v) 770 { 771 struct auacer_softc *sc; 772 int props; 773 774 sc = v; 775 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 776 /* 777 * Even if the codec is fixed-rate, set_param() succeeds for any sample 778 * rate because of aurateconv. Applications can't know what rate the 779 * device can process in the case of mmap(). 780 */ 781 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 782 props |= AUDIO_PROP_MMAP; 783 return props; 784 } 785 786 static void 787 auacer_get_locks(void *v, kmutex_t **intr, kmutex_t **proc) 788 { 789 struct auacer_softc *sc; 790 791 sc = v; 792 *intr = &sc->sc_intr_lock; 793 *proc = &sc->sc_lock; 794 } 795 796 static void 797 auacer_add_entry(struct auacer_chan *chan) 798 { 799 struct auacer_dmalist *q; 800 801 q = &chan->dmalist[chan->ptr]; 802 803 DPRINTF(ALI_DEBUG_INTR, 804 ("auacer_add_entry: %p = %x @ 0x%x\n", 805 q, chan->blksize / 2, chan->p)); 806 807 q->base = htole32(chan->p); 808 q->len = htole32((chan->blksize / ALI_SAMPLE_SIZE) | ALI_DMAF_IOC); 809 chan->p += chan->blksize; 810 if (chan->p >= chan->end) 811 chan->p = chan->start; 812 813 if (++chan->ptr >= ALI_DMALIST_MAX) 814 chan->ptr = 0; 815 } 816 817 static void 818 auacer_upd_chan(struct auacer_softc *sc, struct auacer_chan *chan) 819 { 820 uint32_t sts; 821 uint32_t civ; 822 823 sts = READ2(sc, chan->port + ALI_OFF_SR); 824 /* intr ack */ 825 WRITE2(sc, chan->port + ALI_OFF_SR, sts & ALI_SR_W1TC); 826 WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(chan->port)); 827 828 DPRINTF(ALI_DEBUG_INTR, ("auacer_upd_chan: sts=0x%x\n", sts)); 829 830 if (sts & ALI_SR_DMA_INT_FIFO) { 831 printf("%s: fifo underrun # %u\n", 832 device_xname(&sc->sc_dev), ++chan->fifoe); 833 } 834 835 civ = READ1(sc, chan->port + ALI_OFF_CIV); 836 837 DPRINTF(ALI_DEBUG_INTR,("auacer_intr: civ=%u ptr=%u\n",civ,chan->ptr)); 838 839 /* XXX */ 840 while (chan->ptr != civ) { 841 auacer_add_entry(chan); 842 } 843 844 WRITE1(sc, chan->port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK); 845 846 while (chan->ack != civ) { 847 if (chan->intr) { 848 DPRINTF(ALI_DEBUG_INTR,("auacer_upd_chan: callback\n")); 849 chan->intr(chan->arg); 850 } 851 chan->ack++; 852 if (chan->ack >= ALI_DMALIST_MAX) 853 chan->ack = 0; 854 } 855 } 856 857 static int 858 auacer_intr(void *v) 859 { 860 struct auacer_softc *sc; 861 int ret, intrs; 862 863 sc = v; 864 865 DPRINTF(ALI_DEBUG_INTR, ("auacer_intr: intrs=0x%x\n", 866 READ4(sc, ALI_INTERRUPTSR))); 867 868 mutex_spin_enter(&sc->sc_intr_lock); 869 intrs = READ4(sc, ALI_INTERRUPTSR); 870 ret = 0; 871 if (intrs & ALI_INT_PCMOUT) { 872 auacer_upd_chan(sc, &sc->sc_pcmo); 873 ret++; 874 } 875 mutex_spin_exit(&sc->sc_intr_lock); 876 877 return ret != 0; 878 } 879 880 static void 881 auacer_setup_chan(struct auacer_softc *sc, struct auacer_chan *chan, 882 uint32_t start, uint32_t size, uint32_t blksize, 883 void (*intr)(void *), void *arg) 884 { 885 uint32_t port, slot; 886 uint32_t offs, val; 887 888 chan->start = start; 889 chan->ptr = 0; 890 chan->p = chan->start; 891 chan->end = chan->start + size; 892 chan->blksize = blksize; 893 chan->ack = 0; 894 chan->intr = intr; 895 chan->arg = arg; 896 897 auacer_add_entry(chan); 898 auacer_add_entry(chan); 899 900 port = chan->port; 901 slot = ALI_PORT2SLOT(port); 902 903 WRITE1(sc, port + ALI_OFF_CIV, 0); 904 WRITE1(sc, port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK); 905 offs = (char *)chan->dmalist - (char *)sc->sc_cdata; 906 WRITE4(sc, port + ALI_OFF_BDBAR, sc->sc_cddma + offs); 907 WRITE1(sc, port + ALI_OFF_CR, 908 ALI_CR_IOCE | ALI_CR_FEIE | ALI_CR_LVBIE | ALI_CR_RPBM); 909 val = READ4(sc, ALI_DMACR); 910 val &= ~(1 << (slot+16)); /* no pause */ 911 val |= 1 << slot; /* start */ 912 WRITE4(sc, ALI_DMACR, val); 913 } 914 915 static int 916 auacer_trigger_output(void *v, void *start, void *end, int blksize, 917 void (*intr)(void *), void *arg, const audio_params_t *param) 918 { 919 struct auacer_softc *sc; 920 struct auacer_dma *p; 921 uint32_t size; 922 923 DPRINTF(ALI_DEBUG_DMA, 924 ("auacer_trigger_output(%p, %p, %d, %p, %p, %p)\n", 925 start, end, blksize, intr, arg, param)); 926 sc = v; 927 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 928 continue; 929 if (!p) { 930 printf("auacer_trigger_output: bad addr %p\n", start); 931 return (EINVAL); 932 } 933 934 size = (char *)end - (char *)start; 935 auacer_setup_chan(sc, &sc->sc_pcmo, DMAADDR(p), size, blksize, 936 intr, arg); 937 938 return 0; 939 } 940 941 static int 942 auacer_trigger_input(void *v, void *start, void *end, 943 int blksize, void (*intr)(void *), void *arg, 944 const audio_params_t *param) 945 { 946 return EINVAL; 947 } 948 949 static int 950 auacer_allocmem(struct auacer_softc *sc, size_t size, size_t align, 951 struct auacer_dma *p) 952 { 953 int error; 954 955 p->size = size; 956 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 957 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 958 &p->nsegs, BUS_DMA_WAITOK); 959 if (error) 960 return error; 961 962 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 963 &p->addr, BUS_DMA_WAITOK|sc->sc_dmamap_flags); 964 if (error) 965 goto free; 966 967 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 968 0, BUS_DMA_WAITOK, &p->map); 969 if (error) 970 goto unmap; 971 972 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 973 BUS_DMA_WAITOK); 974 if (error) 975 goto destroy; 976 return (0); 977 978 destroy: 979 bus_dmamap_destroy(sc->dmat, p->map); 980 unmap: 981 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 982 free: 983 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 984 return error; 985 } 986 987 static int 988 auacer_freemem(struct auacer_softc *sc, struct auacer_dma *p) 989 { 990 991 bus_dmamap_unload(sc->dmat, p->map); 992 bus_dmamap_destroy(sc->dmat, p->map); 993 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 994 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 995 return 0; 996 } 997 998 static int 999 auacer_alloc_cdata(struct auacer_softc *sc) 1000 { 1001 bus_dma_segment_t seg; 1002 int error, rseg; 1003 1004 /* 1005 * Allocate the control data structure, and create and load the 1006 * DMA map for it. 1007 */ 1008 if ((error = bus_dmamem_alloc(sc->dmat, 1009 sizeof(struct auacer_cdata), 1010 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1011 aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n", 1012 error); 1013 goto fail_0; 1014 } 1015 1016 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1017 sizeof(struct auacer_cdata), 1018 (void **) &sc->sc_cdata, 1019 sc->sc_dmamap_flags)) != 0) { 1020 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 1021 error); 1022 goto fail_1; 1023 } 1024 1025 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auacer_cdata), 1, 1026 sizeof(struct auacer_cdata), 0, 0, 1027 &sc->sc_cddmamap)) != 0) { 1028 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 1029 "error = %d\n", error); 1030 goto fail_2; 1031 } 1032 1033 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1034 sc->sc_cdata, sizeof(struct auacer_cdata), 1035 NULL, 0)) != 0) { 1036 aprint_error_dev(&sc->sc_dev, "unable to load control data DMA map, " 1037 "error = %d\n", error); 1038 goto fail_3; 1039 } 1040 1041 return 0; 1042 1043 fail_3: 1044 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1045 fail_2: 1046 bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata, 1047 sizeof(struct auacer_cdata)); 1048 fail_1: 1049 bus_dmamem_free(sc->dmat, &seg, rseg); 1050 fail_0: 1051 return error; 1052 } 1053 1054 static bool 1055 auacer_resume(device_t dv PMF_FN_ARGS) 1056 { 1057 struct auacer_softc *sc = device_private(dv); 1058 1059 mutex_enter(&sc->sc_lock); 1060 mutex_spin_enter(&sc->sc_intr_lock); 1061 auacer_reset_codec(sc); 1062 mutex_spin_exit(&sc->sc_intr_lock); 1063 delay(1000); 1064 sc->codec_if->vtbl->restore_ports(sc->codec_if); 1065 mutex_exit(&sc->sc_lock); 1066 1067 return true; 1068 } 1069
Indexes created Wed Oct 29 06:09:47 GMT 2025