auacer.c revision 1.36.2.1
1 /* $NetBSD: auacer.c,v 1.36.2.1 2019/04/21 05:11:22 isaki Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Acer Labs M5455 audio driver 34 * 35 * Acer provides data sheets after signing an NDA, so this is guess work. 36 * The chip behaves somewhat like the Intel i8x0, so this driver 37 * is loosely based on the auich driver. Additional information taken from 38 * the ALSA intel8x0.c driver (which handles M5455 as well). 39 * 40 * As an historical note one can observe that the auich driver borrows 41 * lot from the first NetBSD PCI audio driver, the eap driver. But this 42 * is not attributed anywhere. 43 */ 44 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: auacer.c,v 1.36.2.1 2019/04/21 05:11:22 isaki Exp $"); 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/kmem.h> 53 #include <sys/device.h> 54 #include <sys/fcntl.h> 55 #include <sys/proc.h> 56 57 #include <dev/pci/pcidevs.h> 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/auacerreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/mulaw.h> 64 #include <dev/auconv.h> 65 66 #include <sys/bus.h> 67 68 #include <dev/ic/ac97reg.h> 69 #include <dev/ic/ac97var.h> 70 71 struct auacer_dma { 72 bus_dmamap_t map; 73 void *addr; 74 bus_dma_segment_t segs[1]; 75 int nsegs; 76 size_t size; 77 struct auacer_dma *next; 78 }; 79 80 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 81 #define KERNADDR(p) ((void *)((p)->addr)) 82 83 struct auacer_cdata { 84 struct auacer_dmalist ic_dmalist_pcmo[ALI_DMALIST_MAX]; 85 }; 86 87 struct auacer_chan { 88 uint32_t ptr; 89 uint32_t start, p, end; 90 uint32_t blksize, fifoe; 91 uint32_t ack; 92 uint32_t port; 93 struct auacer_dmalist *dmalist; 94 void (*intr)(void *); 95 void *arg; 96 }; 97 98 struct auacer_softc { 99 device_t sc_dev; 100 void *sc_ih; 101 kmutex_t sc_lock; 102 kmutex_t sc_intr_lock; 103 104 audio_device_t sc_audev; 105 106 bus_space_tag_t iot; 107 bus_space_handle_t mix_ioh; 108 bus_space_handle_t aud_ioh; 109 bus_dma_tag_t dmat; 110 111 struct ac97_codec_if *codec_if; 112 struct ac97_host_if host_if; 113 114 /* DMA scatter-gather lists. */ 115 bus_dmamap_t sc_cddmamap; 116 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 117 118 struct auacer_cdata *sc_cdata; 119 120 struct auacer_chan sc_pcmo; 121 122 struct auacer_dma *sc_dmas; 123 124 pci_chipset_tag_t sc_pc; 125 pcitag_t sc_pt; 126 127 int sc_dmamap_flags; 128 129 #define AUACER_NFORMATS 3 130 struct audio_format sc_formats[AUACER_NFORMATS]; 131 struct audio_encoding_set *sc_encodings; 132 }; 133 134 #define READ1(sc, a) bus_space_read_1(sc->iot, sc->aud_ioh, a) 135 #define READ2(sc, a) bus_space_read_2(sc->iot, sc->aud_ioh, a) 136 #define READ4(sc, a) bus_space_read_4(sc->iot, sc->aud_ioh, a) 137 #define WRITE1(sc, a, v) bus_space_write_1(sc->iot, sc->aud_ioh, a, v) 138 #define WRITE2(sc, a, v) bus_space_write_2(sc->iot, sc->aud_ioh, a, v) 139 #define WRITE4(sc, a, v) bus_space_write_4(sc->iot, sc->aud_ioh, a, v) 140 141 /* Debug */ 142 #ifdef AUACER_DEBUG 143 #define DPRINTF(l,x) do { if (auacer_debug & (l)) printf x; } while(0) 144 int auacer_debug = 0; 145 #define ALI_DEBUG_CODECIO 0x0001 146 #define ALI_DEBUG_DMA 0x0002 147 #define ALI_DEBUG_INTR 0x0004 148 #define ALI_DEBUG_API 0x0008 149 #define ALI_DEBUG_MIXERAPI 0x0010 150 #else 151 #define DPRINTF(x,y) /* nothing */ 152 #endif 153 154 static int auacer_intr(void *); 155 156 static int auacer_query_encoding(void *, struct audio_encoding *); 157 static int auacer_set_params(void *, int, int, audio_params_t *, 158 audio_params_t *, stream_filter_list_t *, 159 stream_filter_list_t *); 160 static int auacer_round_blocksize(void *, int, int, 161 const audio_params_t *); 162 static int auacer_halt_output(void *); 163 static int auacer_halt_input(void *); 164 static int auacer_getdev(void *, struct audio_device *); 165 static int auacer_set_port(void *, mixer_ctrl_t *); 166 static int auacer_get_port(void *, mixer_ctrl_t *); 167 static int auacer_query_devinfo(void *, mixer_devinfo_t *); 168 static void *auacer_allocm(void *, int, size_t); 169 static void auacer_freem(void *, void *, size_t); 170 static size_t auacer_round_buffersize(void *, int, size_t); 171 static paddr_t auacer_mappage(void *, void *, off_t, int); 172 static int auacer_get_props(void *); 173 static int auacer_trigger_output(void *, void *, void *, int, 174 void (*)(void *), void *, 175 const audio_params_t *); 176 static int auacer_trigger_input(void *, void *, void *, int, 177 void (*)(void *), void *, 178 const audio_params_t *); 179 180 static int auacer_alloc_cdata(struct auacer_softc *); 181 182 static int auacer_allocmem(struct auacer_softc *, size_t, size_t, 183 struct auacer_dma *); 184 static int auacer_freemem(struct auacer_softc *, struct auacer_dma *); 185 static void auacer_get_locks(void *, kmutex_t **, kmutex_t **); 186 187 static bool auacer_resume(device_t, const pmf_qual_t *); 188 static int auacer_set_rate(struct auacer_softc *, int, u_int); 189 190 static void auacer_reset(struct auacer_softc *sc); 191 192 static const struct audio_hw_if auacer_hw_if = { 193 .query_encoding = auacer_query_encoding, 194 .set_params = auacer_set_params, 195 .round_blocksize = auacer_round_blocksize, 196 .halt_output = auacer_halt_output, 197 .halt_input = auacer_halt_input, 198 .getdev = auacer_getdev, 199 .set_port = auacer_set_port, 200 .get_port = auacer_get_port, 201 .query_devinfo = auacer_query_devinfo, 202 .allocm = auacer_allocm, 203 .freem = auacer_freem, 204 .round_buffersize = auacer_round_buffersize, 205 .mappage = auacer_mappage, 206 .get_props = auacer_get_props, 207 .trigger_output = auacer_trigger_output, 208 .trigger_input = auacer_trigger_input, 209 .get_locks = auacer_get_locks, 210 }; 211 212 #define AUACER_FORMATS_4CH 1 213 #define AUACER_FORMATS_6CH 2 214 #define AUACER_FORMAT(aumode, ch, chmask) \ 215 { \ 216 .mode = (aumode), \ 217 .encoding = AUDIO_ENCODING_SLINEAR_LE, \ 218 .validbits = 16, \ 219 .precision = 16, \ 220 .channels = (ch), \ 221 .channel_mask = (chmask), \ 222 .frequency_type = 0, \ 223 .frequency = { 8000, 48000 }, \ 224 } 225 static const struct audio_format auacer_formats[AUACER_NFORMATS] = { 226 AUACER_FORMAT(AUMODE_PLAY | AUMODE_RECORD, 2, AUFMT_STEREO), 227 AUACER_FORMAT(AUMODE_PLAY , 4, AUFMT_SURROUND4), 228 AUACER_FORMAT(AUMODE_PLAY , 6, AUFMT_DOLBY_5_1), 229 }; 230 231 static int auacer_attach_codec(void *, struct ac97_codec_if *); 232 static int auacer_read_codec(void *, uint8_t, uint16_t *); 233 static int auacer_write_codec(void *, uint8_t, uint16_t); 234 static int auacer_reset_codec(void *); 235 236 static int 237 auacer_match(device_t parent, cfdata_t match, void *aux) 238 { 239 struct pci_attach_args *pa; 240 241 pa = (struct pci_attach_args *)aux; 242 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 243 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M5455) 244 return 1; 245 return 0; 246 } 247 248 static void 249 auacer_attach(device_t parent, device_t self, void *aux) 250 { 251 struct auacer_softc *sc; 252 struct pci_attach_args *pa; 253 pci_intr_handle_t ih; 254 bus_size_t aud_size; 255 pcireg_t v; 256 const char *intrstr; 257 int i; 258 char intrbuf[PCI_INTRSTR_LEN]; 259 260 sc = device_private(self); 261 sc->sc_dev = self; 262 pa = aux; 263 aprint_normal(": Acer Labs M5455 Audio controller\n"); 264 265 if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, &sc->iot, 266 &sc->aud_ioh, NULL, &aud_size)) { 267 aprint_error(": can't map i/o space\n"); 268 return; 269 } 270 271 sc->sc_pc = pa->pa_pc; 272 sc->sc_pt = pa->pa_tag; 273 sc->dmat = pa->pa_dmat; 274 275 sc->sc_dmamap_flags = BUS_DMA_COHERENT; /* XXX remove */ 276 277 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 278 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 279 280 /* enable bus mastering */ 281 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 282 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 283 v | PCI_COMMAND_MASTER_ENABLE); 284 285 /* Map and establish the interrupt. */ 286 if (pci_intr_map(pa, &ih)) { 287 aprint_error_dev(sc->sc_dev, "can't map interrupt\n"); 288 mutex_destroy(&sc->sc_lock); 289 mutex_destroy(&sc->sc_intr_lock); 290 return; 291 } 292 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 293 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_AUDIO, 294 auacer_intr, sc, device_xname(self)); 295 if (sc->sc_ih == NULL) { 296 aprint_error_dev(sc->sc_dev, "can't establish interrupt"); 297 if (intrstr != NULL) 298 aprint_error(" at %s", intrstr); 299 aprint_error("\n"); 300 mutex_destroy(&sc->sc_lock); 301 mutex_destroy(&sc->sc_intr_lock); 302 return; 303 } 304 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 305 306 strlcpy(sc->sc_audev.name, "M5455 AC97", MAX_AUDIO_DEV_LEN); 307 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 308 "0x%02x", PCI_REVISION(pa->pa_class)); 309 strlcpy(sc->sc_audev.config, device_xname(sc->sc_dev), MAX_AUDIO_DEV_LEN); 310 311 /* Set up DMA lists. */ 312 auacer_alloc_cdata(sc); 313 sc->sc_pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 314 sc->sc_pcmo.ptr = 0; 315 sc->sc_pcmo.port = ALI_BASE_PO; 316 317 DPRINTF(ALI_DEBUG_DMA, ("auacer_attach: lists %p\n", 318 sc->sc_pcmo.dmalist)); 319 320 sc->host_if.arg = sc; 321 sc->host_if.attach = auacer_attach_codec; 322 sc->host_if.read = auacer_read_codec; 323 sc->host_if.write = auacer_write_codec; 324 sc->host_if.reset = auacer_reset_codec; 325 326 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 327 mutex_destroy(&sc->sc_lock); 328 mutex_destroy(&sc->sc_intr_lock); 329 return; 330 } 331 332 /* setup audio_format */ 333 memcpy(sc->sc_formats, auacer_formats, sizeof(auacer_formats)); 334 mutex_enter(&sc->sc_lock); 335 if (!AC97_IS_4CH(sc->codec_if)) 336 AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_4CH]); 337 if (!AC97_IS_6CH(sc->codec_if)) 338 AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_6CH]); 339 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 340 for (i = 0; i < AUACER_NFORMATS; i++) { 341 sc->sc_formats[i].frequency_type = 1; 342 sc->sc_formats[i].frequency[0] = 48000; 343 } 344 } 345 mutex_exit(&sc->sc_lock); 346 347 if (0 != auconv_create_encodings(sc->sc_formats, AUACER_NFORMATS, 348 &sc->sc_encodings)) { 349 mutex_destroy(&sc->sc_lock); 350 mutex_destroy(&sc->sc_intr_lock); 351 return; 352 } 353 354 mutex_enter(&sc->sc_lock); 355 mutex_spin_enter(&sc->sc_intr_lock); 356 auacer_reset(sc); 357 mutex_spin_exit(&sc->sc_intr_lock); 358 mutex_exit(&sc->sc_lock); 359 360 audio_attach_mi(&auacer_hw_if, sc, sc->sc_dev); 361 362 if (!pmf_device_register(self, NULL, auacer_resume)) 363 aprint_error_dev(self, "couldn't establish power handler\n"); 364 } 365 366 CFATTACH_DECL_NEW(auacer, sizeof(struct auacer_softc), 367 auacer_match, auacer_attach, NULL, NULL); 368 369 static int 370 auacer_ready_codec(struct auacer_softc *sc, int mask) 371 { 372 int count; 373 374 for (count = 0; count < 0x7f; count++) { 375 int val = READ1(sc, ALI_CSPSR); 376 if (val & mask) 377 return 0; 378 } 379 380 aprint_normal("auacer_ready_codec: AC97 codec ready timeout.\n"); 381 return EBUSY; 382 } 383 384 static int 385 auacer_sema_codec(struct auacer_softc *sc) 386 { 387 int ttime; 388 389 ttime = 100; 390 while (ttime-- && (READ4(sc, ALI_CAS) & ALI_CAS_SEM_BUSY)) 391 delay(1); 392 if (!ttime) 393 aprint_normal("auacer_sema_codec: timeout\n"); 394 return auacer_ready_codec(sc, ALI_CSPSR_CODEC_READY); 395 } 396 397 static int 398 auacer_read_codec(void *v, uint8_t reg, uint16_t *val) 399 { 400 struct auacer_softc *sc; 401 402 sc = v; 403 if (auacer_sema_codec(sc)) 404 return EIO; 405 406 reg |= ALI_CPR_ADDR_READ; 407 #if 0 408 if (ac97->num) 409 reg |= ALI_CPR_ADDR_SECONDARY; 410 #endif 411 WRITE2(sc, ALI_CPR_ADDR, reg); 412 if (auacer_ready_codec(sc, ALI_CSPSR_READ_OK)) 413 return EIO; 414 *val = READ2(sc, ALI_SPR); 415 416 DPRINTF(ALI_DEBUG_CODECIO, ("auacer_read_codec: reg=0x%x val=0x%x\n", 417 reg, *val)); 418 419 return 0; 420 } 421 422 int 423 auacer_write_codec(void *v, uint8_t reg, uint16_t val) 424 { 425 struct auacer_softc *sc; 426 427 DPRINTF(ALI_DEBUG_CODECIO, ("auacer_write_codec: reg=0x%x val=0x%x\n", 428 reg, val)); 429 sc = v; 430 if (auacer_sema_codec(sc)) 431 return EIO; 432 WRITE2(sc, ALI_CPR, val); 433 #if 0 434 if (ac97->num) 435 reg |= ALI_CPR_ADDR_SECONDARY; 436 #endif 437 WRITE2(sc, ALI_CPR_ADDR, reg); 438 auacer_ready_codec(sc, ALI_CSPSR_WRITE_OK); 439 return 0; 440 } 441 442 static int 443 auacer_attach_codec(void *v, struct ac97_codec_if *cif) 444 { 445 struct auacer_softc *sc; 446 447 sc = v; 448 sc->codec_if = cif; 449 return 0; 450 } 451 452 static int 453 auacer_reset_codec(void *v) 454 { 455 struct auacer_softc *sc; 456 uint32_t reg; 457 int i; 458 459 sc = v; 460 i = 0; 461 reg = READ4(sc, ALI_SCR); 462 if ((reg & 2) == 0) /* Cold required */ 463 reg |= 2; 464 else 465 reg |= 1; /* Warm */ 466 reg &= ~0x80000000; /* ACLink on */ 467 WRITE4(sc, ALI_SCR, reg); 468 469 while (i < 10) { 470 if ((READ4(sc, ALI_INTERRUPTSR) & ALI_INT_GPIO) == 0) 471 break; 472 delay(50000); /* XXX */ 473 i++; 474 } 475 if (i == 10) { 476 return EIO; 477 } 478 479 for (i = 0; i < 10; i++) { 480 reg = READ4(sc, ALI_RTSR); 481 if (reg & 0x80) /* primary codec */ 482 break; 483 WRITE4(sc, ALI_RTSR, reg | 0x80); 484 delay(50000); /* XXX */ 485 } 486 487 return 0; 488 } 489 490 static void 491 auacer_reset(struct auacer_softc *sc) 492 { 493 WRITE4(sc, ALI_SCR, ALI_SCR_RESET); 494 WRITE4(sc, ALI_FIFOCR1, 0x83838383); 495 WRITE4(sc, ALI_FIFOCR2, 0x83838383); 496 WRITE4(sc, ALI_FIFOCR3, 0x83838383); 497 WRITE4(sc, ALI_INTERFACECR, ALI_IF_PO); /* XXX pcm out only */ 498 WRITE4(sc, ALI_INTERRUPTCR, 0x00000000); 499 WRITE4(sc, ALI_INTERRUPTSR, 0x00000000); 500 } 501 502 static int 503 auacer_query_encoding(void *v, struct audio_encoding *aep) 504 { 505 struct auacer_softc *sc; 506 507 DPRINTF(ALI_DEBUG_API, ("auacer_query_encoding\n")); 508 sc = v; 509 return auconv_query_encoding(sc->sc_encodings, aep); 510 } 511 512 static int 513 auacer_set_rate(struct auacer_softc *sc, int mode, u_int srate) 514 { 515 int ret; 516 u_int ratetmp; 517 518 DPRINTF(ALI_DEBUG_API, ("auacer_set_rate: srate=%u\n", srate)); 519 520 ratetmp = srate; 521 if (mode == AUMODE_RECORD) 522 return sc->codec_if->vtbl->set_rate(sc->codec_if, 523 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 524 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 525 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 526 if (ret) 527 return ret; 528 ratetmp = srate; 529 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 530 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 531 if (ret) 532 return ret; 533 ratetmp = srate; 534 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 535 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 536 return ret; 537 } 538 539 static int 540 auacer_set_params(void *v, int setmode, int usemode, 541 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 542 stream_filter_list_t *rfil) 543 { 544 struct auacer_softc *sc; 545 struct audio_params *p; 546 stream_filter_list_t *fil; 547 uint32_t control; 548 int mode, index; 549 550 DPRINTF(ALI_DEBUG_API, ("auacer_set_params\n")); 551 sc = v; 552 for (mode = AUMODE_RECORD; mode != -1; 553 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 554 if ((setmode & mode) == 0) 555 continue; 556 557 p = mode == AUMODE_PLAY ? play : rec; 558 if (p == NULL) 559 continue; 560 561 if ((p->sample_rate != 8000) && 562 (p->sample_rate != 11025) && 563 (p->sample_rate != 12000) && 564 (p->sample_rate != 16000) && 565 (p->sample_rate != 22050) && 566 (p->sample_rate != 24000) && 567 (p->sample_rate != 32000) && 568 (p->sample_rate != 44100) && 569 (p->sample_rate != 48000)) 570 return (EINVAL); 571 572 fil = mode == AUMODE_PLAY ? pfil : rfil; 573 index = auconv_set_converter(sc->sc_formats, AUACER_NFORMATS, 574 mode, p, TRUE, fil); 575 if (index < 0) 576 return EINVAL; 577 if (fil->req_size > 0) 578 p = &fil->filters[0].param; 579 /* p points HW encoding */ 580 if (sc->sc_formats[index].frequency_type != 1 581 && auacer_set_rate(sc, mode, p->sample_rate)) 582 return EINVAL; 583 if (mode == AUMODE_PLAY) { 584 control = READ4(sc, ALI_SCR); 585 control &= ~ALI_SCR_PCM_246_MASK; 586 if (p->channels == 4) 587 control |= ALI_SCR_PCM_4; 588 else if (p->channels == 6) 589 control |= ALI_SCR_PCM_6; 590 WRITE4(sc, ALI_SCR, control); 591 } 592 } 593 594 return (0); 595 } 596 597 static int 598 auacer_round_blocksize(void *v, int blk, int mode, 599 const audio_params_t *param) 600 { 601 602 return blk & ~0x3f; /* keep good alignment */ 603 } 604 605 static void 606 auacer_halt(struct auacer_softc *sc, struct auacer_chan *chan) 607 { 608 uint32_t val; 609 uint8_t port; 610 uint32_t slot; 611 612 port = chan->port; 613 DPRINTF(ALI_DEBUG_API, ("auacer_halt: port=0x%x\n", port)); 614 chan->intr = 0; 615 616 slot = ALI_PORT2SLOT(port); 617 618 val = READ4(sc, ALI_DMACR); 619 val |= 1 << (slot+16); /* pause */ 620 val &= ~(1 << slot); /* no start */ 621 WRITE4(sc, ALI_DMACR, val); 622 WRITE1(sc, port + ALI_OFF_CR, 0); 623 while (READ1(sc, port + ALI_OFF_CR)) 624 ; 625 /* reset whole DMA things */ 626 WRITE1(sc, port + ALI_OFF_CR, ALI_CR_RR); 627 /* clear interrupts */ 628 WRITE1(sc, port + ALI_OFF_SR, READ1(sc, port+ALI_OFF_SR) | ALI_SR_W1TC); 629 WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(port)); 630 } 631 632 static int 633 auacer_halt_output(void *v) 634 { 635 struct auacer_softc *sc; 636 637 DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_output\n")); 638 sc = v; 639 auacer_halt(sc, &sc->sc_pcmo); 640 641 return 0; 642 } 643 644 static int 645 auacer_halt_input(void *v) 646 { 647 DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_input\n")); 648 649 return 0; 650 } 651 652 static int 653 auacer_getdev(void *v, struct audio_device *adp) 654 { 655 struct auacer_softc *sc; 656 657 DPRINTF(ALI_DEBUG_API, ("auacer_getdev\n")); 658 sc = v; 659 *adp = sc->sc_audev; 660 return 0; 661 } 662 663 static int 664 auacer_set_port(void *v, mixer_ctrl_t *cp) 665 { 666 struct auacer_softc *sc; 667 668 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_set_port\n")); 669 sc = v; 670 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 671 } 672 673 static int 674 auacer_get_port(void *v, mixer_ctrl_t *cp) 675 { 676 struct auacer_softc *sc; 677 678 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_get_port\n")); 679 sc = v; 680 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 681 } 682 683 static int 684 auacer_query_devinfo(void *v, mixer_devinfo_t *dp) 685 { 686 struct auacer_softc *sc; 687 688 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_query_devinfo\n")); 689 sc = v; 690 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 691 } 692 693 static void * 694 auacer_allocm(void *v, int direction, size_t size) 695 { 696 struct auacer_softc *sc; 697 struct auacer_dma *p; 698 int error; 699 700 if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX)) 701 return NULL; 702 703 p = kmem_zalloc(sizeof(*p), KM_SLEEP); 704 sc = v; 705 error = auacer_allocmem(sc, size, 0, p); 706 if (error) { 707 kmem_free(p, sizeof(*p)); 708 return NULL; 709 } 710 711 p->next = sc->sc_dmas; 712 sc->sc_dmas = p; 713 714 return KERNADDR(p); 715 } 716 717 static void 718 auacer_freem(void *v, void *ptr, size_t size) 719 { 720 struct auacer_softc *sc; 721 struct auacer_dma *p, **pp; 722 723 sc = v; 724 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 725 if (KERNADDR(p) == ptr) { 726 auacer_freemem(sc, p); 727 *pp = p->next; 728 kmem_free(p, sizeof(*p)); 729 return; 730 } 731 } 732 } 733 734 static size_t 735 auacer_round_buffersize(void *v, int direction, size_t size) 736 { 737 738 if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX)) 739 size = ALI_DMALIST_MAX * ALI_DMASEG_MAX; 740 741 return size; 742 } 743 744 static paddr_t 745 auacer_mappage(void *v, void *mem, off_t off, int prot) 746 { 747 struct auacer_softc *sc; 748 struct auacer_dma *p; 749 750 if (off < 0) 751 return -1; 752 sc = v; 753 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 754 continue; 755 if (p == NULL) 756 return -1; 757 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 758 off, prot, BUS_DMA_WAITOK); 759 } 760 761 static int 762 auacer_get_props(void *v) 763 { 764 struct auacer_softc *sc; 765 int props; 766 767 sc = v; 768 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 769 /* 770 * Even if the codec is fixed-rate, set_param() succeeds for any sample 771 * rate because of aurateconv. Applications can't know what rate the 772 * device can process in the case of mmap(). 773 */ 774 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 775 props |= AUDIO_PROP_MMAP; 776 return props; 777 } 778 779 static void 780 auacer_get_locks(void *v, kmutex_t **intr, kmutex_t **proc) 781 { 782 struct auacer_softc *sc; 783 784 sc = v; 785 *intr = &sc->sc_intr_lock; 786 *proc = &sc->sc_lock; 787 } 788 789 static void 790 auacer_add_entry(struct auacer_chan *chan) 791 { 792 struct auacer_dmalist *q; 793 794 q = &chan->dmalist[chan->ptr]; 795 796 DPRINTF(ALI_DEBUG_INTR, 797 ("auacer_add_entry: %p = %x @ 0x%x\n", 798 q, chan->blksize / 2, chan->p)); 799 800 q->base = htole32(chan->p); 801 q->len = htole32((chan->blksize / ALI_SAMPLE_SIZE) | ALI_DMAF_IOC); 802 chan->p += chan->blksize; 803 if (chan->p >= chan->end) 804 chan->p = chan->start; 805 806 if (++chan->ptr >= ALI_DMALIST_MAX) 807 chan->ptr = 0; 808 } 809 810 static void 811 auacer_upd_chan(struct auacer_softc *sc, struct auacer_chan *chan) 812 { 813 uint32_t sts; 814 uint32_t civ; 815 816 sts = READ2(sc, chan->port + ALI_OFF_SR); 817 /* intr ack */ 818 WRITE2(sc, chan->port + ALI_OFF_SR, sts & ALI_SR_W1TC); 819 WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(chan->port)); 820 821 DPRINTF(ALI_DEBUG_INTR, ("auacer_upd_chan: sts=0x%x\n", sts)); 822 823 if (sts & ALI_SR_DMA_INT_FIFO) { 824 printf("%s: fifo underrun # %u\n", 825 device_xname(sc->sc_dev), ++chan->fifoe); 826 } 827 828 civ = READ1(sc, chan->port + ALI_OFF_CIV); 829 830 DPRINTF(ALI_DEBUG_INTR,("auacer_intr: civ=%u ptr=%u\n",civ,chan->ptr)); 831 832 /* XXX */ 833 while (chan->ptr != civ) { 834 auacer_add_entry(chan); 835 } 836 837 WRITE1(sc, chan->port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK); 838 839 while (chan->ack != civ) { 840 if (chan->intr) { 841 DPRINTF(ALI_DEBUG_INTR,("auacer_upd_chan: callback\n")); 842 chan->intr(chan->arg); 843 } 844 chan->ack++; 845 if (chan->ack >= ALI_DMALIST_MAX) 846 chan->ack = 0; 847 } 848 } 849 850 static int 851 auacer_intr(void *v) 852 { 853 struct auacer_softc *sc; 854 int ret, intrs; 855 856 sc = v; 857 858 DPRINTF(ALI_DEBUG_INTR, ("auacer_intr: intrs=0x%x\n", 859 READ4(sc, ALI_INTERRUPTSR))); 860 861 mutex_spin_enter(&sc->sc_intr_lock); 862 intrs = READ4(sc, ALI_INTERRUPTSR); 863 ret = 0; 864 if (intrs & ALI_INT_PCMOUT) { 865 auacer_upd_chan(sc, &sc->sc_pcmo); 866 ret++; 867 } 868 mutex_spin_exit(&sc->sc_intr_lock); 869 870 return ret != 0; 871 } 872 873 static void 874 auacer_setup_chan(struct auacer_softc *sc, struct auacer_chan *chan, 875 uint32_t start, uint32_t size, uint32_t blksize, 876 void (*intr)(void *), void *arg) 877 { 878 uint32_t port, slot; 879 uint32_t offs, val; 880 881 chan->start = start; 882 chan->ptr = 0; 883 chan->p = chan->start; 884 chan->end = chan->start + size; 885 chan->blksize = blksize; 886 chan->ack = 0; 887 chan->intr = intr; 888 chan->arg = arg; 889 890 auacer_add_entry(chan); 891 auacer_add_entry(chan); 892 893 port = chan->port; 894 slot = ALI_PORT2SLOT(port); 895 896 WRITE1(sc, port + ALI_OFF_CIV, 0); 897 WRITE1(sc, port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK); 898 offs = (char *)chan->dmalist - (char *)sc->sc_cdata; 899 WRITE4(sc, port + ALI_OFF_BDBAR, sc->sc_cddma + offs); 900 WRITE1(sc, port + ALI_OFF_CR, 901 ALI_CR_IOCE | ALI_CR_FEIE | ALI_CR_LVBIE | ALI_CR_RPBM); 902 val = READ4(sc, ALI_DMACR); 903 val &= ~(1 << (slot+16)); /* no pause */ 904 val |= 1 << slot; /* start */ 905 WRITE4(sc, ALI_DMACR, val); 906 } 907 908 static int 909 auacer_trigger_output(void *v, void *start, void *end, int blksize, 910 void (*intr)(void *), void *arg, const audio_params_t *param) 911 { 912 struct auacer_softc *sc; 913 struct auacer_dma *p; 914 uint32_t size; 915 916 DPRINTF(ALI_DEBUG_DMA, 917 ("auacer_trigger_output(%p, %p, %d, %p, %p, %p)\n", 918 start, end, blksize, intr, arg, param)); 919 sc = v; 920 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 921 continue; 922 if (!p) { 923 printf("auacer_trigger_output: bad addr %p\n", start); 924 return (EINVAL); 925 } 926 927 size = (char *)end - (char *)start; 928 auacer_setup_chan(sc, &sc->sc_pcmo, DMAADDR(p), size, blksize, 929 intr, arg); 930 931 return 0; 932 } 933 934 static int 935 auacer_trigger_input(void *v, void *start, void *end, 936 int blksize, void (*intr)(void *), void *arg, 937 const audio_params_t *param) 938 { 939 return EINVAL; 940 } 941 942 static int 943 auacer_allocmem(struct auacer_softc *sc, size_t size, size_t align, 944 struct auacer_dma *p) 945 { 946 int error; 947 948 p->size = size; 949 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 950 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 951 &p->nsegs, BUS_DMA_WAITOK); 952 if (error) 953 return error; 954 955 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 956 &p->addr, BUS_DMA_WAITOK|sc->sc_dmamap_flags); 957 if (error) 958 goto free; 959 960 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 961 0, BUS_DMA_WAITOK, &p->map); 962 if (error) 963 goto unmap; 964 965 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 966 BUS_DMA_WAITOK); 967 if (error) 968 goto destroy; 969 return (0); 970 971 destroy: 972 bus_dmamap_destroy(sc->dmat, p->map); 973 unmap: 974 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 975 free: 976 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 977 return error; 978 } 979 980 static int 981 auacer_freemem(struct auacer_softc *sc, struct auacer_dma *p) 982 { 983 984 bus_dmamap_unload(sc->dmat, p->map); 985 bus_dmamap_destroy(sc->dmat, p->map); 986 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 987 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 988 return 0; 989 } 990 991 static int 992 auacer_alloc_cdata(struct auacer_softc *sc) 993 { 994 bus_dma_segment_t seg; 995 int error, rseg; 996 997 /* 998 * Allocate the control data structure, and create and load the 999 * DMA map for it. 1000 */ 1001 if ((error = bus_dmamem_alloc(sc->dmat, 1002 sizeof(struct auacer_cdata), 1003 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1004 aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n", 1005 error); 1006 goto fail_0; 1007 } 1008 1009 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1010 sizeof(struct auacer_cdata), 1011 (void **) &sc->sc_cdata, 1012 sc->sc_dmamap_flags)) != 0) { 1013 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", 1014 error); 1015 goto fail_1; 1016 } 1017 1018 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auacer_cdata), 1, 1019 sizeof(struct auacer_cdata), 0, 0, 1020 &sc->sc_cddmamap)) != 0) { 1021 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 1022 "error = %d\n", error); 1023 goto fail_2; 1024 } 1025 1026 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1027 sc->sc_cdata, sizeof(struct auacer_cdata), 1028 NULL, 0)) != 0) { 1029 aprint_error_dev(sc->sc_dev, "unable to load control data DMA map, " 1030 "error = %d\n", error); 1031 goto fail_3; 1032 } 1033 1034 return 0; 1035 1036 fail_3: 1037 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1038 fail_2: 1039 bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata, 1040 sizeof(struct auacer_cdata)); 1041 fail_1: 1042 bus_dmamem_free(sc->dmat, &seg, rseg); 1043 fail_0: 1044 return error; 1045 } 1046 1047 static bool 1048 auacer_resume(device_t dv, const pmf_qual_t *qual) 1049 { 1050 struct auacer_softc *sc = device_private(dv); 1051 1052 mutex_enter(&sc->sc_lock); 1053 mutex_spin_enter(&sc->sc_intr_lock); 1054 auacer_reset_codec(sc); 1055 mutex_spin_exit(&sc->sc_intr_lock); 1056 delay(1000); 1057 sc->codec_if->vtbl->restore_ports(sc->codec_if); 1058 mutex_exit(&sc->sc_lock); 1059 1060 return true; 1061 } 1062
Indexes created Fri Oct 31 11:10:07 GMT 2025