auacer.c revision 1.5.2.1
1 /* $NetBSD: auacer.c,v 1.5.2.1 2005/01/02 20:03:10 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Acer Labs M5455 audio driver 41 * 42 * Acer provides data sheets after signing an NDA, so this is guess work. 43 * The chip behaves somewhat like the Intel i8x0, so this driver 44 * is loosely based on the auich driver. Additional information taken from 45 * the ALSA intel8x0.c driver (which handles M5455 as well). 46 * 47 * As an historical note one can observe that the auich driver borrows 48 * lot from the first NetBSD PCI audio driver, the eap driver. But this 49 * is not attributed anywhere. 50 */ 51 52 53 #include <sys/cdefs.h> 54 __KERNEL_RCSID(0, "$NetBSD: auacer.c,v 1.5.2.1 2005/01/02 20:03:10 kent Exp $"); 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/malloc.h> 60 #include <sys/device.h> 61 #include <sys/fcntl.h> 62 #include <sys/proc.h> 63 64 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 65 66 #include <dev/pci/pcidevs.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/auacerreg.h> 69 70 #include <sys/audioio.h> 71 #include <dev/audio_if.h> 72 #include <dev/mulaw.h> 73 #include <dev/auconv.h> 74 75 #include <machine/bus.h> 76 77 #include <dev/ic/ac97reg.h> 78 #include <dev/ic/ac97var.h> 79 80 struct auacer_dma { 81 bus_dmamap_t map; 82 caddr_t addr; 83 bus_dma_segment_t segs[1]; 84 int nsegs; 85 size_t size; 86 struct auacer_dma *next; 87 }; 88 89 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 90 #define KERNADDR(p) ((void *)((p)->addr)) 91 92 struct auacer_cdata { 93 struct auacer_dmalist ic_dmalist_pcmo[ALI_DMALIST_MAX]; 94 }; 95 96 struct auacer_chan { 97 uint32_t ptr; 98 uint32_t start, p, end; 99 uint32_t blksize, fifoe; 100 uint32_t ack; 101 uint32_t port; 102 struct auacer_dmalist *dmalist; 103 void (*intr)(void *); 104 void *arg; 105 }; 106 107 struct auacer_softc { 108 struct device sc_dev; 109 void *sc_ih; 110 111 audio_device_t sc_audev; 112 113 bus_space_tag_t iot; 114 bus_space_handle_t mix_ioh; 115 bus_space_handle_t aud_ioh; 116 bus_dma_tag_t dmat; 117 118 struct ac97_codec_if *codec_if; 119 struct ac97_host_if host_if; 120 121 /* DMA scatter-gather lists. */ 122 bus_dmamap_t sc_cddmamap; 123 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 124 125 struct auacer_cdata *sc_cdata; 126 127 struct auacer_chan sc_pcmo; 128 129 struct auacer_dma *sc_dmas; 130 131 pci_chipset_tag_t sc_pc; 132 pcitag_t sc_pt; 133 134 int sc_dmamap_flags; 135 136 /* Power Management */ 137 void *sc_powerhook; 138 int sc_suspend; 139 140 #define AUACER_NFORMATS 3 141 struct audio_format sc_formats[AUACER_NFORMATS]; 142 struct audio_encoding_set *sc_encodings; 143 }; 144 145 #define READ1(sc, a) bus_space_read_1(sc->iot, sc->aud_ioh, a) 146 #define READ2(sc, a) bus_space_read_2(sc->iot, sc->aud_ioh, a) 147 #define READ4(sc, a) bus_space_read_4(sc->iot, sc->aud_ioh, a) 148 #define WRITE1(sc, a, v) bus_space_write_1(sc->iot, sc->aud_ioh, a, v) 149 #define WRITE2(sc, a, v) bus_space_write_2(sc->iot, sc->aud_ioh, a, v) 150 #define WRITE4(sc, a, v) bus_space_write_4(sc->iot, sc->aud_ioh, a, v) 151 152 /* Debug */ 153 #ifdef AUACER_DEBUG 154 #define DPRINTF(l,x) do { if (auacer_debug & (l)) printf x; } while(0) 155 int auacer_debug = 0; 156 #define ALI_DEBUG_CODECIO 0x0001 157 #define ALI_DEBUG_DMA 0x0002 158 #define ALI_DEBUG_INTR 0x0004 159 #define ALI_DEBUG_API 0x0008 160 #define ALI_DEBUG_MIXERAPI 0x0010 161 #else 162 #define DPRINTF(x,y) /* nothing */ 163 #endif 164 165 int auacer_match(struct device *, struct cfdata *, void *); 166 void auacer_attach(struct device *, struct device *, void *); 167 int auacer_intr(void *); 168 169 CFATTACH_DECL(auacer, sizeof(struct auacer_softc), 170 auacer_match, auacer_attach, NULL, NULL); 171 172 int auacer_open(void *, int); 173 void auacer_close(void *); 174 int auacer_query_encoding(void *, struct audio_encoding *); 175 int auacer_set_params(void *, int, int, audio_params_t *, audio_params_t *, 176 stream_filter_list_t *, stream_filter_list_t *); 177 int auacer_round_blocksize(void *, int); 178 int auacer_halt_output(void *); 179 int auacer_halt_input(void *); 180 int auacer_getdev(void *, struct audio_device *); 181 int auacer_set_port(void *, mixer_ctrl_t *); 182 int auacer_get_port(void *, mixer_ctrl_t *); 183 int auacer_query_devinfo(void *, mixer_devinfo_t *); 184 void *auacer_allocm(void *, int, size_t, struct malloc_type *, int); 185 void auacer_freem(void *, void *, struct malloc_type *); 186 size_t auacer_round_buffersize(void *, int, size_t); 187 paddr_t auacer_mappage(void *, void *, off_t, int); 188 int auacer_get_props(void *); 189 int auacer_trigger_output(void *, void *, void *, int, void (*)(void *), 190 void *, const audio_params_t *); 191 int auacer_trigger_input(void *, void *, void *, int, void (*)(void *), 192 void *, const audio_params_t *); 193 194 int auacer_alloc_cdata(struct auacer_softc *); 195 196 int auacer_allocmem(struct auacer_softc *, size_t, size_t, 197 struct auacer_dma *); 198 int auacer_freemem(struct auacer_softc *, struct auacer_dma *); 199 200 void auacer_powerhook(int, void *); 201 int auacer_set_rate(struct auacer_softc *, int, u_int); 202 void auacer_finish_attach(struct device *); 203 204 static void auacer_reset(struct auacer_softc *sc); 205 206 struct audio_hw_if auacer_hw_if = { 207 auacer_open, 208 auacer_close, 209 NULL, /* drain */ 210 auacer_query_encoding, 211 auacer_set_params, 212 auacer_round_blocksize, 213 NULL, /* commit_setting */ 214 NULL, /* init_output */ 215 NULL, /* init_input */ 216 NULL, /* start_output */ 217 NULL, /* start_input */ 218 auacer_halt_output, 219 auacer_halt_input, 220 NULL, /* speaker_ctl */ 221 auacer_getdev, 222 NULL, /* getfd */ 223 auacer_set_port, 224 auacer_get_port, 225 auacer_query_devinfo, 226 auacer_allocm, 227 auacer_freem, 228 auacer_round_buffersize, 229 auacer_mappage, 230 auacer_get_props, 231 auacer_trigger_output, 232 auacer_trigger_input, 233 NULL, /* dev_ioctl */ 234 }; 235 236 #define AUACER_FORMATS_4CH 1 237 #define AUACER_FORMATS_6CH 2 238 static const struct audio_format auacer_formats[AUACER_NFORMATS] = { 239 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 240 2, AUFMT_STEREO, 0, {8000, 48000}}, 241 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 242 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 243 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 244 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 245 }; 246 247 int auacer_attach_codec(void *, struct ac97_codec_if *); 248 int auacer_read_codec(void *, u_int8_t, u_int16_t *); 249 int auacer_write_codec(void *, u_int8_t, u_int16_t); 250 int auacer_reset_codec(void *); 251 252 int 253 auacer_match(struct device *parent, struct cfdata *match, void *aux) 254 { 255 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 256 257 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 258 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M5455) 259 return 1; 260 return 0; 261 } 262 263 void 264 auacer_attach(struct device *parent, struct device *self, void *aux) 265 { 266 struct auacer_softc *sc = (struct auacer_softc *)self; 267 struct pci_attach_args *pa = aux; 268 pci_intr_handle_t ih; 269 bus_size_t aud_size; 270 pcireg_t v; 271 const char *intrstr; 272 int i; 273 274 aprint_normal(": Acer Labs M5455 Audio controller\n"); 275 276 if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, &sc->iot, 277 &sc->aud_ioh, NULL, &aud_size)) { 278 aprint_error(": can't map i/o space\n"); 279 return; 280 } 281 282 sc->sc_pc = pa->pa_pc; 283 sc->sc_pt = pa->pa_tag; 284 sc->dmat = pa->pa_dmat; 285 286 sc->sc_dmamap_flags = BUS_DMA_COHERENT; /* XXX remove */ 287 288 /* enable bus mastering */ 289 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 290 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 291 v | PCI_COMMAND_MASTER_ENABLE); 292 293 /* Map and establish the interrupt. */ 294 if (pci_intr_map(pa, &ih)) { 295 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 296 return; 297 } 298 intrstr = pci_intr_string(pa->pa_pc, ih); 299 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 300 auacer_intr, sc); 301 if (sc->sc_ih == NULL) { 302 aprint_error("%s: can't establish interrupt", 303 sc->sc_dev.dv_xname); 304 if (intrstr != NULL) 305 aprint_normal(" at %s", intrstr); 306 aprint_normal("\n"); 307 return; 308 } 309 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 310 311 strlcpy(sc->sc_audev.name, "M5455 AC97", MAX_AUDIO_DEV_LEN); 312 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 313 "0x%02x", PCI_REVISION(pa->pa_class)); 314 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 315 316 /* Set up DMA lists. */ 317 auacer_alloc_cdata(sc); 318 sc->sc_pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 319 sc->sc_pcmo.ptr = 0; 320 sc->sc_pcmo.port = ALI_BASE_PO; 321 322 DPRINTF(ALI_DEBUG_DMA, ("auacer_attach: lists %p\n", 323 sc->sc_pcmo.dmalist)); 324 325 sc->host_if.arg = sc; 326 sc->host_if.attach = auacer_attach_codec; 327 sc->host_if.read = auacer_read_codec; 328 sc->host_if.write = auacer_write_codec; 329 sc->host_if.reset = auacer_reset_codec; 330 331 if (ac97_attach(&sc->host_if, self) != 0) 332 return; 333 334 /* setup audio_format */ 335 memcpy(sc->sc_formats, auacer_formats, sizeof(auacer_formats)); 336 if (!AC97_IS_4CH(sc->codec_if)) 337 AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_4CH]); 338 if (!AC97_IS_6CH(sc->codec_if)) 339 AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_6CH]); 340 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 341 for (i = 0; i < AUACER_NFORMATS; i++) { 342 sc->sc_formats[i].frequency_type = 1; 343 sc->sc_formats[i].frequency[0] = 48000; 344 } 345 } 346 347 if (0 != auconv_create_encodings(sc->sc_formats, AUACER_NFORMATS, 348 &sc->sc_encodings)) { 349 return; 350 } 351 352 /* Watch for power change */ 353 sc->sc_suspend = PWR_RESUME; 354 sc->sc_powerhook = powerhook_establish(auacer_powerhook, sc); 355 356 audio_attach_mi(&auacer_hw_if, sc, &sc->sc_dev); 357 358 auacer_reset(sc); 359 } 360 361 static int 362 auacer_ready_codec(struct auacer_softc *sc, int mask) 363 { 364 int count = 0; 365 366 for (count = 0; count < 0x7f; count++) { 367 int val = READ1(sc, ALI_CSPSR); 368 if (val & mask) 369 return 0; 370 } 371 372 aprint_normal("auacer_ready_codec: AC97 codec ready timeout.\n"); 373 return EBUSY; 374 } 375 376 static int 377 auacer_sema_codec(struct auacer_softc *sc) 378 { 379 int time = 100; 380 381 while (time-- && (READ4(sc, ALI_CAS) & ALI_CAS_SEM_BUSY)) 382 delay(1); 383 if (!time) 384 aprint_normal("auacer_sema_codec: timeout\n"); 385 return auacer_ready_codec(sc, ALI_CSPSR_CODEC_READY); 386 } 387 388 int 389 auacer_read_codec(void *v, u_int8_t reg, u_int16_t *val) 390 { 391 struct auacer_softc *sc = v; 392 393 if (auacer_sema_codec(sc)) 394 return EIO; 395 396 reg |= ALI_CPR_ADDR_READ; 397 #if 0 398 if (ac97->num) 399 reg |= ALI_CPR_ADDR_SECONDARY; 400 #endif 401 WRITE2(sc, ALI_CPR_ADDR, reg); 402 if (auacer_ready_codec(sc, ALI_CSPSR_READ_OK)) 403 return EIO; 404 *val = READ2(sc, ALI_SPR); 405 406 DPRINTF(ALI_DEBUG_CODECIO, ("auacer_read_codec: reg=0x%x val=0x%x\n", 407 reg, *val)); 408 409 return 0; 410 } 411 412 int 413 auacer_write_codec(void *v, u_int8_t reg, u_int16_t val) 414 { 415 struct auacer_softc *sc = v; 416 417 DPRINTF(ALI_DEBUG_CODECIO, ("auacer_write_codec: reg=0x%x val=0x%x\n", 418 reg, val)); 419 420 if (auacer_sema_codec(sc)) 421 return EIO; 422 WRITE2(sc, ALI_CPR, val); 423 #if 0 424 if (ac97->num) 425 reg |= ALI_CPR_ADDR_SECONDARY; 426 #endif 427 WRITE2(sc, ALI_CPR_ADDR, reg); 428 auacer_ready_codec(sc, ALI_CSPSR_WRITE_OK); 429 return 0; 430 } 431 432 int 433 auacer_attach_codec(void *v, struct ac97_codec_if *cif) 434 { 435 struct auacer_softc *sc = v; 436 437 sc->codec_if = cif; 438 return 0; 439 } 440 441 int 442 auacer_reset_codec(void *v) 443 { 444 struct auacer_softc *sc = v; 445 u_int32_t reg; 446 int i = 0; 447 448 reg = READ4(sc, ALI_SCR); 449 if ((reg & 2) == 0) /* Cold required */ 450 reg |= 2; 451 else 452 reg |= 1; /* Warm */ 453 reg &= ~0x80000000; /* ACLink on */ 454 WRITE4(sc, ALI_SCR, reg); 455 456 while (i < 10) { 457 if ((READ4(sc, ALI_INTERRUPTSR) & ALI_INT_GPIO) == 0) 458 break; 459 delay(50000); /* XXX */ 460 i++; 461 } 462 if (i == 10) { 463 return EIO; 464 } 465 466 for (i = 0; i < 10; i++) { 467 reg = READ4(sc, ALI_RTSR); 468 if (reg & 0x80) /* primary codec */ 469 break; 470 WRITE4(sc, ALI_RTSR, reg | 0x80); 471 delay(50000); /* XXX */ 472 } 473 474 return 0; 475 } 476 477 static void 478 auacer_reset(struct auacer_softc *sc) 479 { 480 WRITE4(sc, ALI_SCR, ALI_SCR_RESET); 481 WRITE4(sc, ALI_FIFOCR1, 0x83838383); 482 WRITE4(sc, ALI_FIFOCR2, 0x83838383); 483 WRITE4(sc, ALI_FIFOCR3, 0x83838383); 484 WRITE4(sc, ALI_INTERFACECR, ALI_IF_PO); /* XXX pcm out only */ 485 WRITE4(sc, ALI_INTERRUPTCR, 0x00000000); 486 WRITE4(sc, ALI_INTERRUPTSR, 0x00000000); 487 } 488 489 int 490 auacer_open(void *v, int flags) 491 { 492 DPRINTF(ALI_DEBUG_API, ("auacer_open: flags=%d\n", flags)); 493 return 0; 494 } 495 496 void 497 auacer_close(void *v) 498 { 499 DPRINTF(ALI_DEBUG_API, ("auacer_close\n")); 500 } 501 502 int 503 auacer_query_encoding(void *v, struct audio_encoding *aep) 504 { 505 struct auacer_softc *sc; 506 507 DPRINTF(ALI_DEBUG_API, ("auacer_query_encoding\n")); 508 sc = v; 509 return auconv_query_encoding(sc->sc_encodings, aep); 510 } 511 512 int 513 auacer_set_rate(struct auacer_softc *sc, int mode, u_int srate) 514 { 515 int ret; 516 u_int ratetmp; 517 518 DPRINTF(ALI_DEBUG_API, ("auacer_set_rate: srate=%lu\n", srate)); 519 520 ratetmp = srate; 521 if (mode == AUMODE_RECORD) 522 return sc->codec_if->vtbl->set_rate(sc->codec_if, 523 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 524 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 525 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 526 if (ret) 527 return ret; 528 ratetmp = srate; 529 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 530 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 531 if (ret) 532 return ret; 533 ratetmp = srate; 534 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 535 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 536 return ret; 537 } 538 539 int 540 auacer_set_params(void *v, int setmode, int usemode, audio_params_t *play, 541 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 542 { 543 struct auacer_softc *sc = v; 544 struct audio_params *p; 545 stream_filter_list_t *fil; 546 uint32_t control; 547 int mode, index; 548 549 DPRINTF(ALI_DEBUG_API, ("auacer_set_params\n")); 550 551 for (mode = AUMODE_RECORD; mode != -1; 552 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 553 if ((setmode & mode) == 0) 554 continue; 555 556 p = mode == AUMODE_PLAY ? play : rec; 557 if (p == NULL) 558 continue; 559 560 if ((p->sample_rate != 8000) && 561 (p->sample_rate != 11025) && 562 (p->sample_rate != 12000) && 563 (p->sample_rate != 16000) && 564 (p->sample_rate != 22050) && 565 (p->sample_rate != 24000) && 566 (p->sample_rate != 32000) && 567 (p->sample_rate != 44100) && 568 (p->sample_rate != 48000)) 569 return (EINVAL); 570 571 fil = mode == AUMODE_PLAY ? pfil : rfil; 572 index = auconv_set_converter(sc->sc_formats, AUACER_NFORMATS, 573 mode, p, TRUE, fil); 574 if (index < 0) 575 return EINVAL; 576 if (fil->req_size > 0) 577 p = &fil->filters[0].param; 578 /* p points HW encoding */ 579 if (sc->sc_formats[index].frequency_type != 1 580 && auacer_set_rate(sc, mode, p->sample_rate)) 581 return EINVAL; 582 if (mode == AUMODE_PLAY) { 583 control = READ4(sc, ALI_SCR); 584 control &= ~ALI_SCR_PCM_246_MASK; 585 if (p->channels == 4) 586 control |= ALI_SCR_PCM_4; 587 else if (p->channels == 6) 588 control |= ALI_SCR_PCM_6; 589 WRITE4(sc, ALI_SCR, control); 590 } 591 } 592 593 return (0); 594 } 595 596 int 597 auacer_round_blocksize(void *v, int blk) 598 { 599 600 return (blk & ~0x3f); /* keep good alignment */ 601 } 602 603 static void 604 auacer_halt(struct auacer_softc *sc, struct auacer_chan *chan) 605 { 606 uint32_t val; 607 uint8_t port = chan->port; 608 uint32_t slot; 609 610 DPRINTF(ALI_DEBUG_API, ("auacer_halt: port=0x%x\n", port)); 611 612 chan->intr = 0; 613 614 slot = ALI_PORT2SLOT(port); 615 616 val = READ4(sc, ALI_DMACR); 617 val |= 1 << (slot+16); /* pause */ 618 val &= ~(1 << slot); /* no start */ 619 WRITE4(sc, ALI_DMACR, val); 620 WRITE1(sc, port + ALI_OFF_CR, 0); 621 while (READ1(sc, port + ALI_OFF_CR)) 622 ; 623 /* reset whole DMA things */ 624 WRITE1(sc, port + ALI_OFF_CR, ALI_CR_RR); 625 /* clear interrupts */ 626 WRITE1(sc, port + ALI_OFF_SR, READ1(sc, port+ALI_OFF_SR) | ALI_SR_W1TC); 627 WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(port)); 628 } 629 630 int 631 auacer_halt_output(void *v) 632 { 633 struct auacer_softc *sc = v; 634 635 DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_output\n")); 636 637 auacer_halt(sc, &sc->sc_pcmo); 638 639 return (0); 640 } 641 642 int 643 auacer_halt_input(void *v) 644 { 645 /*struct auacer_softc *sc = v;*/ 646 647 DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_input\n")); 648 649 return (0); 650 } 651 652 int 653 auacer_getdev(void *v, struct audio_device *adp) 654 { 655 struct auacer_softc *sc = v; 656 657 DPRINTF(ALI_DEBUG_API, ("auacer_getdev\n")); 658 659 *adp = sc->sc_audev; 660 return (0); 661 } 662 663 int 664 auacer_set_port(void *v, mixer_ctrl_t *cp) 665 { 666 struct auacer_softc *sc = v; 667 668 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_set_port\n")); 669 670 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 671 } 672 673 int 674 auacer_get_port(void *v, mixer_ctrl_t *cp) 675 { 676 struct auacer_softc *sc = v; 677 678 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_get_port\n")); 679 680 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 681 } 682 683 int 684 auacer_query_devinfo(void *v, mixer_devinfo_t *dp) 685 { 686 struct auacer_softc *sc = v; 687 688 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_query_devinfo\n")); 689 690 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 691 } 692 693 void * 694 auacer_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 695 int flags) 696 { 697 struct auacer_softc *sc = v; 698 struct auacer_dma *p; 699 int error; 700 701 if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX)) 702 return (NULL); 703 704 p = malloc(sizeof(*p), pool, flags | M_ZERO); 705 if (p == NULL) 706 return (NULL); 707 708 error = auacer_allocmem(sc, size, 0, p); 709 if (error) { 710 free(p, pool); 711 return (NULL); 712 } 713 714 p->next = sc->sc_dmas; 715 sc->sc_dmas = p; 716 717 return (KERNADDR(p)); 718 } 719 720 void 721 auacer_freem(void *v, void *ptr, struct malloc_type *pool) 722 { 723 struct auacer_softc *sc = v; 724 struct auacer_dma *p, **pp; 725 726 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 727 if (KERNADDR(p) == ptr) { 728 auacer_freemem(sc, p); 729 *pp = p->next; 730 free(p, pool); 731 return; 732 } 733 } 734 } 735 736 size_t 737 auacer_round_buffersize(void *v, int direction, size_t size) 738 { 739 740 if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX)) 741 size = ALI_DMALIST_MAX * ALI_DMASEG_MAX; 742 743 return size; 744 } 745 746 paddr_t 747 auacer_mappage(void *v, void *mem, off_t off, int prot) 748 { 749 struct auacer_softc *sc = v; 750 struct auacer_dma *p; 751 752 if (off < 0) 753 return (-1); 754 755 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 756 ; 757 if (!p) 758 return (-1); 759 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 760 off, prot, BUS_DMA_WAITOK)); 761 } 762 763 int 764 auacer_get_props(void *v) 765 { 766 struct auacer_softc *sc = v; 767 int props; 768 769 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 770 /* 771 * Even if the codec is fixed-rate, set_param() succeeds for any sample 772 * rate because of aurateconv. Applications can't know what rate the 773 * device can process in the case of mmap(). 774 */ 775 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 776 props |= AUDIO_PROP_MMAP; 777 return props; 778 } 779 780 static void 781 auacer_add_entry(struct auacer_chan *chan) 782 { 783 struct auacer_dmalist *q; 784 785 q = &chan->dmalist[chan->ptr]; 786 787 DPRINTF(ALI_DEBUG_INTR, 788 ("auacer_add_entry: %p = %x @ 0x%x\n", 789 q, chan->blksize / 2, chan->p)); 790 791 q->base = htole32(chan->p); 792 q->len = htole32((chan->blksize / ALI_SAMPLE_SIZE) | ALI_DMAF_IOC); 793 chan->p += chan->blksize; 794 if (chan->p >= chan->end) 795 chan->p = chan->start; 796 797 if (++chan->ptr >= ALI_DMALIST_MAX) 798 chan->ptr = 0; 799 } 800 801 static void 802 auacer_upd_chan(struct auacer_softc *sc, struct auacer_chan *chan) 803 { 804 uint32_t sts; 805 uint32_t civ; 806 807 sts = READ2(sc, chan->port + ALI_OFF_SR); 808 /* intr ack */ 809 WRITE2(sc, chan->port + ALI_OFF_SR, sts & ALI_SR_W1TC); 810 WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(chan->port)); 811 812 DPRINTF(ALI_DEBUG_INTR, ("auacer_upd_chan: sts=0x%x\n", sts)); 813 814 if (sts & ALI_SR_DMA_INT_FIFO) { 815 printf("%s: fifo underrun # %u\n", 816 sc->sc_dev.dv_xname, ++chan->fifoe); 817 } 818 819 civ = READ1(sc, chan->port + ALI_OFF_CIV); 820 821 DPRINTF(ALI_DEBUG_INTR,("auacer_intr: civ=%u ptr=%u\n",civ,chan->ptr)); 822 823 /* XXX */ 824 while (chan->ptr != civ) { 825 auacer_add_entry(chan); 826 } 827 828 WRITE1(sc, chan->port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK); 829 830 while (chan->ack != civ) { 831 if (chan->intr) { 832 DPRINTF(ALI_DEBUG_INTR,("auacer_upd_chan: callback\n")); 833 chan->intr(chan->arg); 834 } 835 chan->ack++; 836 if (chan->ack >= ALI_DMALIST_MAX) 837 chan->ack = 0; 838 } 839 } 840 841 int 842 auacer_intr(void *v) 843 { 844 struct auacer_softc *sc = v; 845 int ret, intrs; 846 847 intrs = READ4(sc, ALI_INTERRUPTSR); 848 DPRINTF(ALI_DEBUG_INTR, ("auacer_intr: intrs=0x%x\n", intrs)); 849 850 ret = 0; 851 if (intrs & ALI_INT_PCMOUT) { 852 auacer_upd_chan(sc, &sc->sc_pcmo); 853 ret++; 854 } 855 856 return ret != 0; 857 } 858 859 static void 860 auacer_setup_chan(struct auacer_softc *sc, struct auacer_chan *chan, 861 uint32_t start, uint32_t size, uint32_t blksize, 862 void (*intr)(void *), void *arg) 863 { 864 uint32_t port, slot; 865 uint32_t offs, val; 866 867 chan->start = start; 868 chan->ptr = 0; 869 chan->p = chan->start; 870 chan->end = chan->start + size; 871 chan->blksize = blksize; 872 chan->ack = 0; 873 chan->intr = intr; 874 chan->arg = arg; 875 876 auacer_add_entry(chan); 877 auacer_add_entry(chan); 878 879 port = chan->port; 880 slot = ALI_PORT2SLOT(port); 881 882 WRITE1(sc, port + ALI_OFF_CIV, 0); 883 WRITE1(sc, port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK); 884 offs = (char *)chan->dmalist - (char *)sc->sc_cdata; 885 WRITE4(sc, port + ALI_OFF_BDBAR, sc->sc_cddma + offs); 886 WRITE1(sc, port + ALI_OFF_CR, 887 ALI_CR_IOCE | ALI_CR_FEIE | ALI_CR_LVBIE | ALI_CR_RPBM); 888 val = READ4(sc, ALI_DMACR); 889 val &= ~(1 << (slot+16)); /* no pause */ 890 val |= 1 << slot; /* start */ 891 WRITE4(sc, ALI_DMACR, val); 892 } 893 894 int 895 auacer_trigger_output(void *v, void *start, void *end, int blksize, 896 void (*intr)(void *), void *arg, const audio_params_t *param) 897 { 898 struct auacer_softc *sc = v; 899 struct auacer_dma *p; 900 uint32_t size; 901 902 DPRINTF(ALI_DEBUG_DMA, 903 ("auacer_trigger_output(%p, %p, %d, %p, %p, %p)\n", 904 start, end, blksize, intr, arg, param)); 905 906 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 907 ; 908 if (!p) { 909 printf("auacer_trigger_output: bad addr %p\n", start); 910 return (EINVAL); 911 } 912 913 size = (char *)end - (char *)start; 914 auacer_setup_chan(sc, &sc->sc_pcmo, DMAADDR(p), size, blksize, 915 intr, arg); 916 917 return 0; 918 } 919 920 int 921 auacer_trigger_input(void *v, void *start, void *end, int blksize, 922 void (*intr)(void *), void *arg, 923 const audio_params_t *param) 924 { 925 return (EINVAL); 926 } 927 928 int 929 auacer_allocmem(struct auacer_softc *sc, size_t size, size_t align, 930 struct auacer_dma *p) 931 { 932 int error; 933 934 p->size = size; 935 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 936 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 937 &p->nsegs, BUS_DMA_NOWAIT); 938 if (error) 939 return (error); 940 941 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 942 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 943 if (error) 944 goto free; 945 946 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 947 0, BUS_DMA_NOWAIT, &p->map); 948 if (error) 949 goto unmap; 950 951 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 952 BUS_DMA_NOWAIT); 953 if (error) 954 goto destroy; 955 return (0); 956 957 destroy: 958 bus_dmamap_destroy(sc->dmat, p->map); 959 unmap: 960 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 961 free: 962 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 963 return (error); 964 } 965 966 int 967 auacer_freemem(struct auacer_softc *sc, struct auacer_dma *p) 968 { 969 970 bus_dmamap_unload(sc->dmat, p->map); 971 bus_dmamap_destroy(sc->dmat, p->map); 972 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 973 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 974 return (0); 975 } 976 977 int 978 auacer_alloc_cdata(struct auacer_softc *sc) 979 { 980 bus_dma_segment_t seg; 981 int error, rseg; 982 983 /* 984 * Allocate the control data structure, and create and load the 985 * DMA map for it. 986 */ 987 if ((error = bus_dmamem_alloc(sc->dmat, 988 sizeof(struct auacer_cdata), 989 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 990 printf("%s: unable to allocate control data, error = %d\n", 991 sc->sc_dev.dv_xname, error); 992 goto fail_0; 993 } 994 995 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 996 sizeof(struct auacer_cdata), 997 (caddr_t *) &sc->sc_cdata, 998 sc->sc_dmamap_flags)) != 0) { 999 printf("%s: unable to map control data, error = %d\n", 1000 sc->sc_dev.dv_xname, error); 1001 goto fail_1; 1002 } 1003 1004 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auacer_cdata), 1, 1005 sizeof(struct auacer_cdata), 0, 0, 1006 &sc->sc_cddmamap)) != 0) { 1007 printf("%s: unable to create control data DMA map, " 1008 "error = %d\n", sc->sc_dev.dv_xname, error); 1009 goto fail_2; 1010 } 1011 1012 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1013 sc->sc_cdata, sizeof(struct auacer_cdata), 1014 NULL, 0)) != 0) { 1015 printf("%s: unable to load control data DMA map, " 1016 "error = %d\n", sc->sc_dev.dv_xname, error); 1017 goto fail_3; 1018 } 1019 1020 return (0); 1021 1022 fail_3: 1023 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1024 fail_2: 1025 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1026 sizeof(struct auacer_cdata)); 1027 fail_1: 1028 bus_dmamem_free(sc->dmat, &seg, rseg); 1029 fail_0: 1030 return (error); 1031 } 1032 1033 void 1034 auacer_powerhook(int why, void *addr) 1035 { 1036 struct auacer_softc *sc = (struct auacer_softc *)addr; 1037 1038 switch (why) { 1039 case PWR_SUSPEND: 1040 case PWR_STANDBY: 1041 /* Power down */ 1042 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1043 sc->sc_suspend = why; 1044 break; 1045 1046 case PWR_RESUME: 1047 /* Wake up */ 1048 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1049 if (sc->sc_suspend == PWR_RESUME) { 1050 printf("%s: resume without suspend.\n", 1051 sc->sc_dev.dv_xname); 1052 sc->sc_suspend = why; 1053 return; 1054 } 1055 sc->sc_suspend = why; 1056 auacer_reset_codec(sc); 1057 delay(1000); 1058 sc->codec_if->vtbl->restore_ports(sc->codec_if); 1059 break; 1060 1061 case PWR_SOFTSUSPEND: 1062 case PWR_SOFTSTANDBY: 1063 case PWR_SOFTRESUME: 1064 break; 1065 } 1066 } 1067
Indexes created Thu Oct 30 03:10:01 GMT 2025