auacer.c revision 1.7
1 /* $NetBSD: auacer.c,v 1.7 2005/01/15 15:19:52 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Acer Labs M5455 audio driver 41 * 42 * Acer provides data sheets after signing an NDA, so this is guess work. 43 * The chip behaves somewhat like the Intel i8x0, so this driver 44 * is loosely based on the auich driver. Additional information taken from 45 * the ALSA intel8x0.c driver (which handles M5455 as well). 46 * 47 * As an historical note one can observe that the auich driver borrows 48 * lot from the first NetBSD PCI audio driver, the eap driver. But this 49 * is not attributed anywhere. 50 */ 51 52 53 #include <sys/cdefs.h> 54 __KERNEL_RCSID(0, "$NetBSD: auacer.c,v 1.7 2005/01/15 15:19:52 kent Exp $"); 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/malloc.h> 60 #include <sys/device.h> 61 #include <sys/fcntl.h> 62 #include <sys/proc.h> 63 64 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 65 66 #include <dev/pci/pcidevs.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/auacerreg.h> 69 70 #include <sys/audioio.h> 71 #include <dev/audio_if.h> 72 #include <dev/mulaw.h> 73 #include <dev/auconv.h> 74 75 #include <machine/bus.h> 76 77 #include <dev/ic/ac97reg.h> 78 #include <dev/ic/ac97var.h> 79 80 struct auacer_dma { 81 bus_dmamap_t map; 82 caddr_t addr; 83 bus_dma_segment_t segs[1]; 84 int nsegs; 85 size_t size; 86 struct auacer_dma *next; 87 }; 88 89 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 90 #define KERNADDR(p) ((void *)((p)->addr)) 91 92 struct auacer_cdata { 93 struct auacer_dmalist ic_dmalist_pcmo[ALI_DMALIST_MAX]; 94 }; 95 96 struct auacer_chan { 97 uint32_t ptr; 98 uint32_t start, p, end; 99 uint32_t blksize, fifoe; 100 uint32_t ack; 101 uint32_t port; 102 struct auacer_dmalist *dmalist; 103 void (*intr)(void *); 104 void *arg; 105 }; 106 107 struct auacer_softc { 108 struct device sc_dev; 109 void *sc_ih; 110 111 audio_device_t sc_audev; 112 113 bus_space_tag_t iot; 114 bus_space_handle_t mix_ioh; 115 bus_space_handle_t aud_ioh; 116 bus_dma_tag_t dmat; 117 118 struct ac97_codec_if *codec_if; 119 struct ac97_host_if host_if; 120 121 /* DMA scatter-gather lists. */ 122 bus_dmamap_t sc_cddmamap; 123 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 124 125 struct auacer_cdata *sc_cdata; 126 127 struct auacer_chan sc_pcmo; 128 129 struct auacer_dma *sc_dmas; 130 131 pci_chipset_tag_t sc_pc; 132 pcitag_t sc_pt; 133 134 int sc_dmamap_flags; 135 136 /* Power Management */ 137 void *sc_powerhook; 138 int sc_suspend; 139 140 #define AUACER_NFORMATS 3 141 struct audio_format sc_formats[AUACER_NFORMATS]; 142 struct audio_encoding_set *sc_encodings; 143 }; 144 145 #define READ1(sc, a) bus_space_read_1(sc->iot, sc->aud_ioh, a) 146 #define READ2(sc, a) bus_space_read_2(sc->iot, sc->aud_ioh, a) 147 #define READ4(sc, a) bus_space_read_4(sc->iot, sc->aud_ioh, a) 148 #define WRITE1(sc, a, v) bus_space_write_1(sc->iot, sc->aud_ioh, a, v) 149 #define WRITE2(sc, a, v) bus_space_write_2(sc->iot, sc->aud_ioh, a, v) 150 #define WRITE4(sc, a, v) bus_space_write_4(sc->iot, sc->aud_ioh, a, v) 151 152 /* Debug */ 153 #ifdef AUACER_DEBUG 154 #define DPRINTF(l,x) do { if (auacer_debug & (l)) printf x; } while(0) 155 int auacer_debug = 0; 156 #define ALI_DEBUG_CODECIO 0x0001 157 #define ALI_DEBUG_DMA 0x0002 158 #define ALI_DEBUG_INTR 0x0004 159 #define ALI_DEBUG_API 0x0008 160 #define ALI_DEBUG_MIXERAPI 0x0010 161 #else 162 #define DPRINTF(x,y) /* nothing */ 163 #endif 164 165 int auacer_match(struct device *, struct cfdata *, void *); 166 void auacer_attach(struct device *, struct device *, void *); 167 int auacer_intr(void *); 168 169 CFATTACH_DECL(auacer, sizeof(struct auacer_softc), 170 auacer_match, auacer_attach, NULL, NULL); 171 172 int auacer_query_encoding(void *, struct audio_encoding *); 173 int auacer_set_params(void *, int, int, audio_params_t *, audio_params_t *, 174 stream_filter_list_t *, stream_filter_list_t *); 175 int auacer_round_blocksize(void *, int, int, const audio_params_t *); 176 int auacer_halt_output(void *); 177 int auacer_halt_input(void *); 178 int auacer_getdev(void *, struct audio_device *); 179 int auacer_set_port(void *, mixer_ctrl_t *); 180 int auacer_get_port(void *, mixer_ctrl_t *); 181 int auacer_query_devinfo(void *, mixer_devinfo_t *); 182 void *auacer_allocm(void *, int, size_t, struct malloc_type *, int); 183 void auacer_freem(void *, void *, struct malloc_type *); 184 size_t auacer_round_buffersize(void *, int, size_t); 185 paddr_t auacer_mappage(void *, void *, off_t, int); 186 int auacer_get_props(void *); 187 int auacer_trigger_output(void *, void *, void *, int, void (*)(void *), 188 void *, const audio_params_t *); 189 int auacer_trigger_input(void *, void *, void *, int, void (*)(void *), 190 void *, const audio_params_t *); 191 192 int auacer_alloc_cdata(struct auacer_softc *); 193 194 int auacer_allocmem(struct auacer_softc *, size_t, size_t, 195 struct auacer_dma *); 196 int auacer_freemem(struct auacer_softc *, struct auacer_dma *); 197 198 void auacer_powerhook(int, void *); 199 int auacer_set_rate(struct auacer_softc *, int, u_int); 200 void auacer_finish_attach(struct device *); 201 202 static void auacer_reset(struct auacer_softc *sc); 203 204 struct audio_hw_if auacer_hw_if = { 205 NULL, /* open */ 206 NULL, /* close */ 207 NULL, /* drain */ 208 auacer_query_encoding, 209 auacer_set_params, 210 auacer_round_blocksize, 211 NULL, /* commit_setting */ 212 NULL, /* init_output */ 213 NULL, /* init_input */ 214 NULL, /* start_output */ 215 NULL, /* start_input */ 216 auacer_halt_output, 217 auacer_halt_input, 218 NULL, /* speaker_ctl */ 219 auacer_getdev, 220 NULL, /* getfd */ 221 auacer_set_port, 222 auacer_get_port, 223 auacer_query_devinfo, 224 auacer_allocm, 225 auacer_freem, 226 auacer_round_buffersize, 227 auacer_mappage, 228 auacer_get_props, 229 auacer_trigger_output, 230 auacer_trigger_input, 231 NULL, /* dev_ioctl */ 232 }; 233 234 #define AUACER_FORMATS_4CH 1 235 #define AUACER_FORMATS_6CH 2 236 static const struct audio_format auacer_formats[AUACER_NFORMATS] = { 237 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 238 2, AUFMT_STEREO, 0, {8000, 48000}}, 239 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 240 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 241 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 242 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 243 }; 244 245 int auacer_attach_codec(void *, struct ac97_codec_if *); 246 int auacer_read_codec(void *, uint8_t, uint16_t *); 247 int auacer_write_codec(void *, uint8_t, uint16_t); 248 int auacer_reset_codec(void *); 249 250 int 251 auacer_match(struct device *parent, struct cfdata *match, void *aux) 252 { 253 struct pci_attach_args *pa; 254 255 pa = (struct pci_attach_args *)aux; 256 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 257 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M5455) 258 return 1; 259 return 0; 260 } 261 262 void 263 auacer_attach(struct device *parent, struct device *self, void *aux) 264 { 265 struct auacer_softc *sc; 266 struct pci_attach_args *pa; 267 pci_intr_handle_t ih; 268 bus_size_t aud_size; 269 pcireg_t v; 270 const char *intrstr; 271 int i; 272 273 sc = (struct auacer_softc *)self; 274 pa = aux; 275 aprint_normal(": Acer Labs M5455 Audio controller\n"); 276 277 if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, &sc->iot, 278 &sc->aud_ioh, NULL, &aud_size)) { 279 aprint_error(": can't map i/o space\n"); 280 return; 281 } 282 283 sc->sc_pc = pa->pa_pc; 284 sc->sc_pt = pa->pa_tag; 285 sc->dmat = pa->pa_dmat; 286 287 sc->sc_dmamap_flags = BUS_DMA_COHERENT; /* XXX remove */ 288 289 /* enable bus mastering */ 290 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 291 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 292 v | PCI_COMMAND_MASTER_ENABLE); 293 294 /* Map and establish the interrupt. */ 295 if (pci_intr_map(pa, &ih)) { 296 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 297 return; 298 } 299 intrstr = pci_intr_string(pa->pa_pc, ih); 300 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 301 auacer_intr, sc); 302 if (sc->sc_ih == NULL) { 303 aprint_error("%s: can't establish interrupt", 304 sc->sc_dev.dv_xname); 305 if (intrstr != NULL) 306 aprint_normal(" at %s", intrstr); 307 aprint_normal("\n"); 308 return; 309 } 310 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 311 312 strlcpy(sc->sc_audev.name, "M5455 AC97", MAX_AUDIO_DEV_LEN); 313 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 314 "0x%02x", PCI_REVISION(pa->pa_class)); 315 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 316 317 /* Set up DMA lists. */ 318 auacer_alloc_cdata(sc); 319 sc->sc_pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 320 sc->sc_pcmo.ptr = 0; 321 sc->sc_pcmo.port = ALI_BASE_PO; 322 323 DPRINTF(ALI_DEBUG_DMA, ("auacer_attach: lists %p\n", 324 sc->sc_pcmo.dmalist)); 325 326 sc->host_if.arg = sc; 327 sc->host_if.attach = auacer_attach_codec; 328 sc->host_if.read = auacer_read_codec; 329 sc->host_if.write = auacer_write_codec; 330 sc->host_if.reset = auacer_reset_codec; 331 332 if (ac97_attach(&sc->host_if, self) != 0) 333 return; 334 335 /* setup audio_format */ 336 memcpy(sc->sc_formats, auacer_formats, sizeof(auacer_formats)); 337 if (!AC97_IS_4CH(sc->codec_if)) 338 AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_4CH]); 339 if (!AC97_IS_6CH(sc->codec_if)) 340 AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_6CH]); 341 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 342 for (i = 0; i < AUACER_NFORMATS; i++) { 343 sc->sc_formats[i].frequency_type = 1; 344 sc->sc_formats[i].frequency[0] = 48000; 345 } 346 } 347 348 if (0 != auconv_create_encodings(sc->sc_formats, AUACER_NFORMATS, 349 &sc->sc_encodings)) { 350 return; 351 } 352 353 /* Watch for power change */ 354 sc->sc_suspend = PWR_RESUME; 355 sc->sc_powerhook = powerhook_establish(auacer_powerhook, sc); 356 357 audio_attach_mi(&auacer_hw_if, sc, &sc->sc_dev); 358 359 auacer_reset(sc); 360 } 361 362 static int 363 auacer_ready_codec(struct auacer_softc *sc, int mask) 364 { 365 int count; 366 367 for (count = 0; count < 0x7f; count++) { 368 int val = READ1(sc, ALI_CSPSR); 369 if (val & mask) 370 return 0; 371 } 372 373 aprint_normal("auacer_ready_codec: AC97 codec ready timeout.\n"); 374 return EBUSY; 375 } 376 377 static int 378 auacer_sema_codec(struct auacer_softc *sc) 379 { 380 int time; 381 382 time = 100; 383 while (time-- && (READ4(sc, ALI_CAS) & ALI_CAS_SEM_BUSY)) 384 delay(1); 385 if (!time) 386 aprint_normal("auacer_sema_codec: timeout\n"); 387 return auacer_ready_codec(sc, ALI_CSPSR_CODEC_READY); 388 } 389 390 int 391 auacer_read_codec(void *v, uint8_t reg, uint16_t *val) 392 { 393 struct auacer_softc *sc; 394 395 sc = v; 396 if (auacer_sema_codec(sc)) 397 return EIO; 398 399 reg |= ALI_CPR_ADDR_READ; 400 #if 0 401 if (ac97->num) 402 reg |= ALI_CPR_ADDR_SECONDARY; 403 #endif 404 WRITE2(sc, ALI_CPR_ADDR, reg); 405 if (auacer_ready_codec(sc, ALI_CSPSR_READ_OK)) 406 return EIO; 407 *val = READ2(sc, ALI_SPR); 408 409 DPRINTF(ALI_DEBUG_CODECIO, ("auacer_read_codec: reg=0x%x val=0x%x\n", 410 reg, *val)); 411 412 return 0; 413 } 414 415 int 416 auacer_write_codec(void *v, uint8_t reg, uint16_t val) 417 { 418 struct auacer_softc *sc; 419 420 DPRINTF(ALI_DEBUG_CODECIO, ("auacer_write_codec: reg=0x%x val=0x%x\n", 421 reg, val)); 422 sc = v; 423 if (auacer_sema_codec(sc)) 424 return EIO; 425 WRITE2(sc, ALI_CPR, val); 426 #if 0 427 if (ac97->num) 428 reg |= ALI_CPR_ADDR_SECONDARY; 429 #endif 430 WRITE2(sc, ALI_CPR_ADDR, reg); 431 auacer_ready_codec(sc, ALI_CSPSR_WRITE_OK); 432 return 0; 433 } 434 435 int 436 auacer_attach_codec(void *v, struct ac97_codec_if *cif) 437 { 438 struct auacer_softc *sc; 439 440 sc = v; 441 sc->codec_if = cif; 442 return 0; 443 } 444 445 int 446 auacer_reset_codec(void *v) 447 { 448 struct auacer_softc *sc; 449 uint32_t reg; 450 int i; 451 452 sc = v; 453 i = 0; 454 reg = READ4(sc, ALI_SCR); 455 if ((reg & 2) == 0) /* Cold required */ 456 reg |= 2; 457 else 458 reg |= 1; /* Warm */ 459 reg &= ~0x80000000; /* ACLink on */ 460 WRITE4(sc, ALI_SCR, reg); 461 462 while (i < 10) { 463 if ((READ4(sc, ALI_INTERRUPTSR) & ALI_INT_GPIO) == 0) 464 break; 465 delay(50000); /* XXX */ 466 i++; 467 } 468 if (i == 10) { 469 return EIO; 470 } 471 472 for (i = 0; i < 10; i++) { 473 reg = READ4(sc, ALI_RTSR); 474 if (reg & 0x80) /* primary codec */ 475 break; 476 WRITE4(sc, ALI_RTSR, reg | 0x80); 477 delay(50000); /* XXX */ 478 } 479 480 return 0; 481 } 482 483 static void 484 auacer_reset(struct auacer_softc *sc) 485 { 486 WRITE4(sc, ALI_SCR, ALI_SCR_RESET); 487 WRITE4(sc, ALI_FIFOCR1, 0x83838383); 488 WRITE4(sc, ALI_FIFOCR2, 0x83838383); 489 WRITE4(sc, ALI_FIFOCR3, 0x83838383); 490 WRITE4(sc, ALI_INTERFACECR, ALI_IF_PO); /* XXX pcm out only */ 491 WRITE4(sc, ALI_INTERRUPTCR, 0x00000000); 492 WRITE4(sc, ALI_INTERRUPTSR, 0x00000000); 493 } 494 495 int 496 auacer_query_encoding(void *v, struct audio_encoding *aep) 497 { 498 struct auacer_softc *sc; 499 500 DPRINTF(ALI_DEBUG_API, ("auacer_query_encoding\n")); 501 sc = v; 502 return auconv_query_encoding(sc->sc_encodings, aep); 503 } 504 505 int 506 auacer_set_rate(struct auacer_softc *sc, int mode, u_int srate) 507 { 508 int ret; 509 u_int ratetmp; 510 511 DPRINTF(ALI_DEBUG_API, ("auacer_set_rate: srate=%lu\n", srate)); 512 513 ratetmp = srate; 514 if (mode == AUMODE_RECORD) 515 return sc->codec_if->vtbl->set_rate(sc->codec_if, 516 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 517 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 518 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 519 if (ret) 520 return ret; 521 ratetmp = srate; 522 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 523 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 524 if (ret) 525 return ret; 526 ratetmp = srate; 527 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 528 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 529 return ret; 530 } 531 532 int 533 auacer_set_params(void *v, int setmode, int usemode, audio_params_t *play, 534 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 535 { 536 struct auacer_softc *sc; 537 struct audio_params *p; 538 stream_filter_list_t *fil; 539 uint32_t control; 540 int mode, index; 541 542 DPRINTF(ALI_DEBUG_API, ("auacer_set_params\n")); 543 sc = v; 544 for (mode = AUMODE_RECORD; mode != -1; 545 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 546 if ((setmode & mode) == 0) 547 continue; 548 549 p = mode == AUMODE_PLAY ? play : rec; 550 if (p == NULL) 551 continue; 552 553 if ((p->sample_rate != 8000) && 554 (p->sample_rate != 11025) && 555 (p->sample_rate != 12000) && 556 (p->sample_rate != 16000) && 557 (p->sample_rate != 22050) && 558 (p->sample_rate != 24000) && 559 (p->sample_rate != 32000) && 560 (p->sample_rate != 44100) && 561 (p->sample_rate != 48000)) 562 return (EINVAL); 563 564 fil = mode == AUMODE_PLAY ? pfil : rfil; 565 index = auconv_set_converter(sc->sc_formats, AUACER_NFORMATS, 566 mode, p, TRUE, fil); 567 if (index < 0) 568 return EINVAL; 569 if (fil->req_size > 0) 570 p = &fil->filters[0].param; 571 /* p points HW encoding */ 572 if (sc->sc_formats[index].frequency_type != 1 573 && auacer_set_rate(sc, mode, p->sample_rate)) 574 return EINVAL; 575 if (mode == AUMODE_PLAY) { 576 control = READ4(sc, ALI_SCR); 577 control &= ~ALI_SCR_PCM_246_MASK; 578 if (p->channels == 4) 579 control |= ALI_SCR_PCM_4; 580 else if (p->channels == 6) 581 control |= ALI_SCR_PCM_6; 582 WRITE4(sc, ALI_SCR, control); 583 } 584 } 585 586 return (0); 587 } 588 589 int 590 auacer_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 591 { 592 593 return blk & ~0x3f; /* keep good alignment */ 594 } 595 596 static void 597 auacer_halt(struct auacer_softc *sc, struct auacer_chan *chan) 598 { 599 uint32_t val; 600 uint8_t port; 601 uint32_t slot; 602 603 port = chan->port; 604 DPRINTF(ALI_DEBUG_API, ("auacer_halt: port=0x%x\n", port)); 605 chan->intr = 0; 606 607 slot = ALI_PORT2SLOT(port); 608 609 val = READ4(sc, ALI_DMACR); 610 val |= 1 << (slot+16); /* pause */ 611 val &= ~(1 << slot); /* no start */ 612 WRITE4(sc, ALI_DMACR, val); 613 WRITE1(sc, port + ALI_OFF_CR, 0); 614 while (READ1(sc, port + ALI_OFF_CR)) 615 ; 616 /* reset whole DMA things */ 617 WRITE1(sc, port + ALI_OFF_CR, ALI_CR_RR); 618 /* clear interrupts */ 619 WRITE1(sc, port + ALI_OFF_SR, READ1(sc, port+ALI_OFF_SR) | ALI_SR_W1TC); 620 WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(port)); 621 } 622 623 int 624 auacer_halt_output(void *v) 625 { 626 struct auacer_softc *sc; 627 628 DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_output\n")); 629 sc = v; 630 auacer_halt(sc, &sc->sc_pcmo); 631 632 return 0; 633 } 634 635 int 636 auacer_halt_input(void *v) 637 { 638 /*struct auacer_softc *sc = v;*/ 639 640 DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_input\n")); 641 642 return 0; 643 } 644 645 int 646 auacer_getdev(void *v, struct audio_device *adp) 647 { 648 struct auacer_softc *sc; 649 650 DPRINTF(ALI_DEBUG_API, ("auacer_getdev\n")); 651 sc = v; 652 *adp = sc->sc_audev; 653 return 0; 654 } 655 656 int 657 auacer_set_port(void *v, mixer_ctrl_t *cp) 658 { 659 struct auacer_softc *sc; 660 661 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_set_port\n")); 662 sc = v; 663 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 664 } 665 666 int 667 auacer_get_port(void *v, mixer_ctrl_t *cp) 668 { 669 struct auacer_softc *sc; 670 671 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_get_port\n")); 672 sc = v; 673 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 674 } 675 676 int 677 auacer_query_devinfo(void *v, mixer_devinfo_t *dp) 678 { 679 struct auacer_softc *sc; 680 681 DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_query_devinfo\n")); 682 sc = v; 683 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 684 } 685 686 void * 687 auacer_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 688 int flags) 689 { 690 struct auacer_softc *sc; 691 struct auacer_dma *p; 692 int error; 693 694 if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX)) 695 return NULL; 696 697 p = malloc(sizeof(*p), pool, flags | M_ZERO); 698 if (p == NULL) 699 return NULL; 700 sc = v; 701 error = auacer_allocmem(sc, size, 0, p); 702 if (error) { 703 free(p, pool); 704 return NULL; 705 } 706 707 p->next = sc->sc_dmas; 708 sc->sc_dmas = p; 709 710 return KERNADDR(p); 711 } 712 713 void 714 auacer_freem(void *v, void *ptr, struct malloc_type *pool) 715 { 716 struct auacer_softc *sc; 717 struct auacer_dma *p, **pp; 718 719 sc = v; 720 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 721 if (KERNADDR(p) == ptr) { 722 auacer_freemem(sc, p); 723 *pp = p->next; 724 free(p, pool); 725 return; 726 } 727 } 728 } 729 730 size_t 731 auacer_round_buffersize(void *v, int direction, size_t size) 732 { 733 734 if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX)) 735 size = ALI_DMALIST_MAX * ALI_DMASEG_MAX; 736 737 return size; 738 } 739 740 paddr_t 741 auacer_mappage(void *v, void *mem, off_t off, int prot) 742 { 743 struct auacer_softc *sc; 744 struct auacer_dma *p; 745 746 if (off < 0) 747 return -1; 748 sc = v; 749 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 750 continue; 751 if (p == NULL) 752 return -1; 753 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 754 off, prot, BUS_DMA_WAITOK); 755 } 756 757 int 758 auacer_get_props(void *v) 759 { 760 struct auacer_softc *sc; 761 int props; 762 763 sc = v; 764 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 765 /* 766 * Even if the codec is fixed-rate, set_param() succeeds for any sample 767 * rate because of aurateconv. Applications can't know what rate the 768 * device can process in the case of mmap(). 769 */ 770 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 771 props |= AUDIO_PROP_MMAP; 772 return props; 773 } 774 775 static void 776 auacer_add_entry(struct auacer_chan *chan) 777 { 778 struct auacer_dmalist *q; 779 780 q = &chan->dmalist[chan->ptr]; 781 782 DPRINTF(ALI_DEBUG_INTR, 783 ("auacer_add_entry: %p = %x @ 0x%x\n", 784 q, chan->blksize / 2, chan->p)); 785 786 q->base = htole32(chan->p); 787 q->len = htole32((chan->blksize / ALI_SAMPLE_SIZE) | ALI_DMAF_IOC); 788 chan->p += chan->blksize; 789 if (chan->p >= chan->end) 790 chan->p = chan->start; 791 792 if (++chan->ptr >= ALI_DMALIST_MAX) 793 chan->ptr = 0; 794 } 795 796 static void 797 auacer_upd_chan(struct auacer_softc *sc, struct auacer_chan *chan) 798 { 799 uint32_t sts; 800 uint32_t civ; 801 802 sts = READ2(sc, chan->port + ALI_OFF_SR); 803 /* intr ack */ 804 WRITE2(sc, chan->port + ALI_OFF_SR, sts & ALI_SR_W1TC); 805 WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(chan->port)); 806 807 DPRINTF(ALI_DEBUG_INTR, ("auacer_upd_chan: sts=0x%x\n", sts)); 808 809 if (sts & ALI_SR_DMA_INT_FIFO) { 810 printf("%s: fifo underrun # %u\n", 811 sc->sc_dev.dv_xname, ++chan->fifoe); 812 } 813 814 civ = READ1(sc, chan->port + ALI_OFF_CIV); 815 816 DPRINTF(ALI_DEBUG_INTR,("auacer_intr: civ=%u ptr=%u\n",civ,chan->ptr)); 817 818 /* XXX */ 819 while (chan->ptr != civ) { 820 auacer_add_entry(chan); 821 } 822 823 WRITE1(sc, chan->port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK); 824 825 while (chan->ack != civ) { 826 if (chan->intr) { 827 DPRINTF(ALI_DEBUG_INTR,("auacer_upd_chan: callback\n")); 828 chan->intr(chan->arg); 829 } 830 chan->ack++; 831 if (chan->ack >= ALI_DMALIST_MAX) 832 chan->ack = 0; 833 } 834 } 835 836 int 837 auacer_intr(void *v) 838 { 839 struct auacer_softc *sc; 840 int ret, intrs; 841 842 sc = v; 843 intrs = READ4(sc, ALI_INTERRUPTSR); 844 DPRINTF(ALI_DEBUG_INTR, ("auacer_intr: intrs=0x%x\n", intrs)); 845 846 ret = 0; 847 if (intrs & ALI_INT_PCMOUT) { 848 auacer_upd_chan(sc, &sc->sc_pcmo); 849 ret++; 850 } 851 852 return ret != 0; 853 } 854 855 static void 856 auacer_setup_chan(struct auacer_softc *sc, struct auacer_chan *chan, 857 uint32_t start, uint32_t size, uint32_t blksize, 858 void (*intr)(void *), void *arg) 859 { 860 uint32_t port, slot; 861 uint32_t offs, val; 862 863 chan->start = start; 864 chan->ptr = 0; 865 chan->p = chan->start; 866 chan->end = chan->start + size; 867 chan->blksize = blksize; 868 chan->ack = 0; 869 chan->intr = intr; 870 chan->arg = arg; 871 872 auacer_add_entry(chan); 873 auacer_add_entry(chan); 874 875 port = chan->port; 876 slot = ALI_PORT2SLOT(port); 877 878 WRITE1(sc, port + ALI_OFF_CIV, 0); 879 WRITE1(sc, port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK); 880 offs = (char *)chan->dmalist - (char *)sc->sc_cdata; 881 WRITE4(sc, port + ALI_OFF_BDBAR, sc->sc_cddma + offs); 882 WRITE1(sc, port + ALI_OFF_CR, 883 ALI_CR_IOCE | ALI_CR_FEIE | ALI_CR_LVBIE | ALI_CR_RPBM); 884 val = READ4(sc, ALI_DMACR); 885 val &= ~(1 << (slot+16)); /* no pause */ 886 val |= 1 << slot; /* start */ 887 WRITE4(sc, ALI_DMACR, val); 888 } 889 890 int 891 auacer_trigger_output(void *v, void *start, void *end, int blksize, 892 void (*intr)(void *), void *arg, const audio_params_t *param) 893 { 894 struct auacer_softc *sc; 895 struct auacer_dma *p; 896 uint32_t size; 897 898 DPRINTF(ALI_DEBUG_DMA, 899 ("auacer_trigger_output(%p, %p, %d, %p, %p, %p)\n", 900 start, end, blksize, intr, arg, param)); 901 sc = v; 902 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 903 continue; 904 if (!p) { 905 printf("auacer_trigger_output: bad addr %p\n", start); 906 return (EINVAL); 907 } 908 909 size = (char *)end - (char *)start; 910 auacer_setup_chan(sc, &sc->sc_pcmo, DMAADDR(p), size, blksize, 911 intr, arg); 912 913 return 0; 914 } 915 916 int 917 auacer_trigger_input(void *v, void *start, void *end, int blksize, 918 void (*intr)(void *), void *arg, 919 const audio_params_t *param) 920 { 921 return EINVAL; 922 } 923 924 int 925 auacer_allocmem(struct auacer_softc *sc, size_t size, size_t align, 926 struct auacer_dma *p) 927 { 928 int error; 929 930 p->size = size; 931 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 932 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 933 &p->nsegs, BUS_DMA_NOWAIT); 934 if (error) 935 return error; 936 937 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 938 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 939 if (error) 940 goto free; 941 942 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 943 0, BUS_DMA_NOWAIT, &p->map); 944 if (error) 945 goto unmap; 946 947 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 948 BUS_DMA_NOWAIT); 949 if (error) 950 goto destroy; 951 return (0); 952 953 destroy: 954 bus_dmamap_destroy(sc->dmat, p->map); 955 unmap: 956 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 957 free: 958 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 959 return error; 960 } 961 962 int 963 auacer_freemem(struct auacer_softc *sc, struct auacer_dma *p) 964 { 965 966 bus_dmamap_unload(sc->dmat, p->map); 967 bus_dmamap_destroy(sc->dmat, p->map); 968 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 969 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 970 return 0; 971 } 972 973 int 974 auacer_alloc_cdata(struct auacer_softc *sc) 975 { 976 bus_dma_segment_t seg; 977 int error, rseg; 978 979 /* 980 * Allocate the control data structure, and create and load the 981 * DMA map for it. 982 */ 983 if ((error = bus_dmamem_alloc(sc->dmat, 984 sizeof(struct auacer_cdata), 985 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 986 printf("%s: unable to allocate control data, error = %d\n", 987 sc->sc_dev.dv_xname, error); 988 goto fail_0; 989 } 990 991 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 992 sizeof(struct auacer_cdata), 993 (caddr_t *) &sc->sc_cdata, 994 sc->sc_dmamap_flags)) != 0) { 995 printf("%s: unable to map control data, error = %d\n", 996 sc->sc_dev.dv_xname, error); 997 goto fail_1; 998 } 999 1000 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auacer_cdata), 1, 1001 sizeof(struct auacer_cdata), 0, 0, 1002 &sc->sc_cddmamap)) != 0) { 1003 printf("%s: unable to create control data DMA map, " 1004 "error = %d\n", sc->sc_dev.dv_xname, error); 1005 goto fail_2; 1006 } 1007 1008 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1009 sc->sc_cdata, sizeof(struct auacer_cdata), 1010 NULL, 0)) != 0) { 1011 printf("%s: unable to load control data DMA map, " 1012 "error = %d\n", sc->sc_dev.dv_xname, error); 1013 goto fail_3; 1014 } 1015 1016 return 0; 1017 1018 fail_3: 1019 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1020 fail_2: 1021 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1022 sizeof(struct auacer_cdata)); 1023 fail_1: 1024 bus_dmamem_free(sc->dmat, &seg, rseg); 1025 fail_0: 1026 return error; 1027 } 1028 1029 void 1030 auacer_powerhook(int why, void *addr) 1031 { 1032 struct auacer_softc *sc; 1033 1034 sc = (struct auacer_softc *)addr; 1035 switch (why) { 1036 case PWR_SUSPEND: 1037 case PWR_STANDBY: 1038 /* Power down */ 1039 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1040 sc->sc_suspend = why; 1041 break; 1042 1043 case PWR_RESUME: 1044 /* Wake up */ 1045 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1046 if (sc->sc_suspend == PWR_RESUME) { 1047 printf("%s: resume without suspend.\n", 1048 sc->sc_dev.dv_xname); 1049 sc->sc_suspend = why; 1050 return; 1051 } 1052 sc->sc_suspend = why; 1053 auacer_reset_codec(sc); 1054 delay(1000); 1055 sc->codec_if->vtbl->restore_ports(sc->codec_if); 1056 break; 1057 1058 case PWR_SOFTSUSPEND: 1059 case PWR_SOFTSTANDBY: 1060 case PWR_SOFTRESUME: 1061 break; 1062 } 1063 } 1064
Indexes created Fri Oct 03 02:09:57 GMT 2025