auich.c revision 1.100
1 /* $NetBSD: auich.c,v 1.100 2005/12/02 19:47:52 xtraeme Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.100 2005/12/02 19:47:52 xtraeme Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 187 struct ac97_codec_if *codec_if; 188 struct ac97_host_if host_if; 189 int sc_codecnum; 190 int sc_codectype; 191 192 /* DMA scatter-gather lists. */ 193 bus_dmamap_t sc_cddmamap; 194 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 195 196 struct auich_cdata *sc_cdata; 197 198 struct auich_ring { 199 int qptr; 200 struct auich_dmalist *dmalist; 201 202 uint32_t start, p, end; 203 int blksize; 204 205 void (*intr)(void *); 206 void *arg; 207 } pcmo, pcmi, mici; 208 209 struct auich_dma *sc_dmas; 210 211 /* SiS 7012 hack */ 212 int sc_sample_shift; 213 int sc_sts_reg; 214 /* 440MX workaround */ 215 int sc_dmamap_flags; 216 217 /* Power Management */ 218 void *sc_powerhook; 219 int sc_suspend; 220 struct pci_conf_state sc_pciconf; 221 222 /* sysctl */ 223 struct sysctllog *sc_log; 224 uint32_t sc_ac97_clock; 225 int sc_ac97_clock_mib; 226 227 int sc_modem_offset; 228 229 #define AUICH_AUDIO_NFORMATS 3 230 #define AUICH_MODEM_NFORMATS 1 231 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 232 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 233 struct audio_encoding_set *sc_encodings; 234 }; 235 236 /* Debug */ 237 #ifdef AUICH_DEBUG 238 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 239 int auich_debug = 0xfffe; 240 #define ICH_DEBUG_CODECIO 0x0001 241 #define ICH_DEBUG_DMA 0x0002 242 #define ICH_DEBUG_INTR 0x0004 243 #else 244 #define DPRINTF(x,y) /* nothing */ 245 #endif 246 247 static int auich_match(struct device *, struct cfdata *, void *); 248 static void auich_attach(struct device *, struct device *, void *); 249 static int auich_detach(struct device *, int); 250 static int auich_activate(struct device *, enum devact); 251 static int auich_intr(void *); 252 253 CFATTACH_DECL(auich, sizeof(struct auich_softc), 254 auich_match, auich_attach, auich_detach, auich_activate); 255 256 static int auich_query_encoding(void *, struct audio_encoding *); 257 static int auich_set_params(void *, int, int, audio_params_t *, 258 audio_params_t *, stream_filter_list_t *, 259 stream_filter_list_t *); 260 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 261 static void auich_halt_pipe(struct auich_softc *, int); 262 static int auich_halt_output(void *); 263 static int auich_halt_input(void *); 264 static int auich_getdev(void *, struct audio_device *); 265 static int auich_set_port(void *, mixer_ctrl_t *); 266 static int auich_get_port(void *, mixer_ctrl_t *); 267 static int auich_query_devinfo(void *, mixer_devinfo_t *); 268 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 269 static void auich_freem(void *, void *, struct malloc_type *); 270 static size_t auich_round_buffersize(void *, int, size_t); 271 static paddr_t auich_mappage(void *, void *, off_t, int); 272 static int auich_get_props(void *); 273 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 274 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 275 static int auich_trigger_output(void *, void *, void *, int, 276 void (*)(void *), void *, const audio_params_t *); 277 static int auich_trigger_input(void *, void *, void *, int, 278 void (*)(void *), void *, const audio_params_t *); 279 280 static int auich_alloc_cdata(struct auich_softc *); 281 282 static int auich_allocmem(struct auich_softc *, size_t, size_t, 283 struct auich_dma *); 284 static int auich_freemem(struct auich_softc *, struct auich_dma *); 285 286 static void auich_powerhook(int, void *); 287 static int auich_set_rate(struct auich_softc *, int, u_long); 288 static int auich_sysctl_verify(SYSCTLFN_ARGS); 289 static void auich_finish_attach(struct device *); 290 static void auich_calibrate(struct auich_softc *); 291 static void auich_clear_cas(struct auich_softc *); 292 293 static int auich_attach_codec(void *, struct ac97_codec_if *); 294 static int auich_read_codec(void *, uint8_t, uint16_t *); 295 static int auich_write_codec(void *, uint8_t, uint16_t); 296 static int auich_reset_codec(void *); 297 298 static const struct audio_hw_if auich_hw_if = { 299 NULL, /* open */ 300 NULL, /* close */ 301 NULL, /* drain */ 302 auich_query_encoding, 303 auich_set_params, 304 auich_round_blocksize, 305 NULL, /* commit_setting */ 306 NULL, /* init_output */ 307 NULL, /* init_input */ 308 NULL, /* start_output */ 309 NULL, /* start_input */ 310 auich_halt_output, 311 auich_halt_input, 312 NULL, /* speaker_ctl */ 313 auich_getdev, 314 NULL, /* getfd */ 315 auich_set_port, 316 auich_get_port, 317 auich_query_devinfo, 318 auich_allocm, 319 auich_freem, 320 auich_round_buffersize, 321 auich_mappage, 322 auich_get_props, 323 auich_trigger_output, 324 auich_trigger_input, 325 NULL, /* dev_ioctl */ 326 }; 327 328 #define AUICH_FORMATS_1CH 0 329 #define AUICH_FORMATS_4CH 1 330 #define AUICH_FORMATS_6CH 2 331 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 332 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 333 2, AUFMT_STEREO, 0, {8000, 48000}}, 334 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 335 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 336 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 337 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 338 }; 339 340 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 341 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 342 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 343 }; 344 345 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 346 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 347 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 348 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 349 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 350 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 351 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 352 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 353 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 354 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 355 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 356 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 357 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 358 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 359 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 360 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 361 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 362 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 363 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 364 365 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 366 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 367 368 struct auich_devtype { 369 pcireg_t id; 370 const char *name; 371 const char *shortname; /* must be less than 11 characters */ 372 }; 373 374 static const struct auich_devtype auich_audio_devices[] = { 375 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 376 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 377 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 378 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 379 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 380 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 381 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 382 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 383 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 384 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 385 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 386 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 387 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 388 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 389 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 390 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 391 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 392 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 393 { 0, NULL, NULL }, 394 }; 395 396 static const struct auich_devtype auich_modem_devices[] = { 397 #ifdef AUICH_ATTACH_MODEM 398 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 399 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 400 #endif 401 { 0, NULL, NULL }, 402 }; 403 404 static const struct auich_devtype * 405 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 406 { 407 const struct auich_devtype *d; 408 409 for (d = auich_devices; d->name != NULL; d++) { 410 if (pa->pa_id == d->id) 411 return d; 412 } 413 414 return NULL; 415 } 416 417 static int 418 auich_match(struct device *parent, struct cfdata *match, void *aux) 419 { 420 struct pci_attach_args *pa; 421 422 pa = aux; 423 if (auich_lookup(pa, auich_audio_devices) != NULL) 424 return 1; 425 if (auich_lookup(pa, auich_modem_devices) != NULL) 426 return 1; 427 428 return 0; 429 } 430 431 static void 432 auich_attach(struct device *parent, struct device *self, void *aux) 433 { 434 struct auich_softc *sc; 435 struct pci_attach_args *pa; 436 pci_intr_handle_t ih; 437 pcireg_t v; 438 const char *intrstr; 439 const struct auich_devtype *d; 440 const struct sysctlnode *node, *node_ac97clock; 441 int err, node_mib, i; 442 443 sc = (struct auich_softc *)self; 444 pa = aux; 445 446 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 447 sc->sc_modem_offset = 0x10; 448 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 449 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 450 sc->sc_modem_offset = 0; 451 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 452 } else 453 panic("auich_attach: impossible"); 454 455 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 456 aprint_naive(": Audio controller\n"); 457 else 458 aprint_naive(": Modem controller\n"); 459 460 sc->sc_pc = pa->pa_pc; 461 sc->sc_pt = pa->pa_tag; 462 463 aprint_normal(": %s\n", d->name); 464 465 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 466 || d->id == PCIID_ICH7 || d->id == PCIID_ICH4MODEM) { 467 /* 468 * Use native mode for ICH4/ICH5/ICH6/ICH7 469 */ 470 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 471 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 472 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 473 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 474 v | ICH_CFG_IOSE); 475 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 476 0, &sc->iot, &sc->mix_ioh, NULL, 477 &sc->mix_size)) { 478 aprint_error("%s: can't map codec i/o space\n", 479 sc->sc_dev.dv_xname); 480 return; 481 } 482 } 483 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 484 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 485 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 486 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 487 v | ICH_CFG_IOSE); 488 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 489 0, &sc->iot, &sc->aud_ioh, NULL, 490 &sc->aud_size)) { 491 aprint_error("%s: can't map device i/o space\n", 492 sc->sc_dev.dv_xname); 493 return; 494 } 495 } 496 } else { 497 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 498 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 499 aprint_error("%s: can't map codec i/o space\n", 500 sc->sc_dev.dv_xname); 501 return; 502 } 503 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 504 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 505 aprint_error("%s: can't map device i/o space\n", 506 sc->sc_dev.dv_xname); 507 return; 508 } 509 } 510 sc->dmat = pa->pa_dmat; 511 512 /* enable bus mastering */ 513 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 514 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 515 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 516 517 /* Map and establish the interrupt. */ 518 if (pci_intr_map(pa, &ih)) { 519 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 520 return; 521 } 522 intrstr = pci_intr_string(pa->pa_pc, ih); 523 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 524 auich_intr, sc); 525 if (sc->sc_ih == NULL) { 526 aprint_error("%s: can't establish interrupt", 527 sc->sc_dev.dv_xname); 528 if (intrstr != NULL) 529 aprint_normal(" at %s", intrstr); 530 aprint_normal("\n"); 531 return; 532 } 533 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 534 535 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 536 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 537 "0x%02x", PCI_REVISION(pa->pa_class)); 538 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 539 540 /* SiS 7012 needs special handling */ 541 if (d->id == PCIID_SIS7012) { 542 sc->sc_sts_reg = ICH_PICB; 543 sc->sc_sample_shift = 0; 544 /* Un-mute output. From Linux. */ 545 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 546 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 547 ICH_SIS_CTL_UNMUTE); 548 } else { 549 sc->sc_sts_reg = ICH_STS; 550 sc->sc_sample_shift = 1; 551 } 552 553 /* Workaround for a 440MX B-stepping erratum */ 554 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 555 if (d->id == PCIID_440MX) { 556 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 557 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 558 } 559 560 /* Set up DMA lists. */ 561 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 562 auich_alloc_cdata(sc); 563 564 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 565 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 566 567 /* Modem codecs are always the secondary codec on ICH */ 568 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 569 570 sc->host_if.arg = sc; 571 sc->host_if.attach = auich_attach_codec; 572 sc->host_if.read = auich_read_codec; 573 sc->host_if.write = auich_write_codec; 574 sc->host_if.reset = auich_reset_codec; 575 576 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 577 return; 578 579 /* setup audio_format */ 580 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 581 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 582 if (!AC97_IS_4CH(sc->codec_if)) 583 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 584 if (!AC97_IS_6CH(sc->codec_if)) 585 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 586 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 587 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 588 sc->sc_audio_formats[i].frequency_type = 1; 589 sc->sc_audio_formats[i].frequency[0] = 48000; 590 } 591 } 592 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 593 &sc->sc_encodings)) 594 return; 595 } else { 596 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 597 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 598 &sc->sc_encodings)) 599 return; 600 } 601 602 603 /* Watch for power change */ 604 sc->sc_suspend = PWR_RESUME; 605 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 606 607 config_interrupts(self, auich_finish_attach); 608 609 /* sysctl setup */ 610 if (AC97_IS_FIXED_RATE(sc->codec_if) && 611 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 612 return; 613 614 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 615 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 616 CTL_HW, CTL_EOL); 617 if (err != 0) 618 goto sysctl_err; 619 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 620 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 621 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 622 if (err != 0) 623 goto sysctl_err; 624 node_mib = node->sysctl_num; 625 626 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 627 /* passing the sc address instead of &sc->sc_ac97_clock */ 628 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 629 CTLFLAG_READWRITE, 630 CTLTYPE_INT, "ac97rate", 631 SYSCTL_DESCR("AC'97 codec link rate"), 632 auich_sysctl_verify, 0, sc, 0, 633 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 634 if (err != 0) 635 goto sysctl_err; 636 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 637 } 638 639 return; 640 641 sysctl_err: 642 printf("%s: failed to add sysctl nodes. (%d)\n", 643 sc->sc_dev.dv_xname, err); 644 return; /* failure of sysctl is not fatal. */ 645 } 646 647 static int 648 auich_activate(struct device *self, enum devact act) 649 { 650 struct auich_softc *sc; 651 int ret; 652 653 sc = (struct auich_softc *)self; 654 ret = 0; 655 switch (act) { 656 case DVACT_ACTIVATE: 657 return EOPNOTSUPP; 658 case DVACT_DEACTIVATE: 659 if (sc->sc_audiodev != NULL) 660 ret = config_deactivate(sc->sc_audiodev); 661 return ret; 662 } 663 return EOPNOTSUPP; 664 } 665 666 static int 667 auich_detach(struct device *self, int flags) 668 { 669 struct auich_softc *sc; 670 671 sc = (struct auich_softc *)self; 672 673 /* audio */ 674 if (sc->sc_audiodev != NULL) 675 config_detach(sc->sc_audiodev, flags); 676 677 /* sysctl */ 678 sysctl_teardown(&sc->sc_log); 679 680 /* audio_encoding_set */ 681 auconv_delete_encodings(sc->sc_encodings); 682 683 /* ac97 */ 684 if (sc->codec_if != NULL) 685 sc->codec_if->vtbl->detach(sc->codec_if); 686 687 /* PCI */ 688 if (sc->sc_ih != NULL) 689 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 690 if (sc->mix_size != 0) 691 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 692 if (sc->aud_size != 0) 693 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 694 return 0; 695 } 696 697 static int 698 auich_sysctl_verify(SYSCTLFN_ARGS) 699 { 700 int error, tmp; 701 struct sysctlnode node; 702 struct auich_softc *sc; 703 704 node = *rnode; 705 sc = rnode->sysctl_data; 706 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 707 tmp = sc->sc_ac97_clock; 708 node.sysctl_data = &tmp; 709 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 710 if (error || newp == NULL) 711 return error; 712 713 if (tmp < 48000 || tmp > 96000) 714 return EINVAL; 715 sc->sc_ac97_clock = tmp; 716 } 717 718 return 0; 719 } 720 721 static void 722 auich_finish_attach(struct device *self) 723 { 724 struct auich_softc *sc; 725 726 sc = (void *)self; 727 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 728 auich_calibrate(sc); 729 730 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 731 } 732 733 #define ICH_CODECIO_INTERVAL 10 734 static int 735 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 736 { 737 struct auich_softc *sc; 738 int i; 739 uint32_t status; 740 741 sc = v; 742 /* wait for an access semaphore */ 743 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 744 bus_space_read_1(sc->iot, sc->aud_ioh, 745 ICH_CAS + sc->sc_modem_offset) & 1; 746 DELAY(ICH_CODECIO_INTERVAL)); 747 748 if (i > 0) { 749 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 750 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 751 DPRINTF(ICH_DEBUG_CODECIO, 752 ("auich_read_codec(%x, %x)\n", reg, *val)); 753 status = bus_space_read_4(sc->iot, sc->aud_ioh, 754 ICH_GSTS + sc->sc_modem_offset); 755 if (status & ICH_RCS) { 756 bus_space_write_4(sc->iot, sc->aud_ioh, 757 ICH_GSTS + sc->sc_modem_offset, 758 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 759 *val = 0xffff; 760 DPRINTF(ICH_DEBUG_CODECIO, 761 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 762 if (reg == AC97_REG_GPIO_STATUS) 763 auich_clear_cas(sc); 764 return -1; 765 } 766 if (reg == AC97_REG_GPIO_STATUS) 767 auich_clear_cas(sc); 768 return 0; 769 } else { 770 aprint_normal("%s: read_codec timeout\n", sc->sc_dev.dv_xname); 771 if (reg == AC97_REG_GPIO_STATUS) 772 auich_clear_cas(sc); 773 return -1; 774 } 775 } 776 777 static int 778 auich_write_codec(void *v, uint8_t reg, uint16_t val) 779 { 780 struct auich_softc *sc; 781 int i; 782 783 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 784 sc = v; 785 /* wait for an access semaphore */ 786 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 787 bus_space_read_1(sc->iot, sc->aud_ioh, 788 ICH_CAS + sc->sc_modem_offset) & 1; 789 DELAY(ICH_CODECIO_INTERVAL)); 790 791 if (i > 0) { 792 bus_space_write_2(sc->iot, sc->mix_ioh, 793 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 794 return 0; 795 } else { 796 aprint_normal("%s: write_codec timeout\n", sc->sc_dev.dv_xname); 797 return -1; 798 } 799 } 800 801 static int 802 auich_attach_codec(void *v, struct ac97_codec_if *cif) 803 { 804 struct auich_softc *sc; 805 806 sc = v; 807 sc->codec_if = cif; 808 809 return 0; 810 } 811 812 static int 813 auich_reset_codec(void *v) 814 { 815 struct auich_softc *sc; 816 int i; 817 uint32_t control, status; 818 819 sc = v; 820 control = bus_space_read_4(sc->iot, sc->aud_ioh, 821 ICH_GCTRL + sc->sc_modem_offset); 822 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 823 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 824 } else { 825 control &= ~ICH_ACLSO; 826 control |= ICH_GIE; 827 } 828 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 829 bus_space_write_4(sc->iot, sc->aud_ioh, 830 ICH_GCTRL + sc->sc_modem_offset, control); 831 832 for (i = 500000; i >= 0; i--) { 833 status = bus_space_read_4(sc->iot, sc->aud_ioh, 834 ICH_GSTS + sc->sc_modem_offset); 835 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 836 break; 837 DELAY(1); 838 } 839 if (i <= 0) { 840 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 841 return ETIMEDOUT; 842 } 843 #ifdef DEBUG 844 if (status & ICH_SCR) 845 printf("%s: The 2nd codec is ready.\n", 846 sc->sc_dev.dv_xname); 847 if (status & ICH_S2CR) 848 printf("%s: The 3rd codec is ready.\n", 849 sc->sc_dev.dv_xname); 850 #endif 851 return 0; 852 } 853 854 static int 855 auich_query_encoding(void *v, struct audio_encoding *aep) 856 { 857 struct auich_softc *sc; 858 859 sc = (struct auich_softc *)v; 860 return auconv_query_encoding(sc->sc_encodings, aep); 861 } 862 863 static int 864 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 865 { 866 int ret; 867 u_int ratetmp; 868 869 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 870 ratetmp = srate; 871 if (mode == AUMODE_RECORD) 872 return sc->codec_if->vtbl->set_rate(sc->codec_if, 873 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 874 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 875 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 876 if (ret) 877 return ret; 878 ratetmp = srate; 879 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 880 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 881 if (ret) 882 return ret; 883 ratetmp = srate; 884 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 885 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 886 return ret; 887 } 888 889 static int 890 auich_set_params(void *v, int setmode, int usemode, audio_params_t *play, 891 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 892 { 893 struct auich_softc *sc; 894 audio_params_t *p; 895 stream_filter_list_t *fil; 896 int mode, index; 897 uint32_t control; 898 899 sc = v; 900 for (mode = AUMODE_RECORD; mode != -1; 901 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 902 if ((setmode & mode) == 0) 903 continue; 904 905 p = mode == AUMODE_PLAY ? play : rec; 906 fil = mode == AUMODE_PLAY ? pfil : rfil; 907 if (p == NULL) 908 continue; 909 910 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 911 if (p->sample_rate < 8000 || 912 p->sample_rate > 48000) 913 return EINVAL; 914 915 index = auconv_set_converter(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 916 mode, p, TRUE, fil); 917 } else { 918 if (p->sample_rate != 8000 && p->sample_rate != 16000) 919 return EINVAL; 920 index = auconv_set_converter(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 921 mode, p, TRUE, fil); 922 } 923 if (index < 0) 924 return EINVAL; 925 if (fil->req_size > 0) 926 p = &fil->filters[0].param; 927 /* p represents HW encoding */ 928 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 929 if (sc->sc_audio_formats[index].frequency_type != 1 930 && auich_set_rate(sc, mode, p->sample_rate)) 931 return EINVAL; 932 } else { 933 if (sc->sc_modem_formats[index].frequency_type != 1 934 && auich_set_rate(sc, mode, p->sample_rate)) 935 return EINVAL; 936 auich_write_codec(sc, AC97_REG_LINE1_RATE, 937 p->sample_rate); 938 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 939 } 940 if (mode == AUMODE_PLAY && 941 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 942 control = bus_space_read_4(sc->iot, sc->aud_ioh, 943 ICH_GCTRL + sc->sc_modem_offset); 944 control &= ~ICH_PCM246_MASK; 945 if (p->channels == 4) { 946 control |= ICH_PCM4; 947 } else if (p->channels == 6) { 948 control |= ICH_PCM6; 949 } 950 bus_space_write_4(sc->iot, sc->aud_ioh, 951 ICH_GCTRL + sc->sc_modem_offset, control); 952 } 953 } 954 955 return 0; 956 } 957 958 static int 959 auich_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 960 { 961 962 return blk & ~0x3f; /* keep good alignment */ 963 } 964 965 static void 966 auich_halt_pipe(struct auich_softc *sc, int pipe) 967 { 968 int i; 969 uint32_t status; 970 971 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 972 for (i = 0; i < 100; i++) { 973 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 974 if (status & ICH_DCH) 975 break; 976 DELAY(1); 977 } 978 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 979 980 #if AUICH_DEBUG 981 if (i > 0) 982 printf("auich_halt_pipe: halt took %d cycles\n", i); 983 #endif 984 } 985 986 static int 987 auich_halt_output(void *v) 988 { 989 struct auich_softc *sc; 990 991 sc = v; 992 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 993 994 auich_halt_pipe(sc, ICH_PCMO); 995 sc->pcmo.intr = NULL; 996 997 return 0; 998 } 999 1000 static int 1001 auich_halt_input(void *v) 1002 { 1003 struct auich_softc *sc; 1004 1005 sc = v; 1006 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", sc->sc_dev.dv_xname)); 1007 1008 auich_halt_pipe(sc, ICH_PCMI); 1009 sc->pcmi.intr = NULL; 1010 1011 return 0; 1012 } 1013 1014 static int 1015 auich_getdev(void *v, struct audio_device *adp) 1016 { 1017 struct auich_softc *sc; 1018 1019 sc = v; 1020 *adp = sc->sc_audev; 1021 return 0; 1022 } 1023 1024 static int 1025 auich_set_port(void *v, mixer_ctrl_t *cp) 1026 { 1027 struct auich_softc *sc; 1028 1029 sc = v; 1030 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1031 } 1032 1033 static int 1034 auich_get_port(void *v, mixer_ctrl_t *cp) 1035 { 1036 struct auich_softc *sc; 1037 1038 sc = v; 1039 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1040 } 1041 1042 static int 1043 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1044 { 1045 struct auich_softc *sc; 1046 1047 sc = v; 1048 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1049 } 1050 1051 static void * 1052 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 1053 int flags) 1054 { 1055 struct auich_softc *sc; 1056 struct auich_dma *p; 1057 int error; 1058 1059 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1060 return NULL; 1061 1062 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1063 if (p == NULL) 1064 return NULL; 1065 1066 sc = v; 1067 error = auich_allocmem(sc, size, 0, p); 1068 if (error) { 1069 free(p, pool); 1070 return NULL; 1071 } 1072 1073 p->next = sc->sc_dmas; 1074 sc->sc_dmas = p; 1075 1076 return KERNADDR(p); 1077 } 1078 1079 static void 1080 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1081 { 1082 struct auich_softc *sc; 1083 struct auich_dma *p, **pp; 1084 1085 sc = v; 1086 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1087 if (KERNADDR(p) == ptr) { 1088 auich_freemem(sc, p); 1089 *pp = p->next; 1090 free(p, pool); 1091 return; 1092 } 1093 } 1094 } 1095 1096 static size_t 1097 auich_round_buffersize(void *v, int direction, size_t size) 1098 { 1099 1100 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1101 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1102 1103 return size; 1104 } 1105 1106 static paddr_t 1107 auich_mappage(void *v, void *mem, off_t off, int prot) 1108 { 1109 struct auich_softc *sc; 1110 struct auich_dma *p; 1111 1112 if (off < 0) 1113 return -1; 1114 sc = v; 1115 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1116 continue; 1117 if (!p) 1118 return -1; 1119 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1120 off, prot, BUS_DMA_WAITOK); 1121 } 1122 1123 static int 1124 auich_get_props(void *v) 1125 { 1126 struct auich_softc *sc; 1127 int props; 1128 1129 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1130 sc = v; 1131 /* 1132 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1133 * rate because of aurateconv. Applications can't know what rate the 1134 * device can process in the case of mmap(). 1135 */ 1136 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1137 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1138 props |= AUDIO_PROP_MMAP; 1139 return props; 1140 } 1141 1142 static int 1143 auich_intr(void *v) 1144 { 1145 struct auich_softc *sc; 1146 int ret, gsts; 1147 #ifdef DIAGNOSTIC 1148 int csts; 1149 #endif 1150 1151 sc = v; 1152 ret = 0; 1153 #ifdef DIAGNOSTIC 1154 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1155 if (csts & PCI_STATUS_MASTER_ABORT) { 1156 printf("auich_intr: PCI master abort\n"); 1157 } 1158 #endif 1159 1160 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1161 ICH_GSTS + sc->sc_modem_offset); 1162 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1163 1164 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1165 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1166 int sts; 1167 1168 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1169 ICH_PCMO + sc->sc_sts_reg); 1170 DPRINTF(ICH_DEBUG_INTR, 1171 ("auich_intr: osts=0x%x\n", sts)); 1172 1173 if (sts & ICH_FIFOE) 1174 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1175 1176 if (sts & ICH_BCIS) 1177 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1178 1179 /* int ack */ 1180 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1181 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1182 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1183 bus_space_write_4(sc->iot, sc->aud_ioh, 1184 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1185 else 1186 bus_space_write_4(sc->iot, sc->aud_ioh, 1187 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1188 ret++; 1189 } 1190 1191 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1192 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1193 int sts; 1194 1195 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1196 ICH_PCMI + sc->sc_sts_reg); 1197 DPRINTF(ICH_DEBUG_INTR, 1198 ("auich_intr: ists=0x%x\n", sts)); 1199 1200 if (sts & ICH_FIFOE) 1201 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1202 1203 if (sts & ICH_BCIS) 1204 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1205 1206 /* int ack */ 1207 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1208 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1209 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1210 bus_space_write_4(sc->iot, sc->aud_ioh, 1211 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1212 else 1213 bus_space_write_4(sc->iot, sc->aud_ioh, 1214 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1215 ret++; 1216 } 1217 1218 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1219 int sts; 1220 1221 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1222 ICH_MICI + sc->sc_sts_reg); 1223 DPRINTF(ICH_DEBUG_INTR, 1224 ("auich_intr: ists=0x%x\n", sts)); 1225 1226 if (sts & ICH_FIFOE) 1227 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1228 1229 if (sts & ICH_BCIS) 1230 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1231 1232 /* int ack */ 1233 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1234 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1235 bus_space_write_4(sc->iot, sc->aud_ioh, 1236 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1237 ret++; 1238 } 1239 1240 #ifdef AUICH_MODEM_DEBUG 1241 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1242 printf("%s: gsts=0x%x\n", sc->sc_dev.dv_xname, gsts); 1243 /* int ack */ 1244 bus_space_write_4(sc->iot, sc->aud_ioh, 1245 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1246 ret++; 1247 } 1248 #endif 1249 1250 return ret; 1251 } 1252 1253 static void 1254 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1255 { 1256 int blksize, qptr; 1257 struct auich_dmalist *q; 1258 1259 blksize = ring->blksize; 1260 1261 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1262 q = &ring->dmalist[qptr]; 1263 q->base = ring->p; 1264 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1265 1266 ring->p += blksize; 1267 if (ring->p >= ring->end) 1268 ring->p = ring->start; 1269 } 1270 ring->qptr = 0; 1271 1272 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1273 (qptr - 1) & ICH_LVI_MASK); 1274 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1275 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1276 } 1277 1278 static void 1279 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1280 { 1281 int blksize, qptr, nqptr; 1282 struct auich_dmalist *q; 1283 1284 blksize = ring->blksize; 1285 qptr = ring->qptr; 1286 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1287 1288 while (qptr != nqptr) { 1289 q = &ring->dmalist[qptr]; 1290 q->base = ring->p; 1291 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1292 1293 DPRINTF(ICH_DEBUG_INTR, 1294 ("auich_intr: %p, %p = %x @ 0x%x\n", 1295 &ring->dmalist[qptr], q, q->len, q->base)); 1296 1297 ring->p += blksize; 1298 if (ring->p >= ring->end) 1299 ring->p = ring->start; 1300 1301 qptr = (qptr + 1) & ICH_LVI_MASK; 1302 if (ring->intr) 1303 ring->intr(ring->arg); 1304 } 1305 ring->qptr = qptr; 1306 1307 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1308 (qptr - 1) & ICH_LVI_MASK); 1309 } 1310 1311 static int 1312 auich_trigger_output(void *v, void *start, void *end, int blksize, 1313 void (*intr)(void *), void *arg, const audio_params_t *param) 1314 { 1315 struct auich_softc *sc; 1316 struct auich_dma *p; 1317 size_t size; 1318 1319 DPRINTF(ICH_DEBUG_DMA, 1320 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1321 start, end, blksize, intr, arg, param)); 1322 sc = v; 1323 1324 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1325 continue; 1326 if (!p) { 1327 printf("auich_trigger_output: bad addr %p\n", start); 1328 return EINVAL; 1329 } 1330 1331 size = (size_t)((caddr_t)end - (caddr_t)start); 1332 1333 sc->pcmo.intr = intr; 1334 sc->pcmo.arg = arg; 1335 sc->pcmo.start = DMAADDR(p); 1336 sc->pcmo.p = sc->pcmo.start; 1337 sc->pcmo.end = sc->pcmo.start + size; 1338 sc->pcmo.blksize = blksize; 1339 1340 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1341 sc->sc_cddma + ICH_PCMO_OFF(0)); 1342 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1343 1344 return 0; 1345 } 1346 1347 static int 1348 auich_trigger_input(void *v, void *start, void *end, int blksize, 1349 void (*intr)(void *), void *arg, const audio_params_t *param) 1350 { 1351 struct auich_softc *sc; 1352 struct auich_dma *p; 1353 size_t size; 1354 1355 DPRINTF(ICH_DEBUG_DMA, 1356 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1357 start, end, blksize, intr, arg, param)); 1358 sc = v; 1359 1360 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1361 continue; 1362 if (!p) { 1363 printf("auich_trigger_input: bad addr %p\n", start); 1364 return EINVAL; 1365 } 1366 1367 size = (size_t)((caddr_t)end - (caddr_t)start); 1368 1369 sc->pcmi.intr = intr; 1370 sc->pcmi.arg = arg; 1371 sc->pcmi.start = DMAADDR(p); 1372 sc->pcmi.p = sc->pcmi.start; 1373 sc->pcmi.end = sc->pcmi.start + size; 1374 sc->pcmi.blksize = blksize; 1375 1376 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1377 sc->sc_cddma + ICH_PCMI_OFF(0)); 1378 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1379 1380 return 0; 1381 } 1382 1383 static int 1384 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1385 struct auich_dma *p) 1386 { 1387 int error; 1388 1389 p->size = size; 1390 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1391 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1392 &p->nsegs, BUS_DMA_NOWAIT); 1393 if (error) 1394 return error; 1395 1396 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1397 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1398 if (error) 1399 goto free; 1400 1401 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1402 0, BUS_DMA_NOWAIT, &p->map); 1403 if (error) 1404 goto unmap; 1405 1406 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1407 BUS_DMA_NOWAIT); 1408 if (error) 1409 goto destroy; 1410 return 0; 1411 1412 destroy: 1413 bus_dmamap_destroy(sc->dmat, p->map); 1414 unmap: 1415 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1416 free: 1417 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1418 return error; 1419 } 1420 1421 static int 1422 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1423 { 1424 1425 bus_dmamap_unload(sc->dmat, p->map); 1426 bus_dmamap_destroy(sc->dmat, p->map); 1427 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1428 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1429 return 0; 1430 } 1431 1432 static int 1433 auich_alloc_cdata(struct auich_softc *sc) 1434 { 1435 bus_dma_segment_t seg; 1436 int error, rseg; 1437 1438 /* 1439 * Allocate the control data structure, and create and load the 1440 * DMA map for it. 1441 */ 1442 if ((error = bus_dmamem_alloc(sc->dmat, 1443 sizeof(struct auich_cdata), 1444 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1445 printf("%s: unable to allocate control data, error = %d\n", 1446 sc->sc_dev.dv_xname, error); 1447 goto fail_0; 1448 } 1449 1450 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1451 sizeof(struct auich_cdata), 1452 (caddr_t *) &sc->sc_cdata, 1453 sc->sc_dmamap_flags)) != 0) { 1454 printf("%s: unable to map control data, error = %d\n", 1455 sc->sc_dev.dv_xname, error); 1456 goto fail_1; 1457 } 1458 1459 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1460 sizeof(struct auich_cdata), 0, 0, 1461 &sc->sc_cddmamap)) != 0) { 1462 printf("%s: unable to create control data DMA map, " 1463 "error = %d\n", sc->sc_dev.dv_xname, error); 1464 goto fail_2; 1465 } 1466 1467 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1468 sc->sc_cdata, sizeof(struct auich_cdata), 1469 NULL, 0)) != 0) { 1470 printf("%s: unable tp load control data DMA map, " 1471 "error = %d\n", sc->sc_dev.dv_xname, error); 1472 goto fail_3; 1473 } 1474 1475 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1476 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1477 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1478 1479 return 0; 1480 1481 fail_3: 1482 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1483 fail_2: 1484 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1485 sizeof(struct auich_cdata)); 1486 fail_1: 1487 bus_dmamem_free(sc->dmat, &seg, rseg); 1488 fail_0: 1489 return error; 1490 } 1491 1492 static void 1493 auich_powerhook(int why, void *addr) 1494 { 1495 struct auich_softc *sc; 1496 1497 sc = (struct auich_softc *)addr; 1498 switch (why) { 1499 case PWR_SUSPEND: 1500 case PWR_STANDBY: 1501 /* Power down */ 1502 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1503 sc->sc_suspend = why; 1504 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1505 break; 1506 1507 case PWR_RESUME: 1508 /* Wake up */ 1509 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1510 if (sc->sc_suspend == PWR_RESUME) { 1511 printf("%s: resume without suspend.\n", 1512 sc->sc_dev.dv_xname); 1513 sc->sc_suspend = why; 1514 return; 1515 } 1516 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1517 sc->sc_suspend = why; 1518 auich_reset_codec(sc); 1519 DELAY(1000); 1520 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1521 break; 1522 1523 case PWR_SOFTSUSPEND: 1524 case PWR_SOFTSTANDBY: 1525 case PWR_SOFTRESUME: 1526 break; 1527 } 1528 } 1529 1530 /* 1531 * Calibrate card (some boards are overclocked and need scaling) 1532 */ 1533 static void 1534 auich_calibrate(struct auich_softc *sc) 1535 { 1536 struct timeval t1, t2; 1537 uint8_t ociv, nciv; 1538 uint64_t wait_us; 1539 uint32_t actual_48k_rate, bytes, ac97rate; 1540 void *temp_buffer; 1541 struct auich_dma *p; 1542 u_int rate; 1543 1544 /* 1545 * Grab audio from input for fixed interval and compare how 1546 * much we actually get with what we expect. Interval needs 1547 * to be sufficiently short that no interrupts are 1548 * generated. 1549 */ 1550 1551 /* Force the codec to a known state first. */ 1552 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1553 rate = sc->sc_ac97_clock = 48000; 1554 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1555 &rate); 1556 1557 /* Setup a buffer */ 1558 bytes = 64000; 1559 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1560 1561 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1562 continue; 1563 if (p == NULL) { 1564 printf("auich_calibrate: bad address %p\n", temp_buffer); 1565 return; 1566 } 1567 sc->pcmi.dmalist[0].base = DMAADDR(p); 1568 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1569 1570 /* 1571 * our data format is stereo, 16 bit so each sample is 4 bytes. 1572 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1573 * we're going to start recording with interrupts disabled and measure 1574 * the time taken for one block to complete. we know the block size, 1575 * we know the time in microseconds, we calculate the sample rate: 1576 * 1577 * actual_rate [bps] = bytes / (time [s] * 4) 1578 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1579 * actual_rate [Hz] = (bytes * 250000) / time [us] 1580 */ 1581 1582 /* prepare */ 1583 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1584 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1585 sc->sc_cddma + ICH_PCMI_OFF(0)); 1586 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1587 (0 - 1) & ICH_LVI_MASK); 1588 1589 /* start */ 1590 microtime(&t1); 1591 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1592 1593 /* wait */ 1594 nciv = ociv; 1595 do { 1596 microtime(&t2); 1597 if (t2.tv_sec - t1.tv_sec > 1) 1598 break; 1599 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1600 ICH_PCMI + ICH_CIV); 1601 } while (nciv == ociv); 1602 microtime(&t2); 1603 1604 /* stop */ 1605 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1606 1607 /* reset */ 1608 DELAY(100); 1609 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1610 1611 /* turn time delta into us */ 1612 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1613 1614 auich_freem(sc, temp_buffer, M_DEVBUF); 1615 1616 if (nciv == ociv) { 1617 printf("%s: ac97 link rate calibration timed out after %" 1618 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1619 return; 1620 } 1621 1622 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1623 1624 if (actual_48k_rate < 50000) 1625 ac97rate = 48000; 1626 else 1627 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1628 1629 printf("%s: measured ac97 link rate at %d Hz", 1630 sc->sc_dev.dv_xname, actual_48k_rate); 1631 if (ac97rate != actual_48k_rate) 1632 printf(", will use %d Hz", ac97rate); 1633 printf("\n"); 1634 1635 sc->sc_ac97_clock = ac97rate; 1636 } 1637 1638 static void 1639 auich_clear_cas(struct auich_softc *sc) 1640 { 1641 /* Clear the codec access semaphore */ 1642 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1643 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1644 1645 return; 1646 } 1647
Indexes created Thu Oct 23 22:10:10 GMT 2025