auich.c revision 1.103
1 /* $NetBSD: auich.c,v 1.103 2006/03/07 23:16:20 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.103 2006/03/07 23:16:20 jmcneill Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 pci_intr_handle_t intrh; 187 188 struct ac97_codec_if *codec_if; 189 struct ac97_host_if host_if; 190 int sc_codecnum; 191 int sc_codectype; 192 193 /* DMA scatter-gather lists. */ 194 bus_dmamap_t sc_cddmamap; 195 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 196 197 struct auich_cdata *sc_cdata; 198 199 struct auich_ring { 200 int qptr; 201 struct auich_dmalist *dmalist; 202 203 uint32_t start, p, end; 204 int blksize; 205 206 void (*intr)(void *); 207 void *arg; 208 } pcmo, pcmi, mici; 209 210 struct auich_dma *sc_dmas; 211 212 /* SiS 7012 hack */ 213 int sc_sample_shift; 214 int sc_sts_reg; 215 /* 440MX workaround */ 216 int sc_dmamap_flags; 217 218 /* Power Management */ 219 void *sc_powerhook; 220 int sc_suspend; 221 int sc_powerstate; 222 struct pci_conf_state sc_pciconf; 223 224 /* sysctl */ 225 struct sysctllog *sc_log; 226 uint32_t sc_ac97_clock; 227 int sc_ac97_clock_mib; 228 229 int sc_modem_offset; 230 231 #define AUICH_AUDIO_NFORMATS 3 232 #define AUICH_MODEM_NFORMATS 1 233 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 234 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 235 struct audio_encoding_set *sc_encodings; 236 }; 237 238 /* Debug */ 239 #ifdef AUICH_DEBUG 240 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 241 int auich_debug = 0xfffe; 242 #define ICH_DEBUG_CODECIO 0x0001 243 #define ICH_DEBUG_DMA 0x0002 244 #define ICH_DEBUG_INTR 0x0004 245 #else 246 #define DPRINTF(x,y) /* nothing */ 247 #endif 248 249 static int auich_match(struct device *, struct cfdata *, void *); 250 static void auich_attach(struct device *, struct device *, void *); 251 static int auich_detach(struct device *, int); 252 static int auich_activate(struct device *, enum devact); 253 static int auich_intr(void *); 254 255 CFATTACH_DECL(auich, sizeof(struct auich_softc), 256 auich_match, auich_attach, auich_detach, auich_activate); 257 258 static int auich_query_encoding(void *, struct audio_encoding *); 259 static int auich_set_params(void *, int, int, audio_params_t *, 260 audio_params_t *, stream_filter_list_t *, 261 stream_filter_list_t *); 262 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 263 static void auich_halt_pipe(struct auich_softc *, int); 264 static int auich_halt_output(void *); 265 static int auich_halt_input(void *); 266 static int auich_getdev(void *, struct audio_device *); 267 static int auich_set_port(void *, mixer_ctrl_t *); 268 static int auich_get_port(void *, mixer_ctrl_t *); 269 static int auich_query_devinfo(void *, mixer_devinfo_t *); 270 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 271 static void auich_freem(void *, void *, struct malloc_type *); 272 static size_t auich_round_buffersize(void *, int, size_t); 273 static paddr_t auich_mappage(void *, void *, off_t, int); 274 static int auich_get_props(void *); 275 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 276 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 277 static int auich_trigger_output(void *, void *, void *, int, 278 void (*)(void *), void *, const audio_params_t *); 279 static int auich_trigger_input(void *, void *, void *, int, 280 void (*)(void *), void *, const audio_params_t *); 281 static int auich_powerstate(void *, int); 282 283 static int auich_alloc_cdata(struct auich_softc *); 284 285 static int auich_allocmem(struct auich_softc *, size_t, size_t, 286 struct auich_dma *); 287 static int auich_freemem(struct auich_softc *, struct auich_dma *); 288 289 static void auich_powerhook(int, void *); 290 static int auich_set_rate(struct auich_softc *, int, u_long); 291 static int auich_sysctl_verify(SYSCTLFN_ARGS); 292 static void auich_finish_attach(struct device *); 293 static void auich_calibrate(struct auich_softc *); 294 static void auich_clear_cas(struct auich_softc *); 295 296 static int auich_attach_codec(void *, struct ac97_codec_if *); 297 static int auich_read_codec(void *, uint8_t, uint16_t *); 298 static int auich_write_codec(void *, uint8_t, uint16_t); 299 static int auich_reset_codec(void *); 300 301 static const struct audio_hw_if auich_hw_if = { 302 NULL, /* open */ 303 NULL, /* close */ 304 NULL, /* drain */ 305 auich_query_encoding, 306 auich_set_params, 307 auich_round_blocksize, 308 NULL, /* commit_setting */ 309 NULL, /* init_output */ 310 NULL, /* init_input */ 311 NULL, /* start_output */ 312 NULL, /* start_input */ 313 auich_halt_output, 314 auich_halt_input, 315 NULL, /* speaker_ctl */ 316 auich_getdev, 317 NULL, /* getfd */ 318 auich_set_port, 319 auich_get_port, 320 auich_query_devinfo, 321 auich_allocm, 322 auich_freem, 323 auich_round_buffersize, 324 auich_mappage, 325 auich_get_props, 326 auich_trigger_output, 327 auich_trigger_input, 328 NULL, /* dev_ioctl */ 329 auich_powerstate, 330 }; 331 332 #define AUICH_FORMATS_1CH 0 333 #define AUICH_FORMATS_4CH 1 334 #define AUICH_FORMATS_6CH 2 335 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 336 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 337 2, AUFMT_STEREO, 0, {8000, 48000}}, 338 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 339 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 340 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 341 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 342 }; 343 344 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 345 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 346 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 347 }; 348 349 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 350 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 351 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 352 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 353 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 354 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 355 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 356 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 357 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 358 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 359 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 360 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 361 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 362 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 363 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 364 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 365 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 366 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 367 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 368 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 369 370 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 371 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 372 373 struct auich_devtype { 374 pcireg_t id; 375 const char *name; 376 const char *shortname; /* must be less than 11 characters */ 377 }; 378 379 static const struct auich_devtype auich_audio_devices[] = { 380 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 381 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 382 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 383 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 384 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 385 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 386 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 387 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 388 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 389 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 390 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 391 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 392 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 393 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 394 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 395 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 396 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 397 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 398 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 399 { 0, NULL, NULL }, 400 }; 401 402 static const struct auich_devtype auich_modem_devices[] = { 403 #ifdef AUICH_ATTACH_MODEM 404 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 405 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 406 #endif 407 { 0, NULL, NULL }, 408 }; 409 410 static const struct auich_devtype * 411 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 412 { 413 const struct auich_devtype *d; 414 415 for (d = auich_devices; d->name != NULL; d++) { 416 if (pa->pa_id == d->id) 417 return d; 418 } 419 420 return NULL; 421 } 422 423 static int 424 auich_match(struct device *parent, struct cfdata *match, void *aux) 425 { 426 struct pci_attach_args *pa; 427 428 pa = aux; 429 if (auich_lookup(pa, auich_audio_devices) != NULL) 430 return 1; 431 if (auich_lookup(pa, auich_modem_devices) != NULL) 432 return 1; 433 434 return 0; 435 } 436 437 static void 438 auich_attach(struct device *parent, struct device *self, void *aux) 439 { 440 struct auich_softc *sc; 441 struct pci_attach_args *pa; 442 pcireg_t v; 443 const char *intrstr; 444 const struct auich_devtype *d; 445 const struct sysctlnode *node, *node_ac97clock; 446 int err, node_mib, i; 447 448 sc = (struct auich_softc *)self; 449 pa = aux; 450 451 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 452 sc->sc_modem_offset = 0x10; 453 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 454 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 455 sc->sc_modem_offset = 0; 456 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 457 } else 458 panic("auich_attach: impossible"); 459 460 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 461 aprint_naive(": Audio controller\n"); 462 else 463 aprint_naive(": Modem controller\n"); 464 465 sc->sc_pc = pa->pa_pc; 466 sc->sc_pt = pa->pa_tag; 467 468 aprint_normal(": %s\n", d->name); 469 470 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 471 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 472 || d->id == PCIID_ICH4MODEM) { 473 /* 474 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 475 */ 476 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 477 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 478 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 479 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 480 v | ICH_CFG_IOSE); 481 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 482 0, &sc->iot, &sc->mix_ioh, NULL, 483 &sc->mix_size)) { 484 aprint_error("%s: can't map codec i/o space\n", 485 sc->sc_dev.dv_xname); 486 return; 487 } 488 } 489 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 490 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 491 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 492 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 493 v | ICH_CFG_IOSE); 494 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 495 0, &sc->iot, &sc->aud_ioh, NULL, 496 &sc->aud_size)) { 497 aprint_error("%s: can't map device i/o space\n", 498 sc->sc_dev.dv_xname); 499 return; 500 } 501 } 502 } else { 503 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 504 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 505 aprint_error("%s: can't map codec i/o space\n", 506 sc->sc_dev.dv_xname); 507 return; 508 } 509 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 510 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 511 aprint_error("%s: can't map device i/o space\n", 512 sc->sc_dev.dv_xname); 513 return; 514 } 515 } 516 sc->dmat = pa->pa_dmat; 517 518 /* enable bus mastering */ 519 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 520 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 521 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 522 523 /* Map and establish the interrupt. */ 524 if (pci_intr_map(pa, &sc->intrh)) { 525 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 526 return; 527 } 528 intrstr = pci_intr_string(pa->pa_pc, sc->intrh); 529 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO, 530 auich_intr, sc); 531 if (sc->sc_ih == NULL) { 532 aprint_error("%s: can't establish interrupt", 533 sc->sc_dev.dv_xname); 534 if (intrstr != NULL) 535 aprint_normal(" at %s", intrstr); 536 aprint_normal("\n"); 537 return; 538 } 539 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 540 541 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 542 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 543 "0x%02x", PCI_REVISION(pa->pa_class)); 544 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 545 546 /* SiS 7012 needs special handling */ 547 if (d->id == PCIID_SIS7012) { 548 sc->sc_sts_reg = ICH_PICB; 549 sc->sc_sample_shift = 0; 550 /* Un-mute output. From Linux. */ 551 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 552 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 553 ICH_SIS_CTL_UNMUTE); 554 } else { 555 sc->sc_sts_reg = ICH_STS; 556 sc->sc_sample_shift = 1; 557 } 558 559 /* Workaround for a 440MX B-stepping erratum */ 560 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 561 if (d->id == PCIID_440MX) { 562 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 563 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 564 } 565 566 /* Set up DMA lists. */ 567 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 568 auich_alloc_cdata(sc); 569 570 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 571 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 572 573 /* Modem codecs are always the secondary codec on ICH */ 574 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 575 576 sc->host_if.arg = sc; 577 sc->host_if.attach = auich_attach_codec; 578 sc->host_if.read = auich_read_codec; 579 sc->host_if.write = auich_write_codec; 580 sc->host_if.reset = auich_reset_codec; 581 582 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 583 return; 584 585 /* setup audio_format */ 586 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 587 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 588 if (!AC97_IS_4CH(sc->codec_if)) 589 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 590 if (!AC97_IS_6CH(sc->codec_if)) 591 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 592 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 593 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 594 sc->sc_audio_formats[i].frequency_type = 1; 595 sc->sc_audio_formats[i].frequency[0] = 48000; 596 } 597 } 598 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 599 &sc->sc_encodings)) 600 return; 601 } else { 602 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 603 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 604 &sc->sc_encodings)) 605 return; 606 } 607 608 609 /* Watch for power change */ 610 sc->sc_suspend = PWR_RESUME; 611 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 612 613 config_interrupts(self, auich_finish_attach); 614 615 /* sysctl setup */ 616 if (AC97_IS_FIXED_RATE(sc->codec_if) && 617 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 618 return; 619 620 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 621 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 622 CTL_HW, CTL_EOL); 623 if (err != 0) 624 goto sysctl_err; 625 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 626 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 627 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 628 if (err != 0) 629 goto sysctl_err; 630 node_mib = node->sysctl_num; 631 632 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 633 /* passing the sc address instead of &sc->sc_ac97_clock */ 634 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 635 CTLFLAG_READWRITE, 636 CTLTYPE_INT, "ac97rate", 637 SYSCTL_DESCR("AC'97 codec link rate"), 638 auich_sysctl_verify, 0, sc, 0, 639 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 640 if (err != 0) 641 goto sysctl_err; 642 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 643 } 644 645 return; 646 647 sysctl_err: 648 printf("%s: failed to add sysctl nodes. (%d)\n", 649 sc->sc_dev.dv_xname, err); 650 return; /* failure of sysctl is not fatal. */ 651 } 652 653 static int 654 auich_activate(struct device *self, enum devact act) 655 { 656 struct auich_softc *sc; 657 int ret; 658 659 sc = (struct auich_softc *)self; 660 ret = 0; 661 switch (act) { 662 case DVACT_ACTIVATE: 663 return EOPNOTSUPP; 664 case DVACT_DEACTIVATE: 665 if (sc->sc_audiodev != NULL) 666 ret = config_deactivate(sc->sc_audiodev); 667 return ret; 668 } 669 return EOPNOTSUPP; 670 } 671 672 static int 673 auich_detach(struct device *self, int flags) 674 { 675 struct auich_softc *sc; 676 677 sc = (struct auich_softc *)self; 678 679 /* audio */ 680 if (sc->sc_audiodev != NULL) 681 config_detach(sc->sc_audiodev, flags); 682 683 /* sysctl */ 684 sysctl_teardown(&sc->sc_log); 685 686 /* audio_encoding_set */ 687 auconv_delete_encodings(sc->sc_encodings); 688 689 /* ac97 */ 690 if (sc->codec_if != NULL) 691 sc->codec_if->vtbl->detach(sc->codec_if); 692 693 /* PCI */ 694 if (sc->sc_ih != NULL) 695 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 696 if (sc->mix_size != 0) 697 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 698 if (sc->aud_size != 0) 699 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 700 return 0; 701 } 702 703 static int 704 auich_sysctl_verify(SYSCTLFN_ARGS) 705 { 706 int error, tmp; 707 struct sysctlnode node; 708 struct auich_softc *sc; 709 710 node = *rnode; 711 sc = rnode->sysctl_data; 712 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 713 tmp = sc->sc_ac97_clock; 714 node.sysctl_data = &tmp; 715 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 716 if (error || newp == NULL) 717 return error; 718 719 if (tmp < 48000 || tmp > 96000) 720 return EINVAL; 721 sc->sc_ac97_clock = tmp; 722 } 723 724 return 0; 725 } 726 727 static void 728 auich_finish_attach(struct device *self) 729 { 730 struct auich_softc *sc; 731 732 sc = (void *)self; 733 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 734 auich_calibrate(sc); 735 736 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 737 738 auich_powerhook(PWR_SUSPEND, sc); 739 740 return; 741 } 742 743 #define ICH_CODECIO_INTERVAL 10 744 static int 745 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 746 { 747 struct auich_softc *sc; 748 int i; 749 uint32_t status; 750 751 sc = v; 752 /* wait for an access semaphore */ 753 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 754 bus_space_read_1(sc->iot, sc->aud_ioh, 755 ICH_CAS + sc->sc_modem_offset) & 1; 756 DELAY(ICH_CODECIO_INTERVAL)); 757 758 if (i > 0) { 759 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 760 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 761 DPRINTF(ICH_DEBUG_CODECIO, 762 ("auich_read_codec(%x, %x)\n", reg, *val)); 763 status = bus_space_read_4(sc->iot, sc->aud_ioh, 764 ICH_GSTS + sc->sc_modem_offset); 765 if (status & ICH_RCS) { 766 bus_space_write_4(sc->iot, sc->aud_ioh, 767 ICH_GSTS + sc->sc_modem_offset, 768 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 769 *val = 0xffff; 770 DPRINTF(ICH_DEBUG_CODECIO, 771 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 772 if (reg == AC97_REG_GPIO_STATUS) 773 auich_clear_cas(sc); 774 return -1; 775 } 776 if (reg == AC97_REG_GPIO_STATUS) 777 auich_clear_cas(sc); 778 return 0; 779 } else { 780 aprint_normal("%s: read_codec timeout\n", sc->sc_dev.dv_xname); 781 if (reg == AC97_REG_GPIO_STATUS) 782 auich_clear_cas(sc); 783 return -1; 784 } 785 } 786 787 static int 788 auich_write_codec(void *v, uint8_t reg, uint16_t val) 789 { 790 struct auich_softc *sc; 791 int i; 792 793 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 794 sc = v; 795 /* wait for an access semaphore */ 796 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 797 bus_space_read_1(sc->iot, sc->aud_ioh, 798 ICH_CAS + sc->sc_modem_offset) & 1; 799 DELAY(ICH_CODECIO_INTERVAL)); 800 801 if (i > 0) { 802 bus_space_write_2(sc->iot, sc->mix_ioh, 803 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 804 return 0; 805 } else { 806 aprint_normal("%s: write_codec timeout\n", sc->sc_dev.dv_xname); 807 return -1; 808 } 809 } 810 811 static int 812 auich_attach_codec(void *v, struct ac97_codec_if *cif) 813 { 814 struct auich_softc *sc; 815 816 sc = v; 817 sc->codec_if = cif; 818 819 return 0; 820 } 821 822 static int 823 auich_reset_codec(void *v) 824 { 825 struct auich_softc *sc; 826 int i; 827 uint32_t control, status; 828 829 sc = v; 830 control = bus_space_read_4(sc->iot, sc->aud_ioh, 831 ICH_GCTRL + sc->sc_modem_offset); 832 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 833 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 834 } else { 835 control &= ~ICH_ACLSO; 836 control |= ICH_GIE; 837 } 838 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 839 bus_space_write_4(sc->iot, sc->aud_ioh, 840 ICH_GCTRL + sc->sc_modem_offset, control); 841 842 for (i = 500000; i >= 0; i--) { 843 status = bus_space_read_4(sc->iot, sc->aud_ioh, 844 ICH_GSTS + sc->sc_modem_offset); 845 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 846 break; 847 DELAY(1); 848 } 849 if (i <= 0) { 850 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 851 return ETIMEDOUT; 852 } 853 #ifdef DEBUG 854 if (status & ICH_SCR) 855 printf("%s: The 2nd codec is ready.\n", 856 sc->sc_dev.dv_xname); 857 if (status & ICH_S2CR) 858 printf("%s: The 3rd codec is ready.\n", 859 sc->sc_dev.dv_xname); 860 #endif 861 return 0; 862 } 863 864 static int 865 auich_query_encoding(void *v, struct audio_encoding *aep) 866 { 867 struct auich_softc *sc; 868 869 sc = (struct auich_softc *)v; 870 return auconv_query_encoding(sc->sc_encodings, aep); 871 } 872 873 static int 874 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 875 { 876 int ret; 877 u_int ratetmp; 878 879 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 880 ratetmp = srate; 881 if (mode == AUMODE_RECORD) 882 return sc->codec_if->vtbl->set_rate(sc->codec_if, 883 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 884 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 885 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 886 if (ret) 887 return ret; 888 ratetmp = srate; 889 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 890 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 891 if (ret) 892 return ret; 893 ratetmp = srate; 894 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 895 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 896 return ret; 897 } 898 899 static int 900 auich_set_params(void *v, int setmode, int usemode, audio_params_t *play, 901 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 902 { 903 struct auich_softc *sc; 904 audio_params_t *p; 905 stream_filter_list_t *fil; 906 int mode, index; 907 uint32_t control; 908 909 sc = v; 910 for (mode = AUMODE_RECORD; mode != -1; 911 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 912 if ((setmode & mode) == 0) 913 continue; 914 915 p = mode == AUMODE_PLAY ? play : rec; 916 fil = mode == AUMODE_PLAY ? pfil : rfil; 917 if (p == NULL) 918 continue; 919 920 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 921 if (p->sample_rate < 8000 || 922 p->sample_rate > 48000) 923 return EINVAL; 924 925 index = auconv_set_converter(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 926 mode, p, TRUE, fil); 927 } else { 928 if (p->sample_rate != 8000 && p->sample_rate != 16000) 929 return EINVAL; 930 index = auconv_set_converter(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 931 mode, p, TRUE, fil); 932 } 933 if (index < 0) 934 return EINVAL; 935 if (fil->req_size > 0) 936 p = &fil->filters[0].param; 937 /* p represents HW encoding */ 938 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 939 if (sc->sc_audio_formats[index].frequency_type != 1 940 && auich_set_rate(sc, mode, p->sample_rate)) 941 return EINVAL; 942 } else { 943 if (sc->sc_modem_formats[index].frequency_type != 1 944 && auich_set_rate(sc, mode, p->sample_rate)) 945 return EINVAL; 946 auich_write_codec(sc, AC97_REG_LINE1_RATE, 947 p->sample_rate); 948 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 949 } 950 if (mode == AUMODE_PLAY && 951 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 952 control = bus_space_read_4(sc->iot, sc->aud_ioh, 953 ICH_GCTRL + sc->sc_modem_offset); 954 control &= ~ICH_PCM246_MASK; 955 if (p->channels == 4) { 956 control |= ICH_PCM4; 957 } else if (p->channels == 6) { 958 control |= ICH_PCM6; 959 } 960 bus_space_write_4(sc->iot, sc->aud_ioh, 961 ICH_GCTRL + sc->sc_modem_offset, control); 962 } 963 } 964 965 return 0; 966 } 967 968 static int 969 auich_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 970 { 971 972 return blk & ~0x3f; /* keep good alignment */ 973 } 974 975 static void 976 auich_halt_pipe(struct auich_softc *sc, int pipe) 977 { 978 int i; 979 uint32_t status; 980 981 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 982 for (i = 0; i < 100; i++) { 983 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 984 if (status & ICH_DCH) 985 break; 986 DELAY(1); 987 } 988 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 989 990 #if AUICH_DEBUG 991 if (i > 0) 992 printf("auich_halt_pipe: halt took %d cycles\n", i); 993 #endif 994 } 995 996 static int 997 auich_halt_output(void *v) 998 { 999 struct auich_softc *sc; 1000 1001 sc = v; 1002 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 1003 1004 auich_halt_pipe(sc, ICH_PCMO); 1005 sc->pcmo.intr = NULL; 1006 1007 return 0; 1008 } 1009 1010 static int 1011 auich_halt_input(void *v) 1012 { 1013 struct auich_softc *sc; 1014 1015 sc = v; 1016 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", sc->sc_dev.dv_xname)); 1017 1018 auich_halt_pipe(sc, ICH_PCMI); 1019 sc->pcmi.intr = NULL; 1020 1021 return 0; 1022 } 1023 1024 static int 1025 auich_getdev(void *v, struct audio_device *adp) 1026 { 1027 struct auich_softc *sc; 1028 1029 sc = v; 1030 *adp = sc->sc_audev; 1031 return 0; 1032 } 1033 1034 static int 1035 auich_set_port(void *v, mixer_ctrl_t *cp) 1036 { 1037 struct auich_softc *sc; 1038 1039 sc = v; 1040 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1041 } 1042 1043 static int 1044 auich_get_port(void *v, mixer_ctrl_t *cp) 1045 { 1046 struct auich_softc *sc; 1047 1048 sc = v; 1049 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1050 } 1051 1052 static int 1053 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1054 { 1055 struct auich_softc *sc; 1056 1057 sc = v; 1058 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1059 } 1060 1061 static void * 1062 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 1063 int flags) 1064 { 1065 struct auich_softc *sc; 1066 struct auich_dma *p; 1067 int error; 1068 1069 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1070 return NULL; 1071 1072 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1073 if (p == NULL) 1074 return NULL; 1075 1076 sc = v; 1077 error = auich_allocmem(sc, size, 0, p); 1078 if (error) { 1079 free(p, pool); 1080 return NULL; 1081 } 1082 1083 p->next = sc->sc_dmas; 1084 sc->sc_dmas = p; 1085 1086 return KERNADDR(p); 1087 } 1088 1089 static void 1090 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1091 { 1092 struct auich_softc *sc; 1093 struct auich_dma *p, **pp; 1094 1095 sc = v; 1096 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1097 if (KERNADDR(p) == ptr) { 1098 auich_freemem(sc, p); 1099 *pp = p->next; 1100 free(p, pool); 1101 return; 1102 } 1103 } 1104 } 1105 1106 static size_t 1107 auich_round_buffersize(void *v, int direction, size_t size) 1108 { 1109 1110 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1111 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1112 1113 return size; 1114 } 1115 1116 static paddr_t 1117 auich_mappage(void *v, void *mem, off_t off, int prot) 1118 { 1119 struct auich_softc *sc; 1120 struct auich_dma *p; 1121 1122 if (off < 0) 1123 return -1; 1124 sc = v; 1125 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1126 continue; 1127 if (!p) 1128 return -1; 1129 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1130 off, prot, BUS_DMA_WAITOK); 1131 } 1132 1133 static int 1134 auich_get_props(void *v) 1135 { 1136 struct auich_softc *sc; 1137 int props; 1138 1139 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1140 sc = v; 1141 /* 1142 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1143 * rate because of aurateconv. Applications can't know what rate the 1144 * device can process in the case of mmap(). 1145 */ 1146 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1147 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1148 props |= AUDIO_PROP_MMAP; 1149 return props; 1150 } 1151 1152 static int 1153 auich_intr(void *v) 1154 { 1155 struct auich_softc *sc; 1156 int ret, gsts; 1157 #ifdef DIAGNOSTIC 1158 int csts; 1159 #endif 1160 1161 sc = v; 1162 ret = 0; 1163 #ifdef DIAGNOSTIC 1164 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1165 if (csts & PCI_STATUS_MASTER_ABORT) { 1166 printf("auich_intr: PCI master abort\n"); 1167 } 1168 #endif 1169 1170 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1171 ICH_GSTS + sc->sc_modem_offset); 1172 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1173 1174 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1175 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1176 int sts; 1177 1178 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1179 ICH_PCMO + sc->sc_sts_reg); 1180 DPRINTF(ICH_DEBUG_INTR, 1181 ("auich_intr: osts=0x%x\n", sts)); 1182 1183 if (sts & ICH_FIFOE) 1184 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1185 1186 if (sts & ICH_BCIS) 1187 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1188 1189 /* int ack */ 1190 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1191 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1192 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1193 bus_space_write_4(sc->iot, sc->aud_ioh, 1194 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1195 else 1196 bus_space_write_4(sc->iot, sc->aud_ioh, 1197 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1198 ret++; 1199 } 1200 1201 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1202 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1203 int sts; 1204 1205 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1206 ICH_PCMI + sc->sc_sts_reg); 1207 DPRINTF(ICH_DEBUG_INTR, 1208 ("auich_intr: ists=0x%x\n", sts)); 1209 1210 if (sts & ICH_FIFOE) 1211 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1212 1213 if (sts & ICH_BCIS) 1214 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1215 1216 /* int ack */ 1217 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1218 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1219 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1220 bus_space_write_4(sc->iot, sc->aud_ioh, 1221 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1222 else 1223 bus_space_write_4(sc->iot, sc->aud_ioh, 1224 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1225 ret++; 1226 } 1227 1228 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1229 int sts; 1230 1231 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1232 ICH_MICI + sc->sc_sts_reg); 1233 DPRINTF(ICH_DEBUG_INTR, 1234 ("auich_intr: ists=0x%x\n", sts)); 1235 1236 if (sts & ICH_FIFOE) 1237 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1238 1239 if (sts & ICH_BCIS) 1240 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1241 1242 /* int ack */ 1243 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1244 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1245 bus_space_write_4(sc->iot, sc->aud_ioh, 1246 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1247 ret++; 1248 } 1249 1250 #ifdef AUICH_MODEM_DEBUG 1251 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1252 printf("%s: gsts=0x%x\n", sc->sc_dev.dv_xname, gsts); 1253 /* int ack */ 1254 bus_space_write_4(sc->iot, sc->aud_ioh, 1255 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1256 ret++; 1257 } 1258 #endif 1259 1260 return ret; 1261 } 1262 1263 static void 1264 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1265 { 1266 int blksize, qptr; 1267 struct auich_dmalist *q; 1268 1269 blksize = ring->blksize; 1270 1271 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1272 q = &ring->dmalist[qptr]; 1273 q->base = ring->p; 1274 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1275 1276 ring->p += blksize; 1277 if (ring->p >= ring->end) 1278 ring->p = ring->start; 1279 } 1280 ring->qptr = 0; 1281 1282 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1283 (qptr - 1) & ICH_LVI_MASK); 1284 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1285 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1286 } 1287 1288 static void 1289 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1290 { 1291 int blksize, qptr, nqptr; 1292 struct auich_dmalist *q; 1293 1294 blksize = ring->blksize; 1295 qptr = ring->qptr; 1296 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1297 1298 while (qptr != nqptr) { 1299 q = &ring->dmalist[qptr]; 1300 q->base = ring->p; 1301 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1302 1303 DPRINTF(ICH_DEBUG_INTR, 1304 ("auich_intr: %p, %p = %x @ 0x%x\n", 1305 &ring->dmalist[qptr], q, q->len, q->base)); 1306 1307 ring->p += blksize; 1308 if (ring->p >= ring->end) 1309 ring->p = ring->start; 1310 1311 qptr = (qptr + 1) & ICH_LVI_MASK; 1312 if (ring->intr) 1313 ring->intr(ring->arg); 1314 } 1315 ring->qptr = qptr; 1316 1317 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1318 (qptr - 1) & ICH_LVI_MASK); 1319 } 1320 1321 static int 1322 auich_trigger_output(void *v, void *start, void *end, int blksize, 1323 void (*intr)(void *), void *arg, const audio_params_t *param) 1324 { 1325 struct auich_softc *sc; 1326 struct auich_dma *p; 1327 size_t size; 1328 1329 DPRINTF(ICH_DEBUG_DMA, 1330 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1331 start, end, blksize, intr, arg, param)); 1332 sc = v; 1333 1334 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1335 continue; 1336 if (!p) { 1337 printf("auich_trigger_output: bad addr %p\n", start); 1338 return EINVAL; 1339 } 1340 1341 size = (size_t)((caddr_t)end - (caddr_t)start); 1342 1343 sc->pcmo.intr = intr; 1344 sc->pcmo.arg = arg; 1345 sc->pcmo.start = DMAADDR(p); 1346 sc->pcmo.p = sc->pcmo.start; 1347 sc->pcmo.end = sc->pcmo.start + size; 1348 sc->pcmo.blksize = blksize; 1349 1350 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1351 sc->sc_cddma + ICH_PCMO_OFF(0)); 1352 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1353 1354 return 0; 1355 } 1356 1357 static int 1358 auich_trigger_input(void *v, void *start, void *end, int blksize, 1359 void (*intr)(void *), void *arg, const audio_params_t *param) 1360 { 1361 struct auich_softc *sc; 1362 struct auich_dma *p; 1363 size_t size; 1364 1365 DPRINTF(ICH_DEBUG_DMA, 1366 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1367 start, end, blksize, intr, arg, param)); 1368 sc = v; 1369 1370 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1371 continue; 1372 if (!p) { 1373 printf("auich_trigger_input: bad addr %p\n", start); 1374 return EINVAL; 1375 } 1376 1377 size = (size_t)((caddr_t)end - (caddr_t)start); 1378 1379 sc->pcmi.intr = intr; 1380 sc->pcmi.arg = arg; 1381 sc->pcmi.start = DMAADDR(p); 1382 sc->pcmi.p = sc->pcmi.start; 1383 sc->pcmi.end = sc->pcmi.start + size; 1384 sc->pcmi.blksize = blksize; 1385 1386 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1387 sc->sc_cddma + ICH_PCMI_OFF(0)); 1388 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1389 1390 return 0; 1391 } 1392 1393 static int 1394 auich_powerstate(void *v, int state) 1395 { 1396 struct auich_softc *sc; 1397 int rv; 1398 1399 sc = (struct auich_softc *)v; 1400 rv = 0; 1401 1402 switch (state) { 1403 case AUDIOPOWER_OFF: 1404 auich_powerhook(PWR_SUSPEND, sc); 1405 break; 1406 case AUDIOPOWER_ON: 1407 auich_powerhook(PWR_RESUME, sc); 1408 break; 1409 default: 1410 aprint_error("%s: unknown power state %d\n", 1411 sc->sc_dev.dv_xname, state); 1412 rv = 1; 1413 break; 1414 } 1415 1416 return rv; 1417 } 1418 1419 static int 1420 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1421 struct auich_dma *p) 1422 { 1423 int error; 1424 1425 p->size = size; 1426 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1427 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1428 &p->nsegs, BUS_DMA_NOWAIT); 1429 if (error) 1430 return error; 1431 1432 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1433 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1434 if (error) 1435 goto free; 1436 1437 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1438 0, BUS_DMA_NOWAIT, &p->map); 1439 if (error) 1440 goto unmap; 1441 1442 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1443 BUS_DMA_NOWAIT); 1444 if (error) 1445 goto destroy; 1446 return 0; 1447 1448 destroy: 1449 bus_dmamap_destroy(sc->dmat, p->map); 1450 unmap: 1451 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1452 free: 1453 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1454 return error; 1455 } 1456 1457 static int 1458 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1459 { 1460 1461 bus_dmamap_unload(sc->dmat, p->map); 1462 bus_dmamap_destroy(sc->dmat, p->map); 1463 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1464 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1465 return 0; 1466 } 1467 1468 static int 1469 auich_alloc_cdata(struct auich_softc *sc) 1470 { 1471 bus_dma_segment_t seg; 1472 int error, rseg; 1473 1474 /* 1475 * Allocate the control data structure, and create and load the 1476 * DMA map for it. 1477 */ 1478 if ((error = bus_dmamem_alloc(sc->dmat, 1479 sizeof(struct auich_cdata), 1480 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1481 printf("%s: unable to allocate control data, error = %d\n", 1482 sc->sc_dev.dv_xname, error); 1483 goto fail_0; 1484 } 1485 1486 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1487 sizeof(struct auich_cdata), 1488 (caddr_t *) &sc->sc_cdata, 1489 sc->sc_dmamap_flags)) != 0) { 1490 printf("%s: unable to map control data, error = %d\n", 1491 sc->sc_dev.dv_xname, error); 1492 goto fail_1; 1493 } 1494 1495 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1496 sizeof(struct auich_cdata), 0, 0, 1497 &sc->sc_cddmamap)) != 0) { 1498 printf("%s: unable to create control data DMA map, " 1499 "error = %d\n", sc->sc_dev.dv_xname, error); 1500 goto fail_2; 1501 } 1502 1503 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1504 sc->sc_cdata, sizeof(struct auich_cdata), 1505 NULL, 0)) != 0) { 1506 printf("%s: unable tp load control data DMA map, " 1507 "error = %d\n", sc->sc_dev.dv_xname, error); 1508 goto fail_3; 1509 } 1510 1511 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1512 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1513 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1514 1515 return 0; 1516 1517 fail_3: 1518 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1519 fail_2: 1520 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1521 sizeof(struct auich_cdata)); 1522 fail_1: 1523 bus_dmamem_free(sc->dmat, &seg, rseg); 1524 fail_0: 1525 return error; 1526 } 1527 1528 static void 1529 auich_powerhook(int why, void *addr) 1530 { 1531 struct auich_softc *sc; 1532 const int d0 = PCI_PWR_D0; 1533 const int d3 = PCI_PWR_D3; 1534 int rv; 1535 1536 sc = (struct auich_softc *)addr; 1537 switch (why) { 1538 case PWR_SUSPEND: 1539 case PWR_STANDBY: 1540 /* Power down */ 1541 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1542 1543 /* if we're already asleep, don't try to sleep again */ 1544 if (sc->sc_suspend == PWR_SUSPEND || 1545 sc->sc_suspend == PWR_STANDBY) 1546 break; 1547 sc->sc_suspend = why; 1548 1549 DELAY(1000); 1550 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1551 1552 if (sc->sc_ih != NULL) 1553 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1554 1555 rv = pci_powerstate(sc->sc_pc, sc->sc_pt, &d3, &sc->sc_powerstate); 1556 if (rv) 1557 aprint_error("%s: unable to set power state (err=%d)\n", 1558 sc->sc_dev.dv_xname, rv); 1559 1560 break; 1561 1562 case PWR_RESUME: 1563 /* Wake up */ 1564 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1565 if (sc->sc_suspend == PWR_RESUME) { 1566 printf("%s: resume without suspend.\n", 1567 sc->sc_dev.dv_xname); 1568 sc->sc_suspend = why; 1569 return; 1570 } 1571 1572 rv = pci_powerstate(sc->sc_pc, sc->sc_pt, &d0, &sc->sc_powerstate); 1573 if (rv) 1574 aprint_error("%s: unable to set power state (err=%d)\n", 1575 sc->sc_dev.dv_xname, rv); 1576 1577 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 1578 auich_intr, sc); 1579 if (sc->sc_ih == NULL) { 1580 aprint_error("%s: can't establish interrupt", 1581 sc->sc_dev.dv_xname); 1582 /* XXX jmcneill what should we do here? */ 1583 return; 1584 } 1585 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1586 sc->sc_suspend = why; 1587 auich_reset_codec(sc); 1588 DELAY(1000); 1589 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1590 break; 1591 1592 case PWR_SOFTSUSPEND: 1593 case PWR_SOFTSTANDBY: 1594 case PWR_SOFTRESUME: 1595 break; 1596 } 1597 } 1598 1599 /* 1600 * Calibrate card (some boards are overclocked and need scaling) 1601 */ 1602 static void 1603 auich_calibrate(struct auich_softc *sc) 1604 { 1605 struct timeval t1, t2; 1606 uint8_t ociv, nciv; 1607 uint64_t wait_us; 1608 uint32_t actual_48k_rate, bytes, ac97rate; 1609 void *temp_buffer; 1610 struct auich_dma *p; 1611 u_int rate; 1612 1613 /* 1614 * Grab audio from input for fixed interval and compare how 1615 * much we actually get with what we expect. Interval needs 1616 * to be sufficiently short that no interrupts are 1617 * generated. 1618 */ 1619 1620 /* Force the codec to a known state first. */ 1621 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1622 rate = sc->sc_ac97_clock = 48000; 1623 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1624 &rate); 1625 1626 /* Setup a buffer */ 1627 bytes = 64000; 1628 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1629 1630 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1631 continue; 1632 if (p == NULL) { 1633 printf("auich_calibrate: bad address %p\n", temp_buffer); 1634 return; 1635 } 1636 sc->pcmi.dmalist[0].base = DMAADDR(p); 1637 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1638 1639 /* 1640 * our data format is stereo, 16 bit so each sample is 4 bytes. 1641 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1642 * we're going to start recording with interrupts disabled and measure 1643 * the time taken for one block to complete. we know the block size, 1644 * we know the time in microseconds, we calculate the sample rate: 1645 * 1646 * actual_rate [bps] = bytes / (time [s] * 4) 1647 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1648 * actual_rate [Hz] = (bytes * 250000) / time [us] 1649 */ 1650 1651 /* prepare */ 1652 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1653 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1654 sc->sc_cddma + ICH_PCMI_OFF(0)); 1655 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1656 (0 - 1) & ICH_LVI_MASK); 1657 1658 /* start */ 1659 microtime(&t1); 1660 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1661 1662 /* wait */ 1663 nciv = ociv; 1664 do { 1665 microtime(&t2); 1666 if (t2.tv_sec - t1.tv_sec > 1) 1667 break; 1668 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1669 ICH_PCMI + ICH_CIV); 1670 } while (nciv == ociv); 1671 microtime(&t2); 1672 1673 /* stop */ 1674 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1675 1676 /* reset */ 1677 DELAY(100); 1678 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1679 1680 /* turn time delta into us */ 1681 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1682 1683 auich_freem(sc, temp_buffer, M_DEVBUF); 1684 1685 if (nciv == ociv) { 1686 printf("%s: ac97 link rate calibration timed out after %" 1687 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1688 return; 1689 } 1690 1691 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1692 1693 if (actual_48k_rate < 50000) 1694 ac97rate = 48000; 1695 else 1696 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1697 1698 printf("%s: measured ac97 link rate at %d Hz", 1699 sc->sc_dev.dv_xname, actual_48k_rate); 1700 if (ac97rate != actual_48k_rate) 1701 printf(", will use %d Hz", ac97rate); 1702 printf("\n"); 1703 1704 sc->sc_ac97_clock = ac97rate; 1705 } 1706 1707 static void 1708 auich_clear_cas(struct auich_softc *sc) 1709 { 1710 /* Clear the codec access semaphore */ 1711 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1712 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1713 1714 return; 1715 } 1716
Indexes created Fri Sep 26 20:09:58 GMT 2025