auich.c revision 1.105
1 /* $NetBSD: auich.c,v 1.105 2006/04/16 07:40:00 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.105 2006/04/16 07:40:00 christos Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 pci_intr_handle_t intrh; 187 188 struct ac97_codec_if *codec_if; 189 struct ac97_host_if host_if; 190 int sc_codecnum; 191 int sc_codectype; 192 enum ac97_host_flags sc_codecflags; 193 194 /* DMA scatter-gather lists. */ 195 bus_dmamap_t sc_cddmamap; 196 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 197 198 struct auich_cdata *sc_cdata; 199 200 struct auich_ring { 201 int qptr; 202 struct auich_dmalist *dmalist; 203 204 uint32_t start, p, end; 205 int blksize; 206 207 void (*intr)(void *); 208 void *arg; 209 } pcmo, pcmi, mici; 210 211 struct auich_dma *sc_dmas; 212 213 /* SiS 7012 hack */ 214 int sc_sample_shift; 215 int sc_sts_reg; 216 /* 440MX workaround */ 217 int sc_dmamap_flags; 218 219 /* Power Management */ 220 void *sc_powerhook; 221 int sc_suspend; 222 int sc_powerstate; 223 struct pci_conf_state sc_pciconf; 224 225 /* sysctl */ 226 struct sysctllog *sc_log; 227 uint32_t sc_ac97_clock; 228 int sc_ac97_clock_mib; 229 230 int sc_modem_offset; 231 232 #define AUICH_AUDIO_NFORMATS 3 233 #define AUICH_MODEM_NFORMATS 1 234 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 235 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 236 struct audio_encoding_set *sc_encodings; 237 }; 238 239 /* Debug */ 240 #ifdef AUICH_DEBUG 241 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 242 int auich_debug = 0xfffe; 243 #define ICH_DEBUG_CODECIO 0x0001 244 #define ICH_DEBUG_DMA 0x0002 245 #define ICH_DEBUG_INTR 0x0004 246 #else 247 #define DPRINTF(x,y) /* nothing */ 248 #endif 249 250 static int auich_match(struct device *, struct cfdata *, void *); 251 static void auich_attach(struct device *, struct device *, void *); 252 static int auich_detach(struct device *, int); 253 static int auich_activate(struct device *, enum devact); 254 static int auich_intr(void *); 255 256 CFATTACH_DECL(auich, sizeof(struct auich_softc), 257 auich_match, auich_attach, auich_detach, auich_activate); 258 259 static int auich_query_encoding(void *, struct audio_encoding *); 260 static int auich_set_params(void *, int, int, audio_params_t *, 261 audio_params_t *, stream_filter_list_t *, 262 stream_filter_list_t *); 263 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 264 static void auich_halt_pipe(struct auich_softc *, int); 265 static int auich_halt_output(void *); 266 static int auich_halt_input(void *); 267 static int auich_getdev(void *, struct audio_device *); 268 static int auich_set_port(void *, mixer_ctrl_t *); 269 static int auich_get_port(void *, mixer_ctrl_t *); 270 static int auich_query_devinfo(void *, mixer_devinfo_t *); 271 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 272 static void auich_freem(void *, void *, struct malloc_type *); 273 static size_t auich_round_buffersize(void *, int, size_t); 274 static paddr_t auich_mappage(void *, void *, off_t, int); 275 static int auich_get_props(void *); 276 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 277 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 278 static int auich_trigger_output(void *, void *, void *, int, 279 void (*)(void *), void *, const audio_params_t *); 280 static int auich_trigger_input(void *, void *, void *, int, 281 void (*)(void *), void *, const audio_params_t *); 282 static int auich_powerstate(void *, int); 283 284 static int auich_alloc_cdata(struct auich_softc *); 285 286 static int auich_allocmem(struct auich_softc *, size_t, size_t, 287 struct auich_dma *); 288 static int auich_freemem(struct auich_softc *, struct auich_dma *); 289 290 static void auich_powerhook(int, void *); 291 static int auich_set_rate(struct auich_softc *, int, u_long); 292 static int auich_sysctl_verify(SYSCTLFN_ARGS); 293 static void auich_finish_attach(struct device *); 294 static void auich_calibrate(struct auich_softc *); 295 static void auich_clear_cas(struct auich_softc *); 296 297 static int auich_attach_codec(void *, struct ac97_codec_if *); 298 static int auich_read_codec(void *, uint8_t, uint16_t *); 299 static int auich_write_codec(void *, uint8_t, uint16_t); 300 static int auich_reset_codec(void *); 301 static enum ac97_host_flags auich_flags_codec(void *); 302 303 static const struct audio_hw_if auich_hw_if = { 304 NULL, /* open */ 305 NULL, /* close */ 306 NULL, /* drain */ 307 auich_query_encoding, 308 auich_set_params, 309 auich_round_blocksize, 310 NULL, /* commit_setting */ 311 NULL, /* init_output */ 312 NULL, /* init_input */ 313 NULL, /* start_output */ 314 NULL, /* start_input */ 315 auich_halt_output, 316 auich_halt_input, 317 NULL, /* speaker_ctl */ 318 auich_getdev, 319 NULL, /* getfd */ 320 auich_set_port, 321 auich_get_port, 322 auich_query_devinfo, 323 auich_allocm, 324 auich_freem, 325 auich_round_buffersize, 326 auich_mappage, 327 auich_get_props, 328 auich_trigger_output, 329 auich_trigger_input, 330 NULL, /* dev_ioctl */ 331 auich_powerstate, 332 }; 333 334 #define AUICH_FORMATS_1CH 0 335 #define AUICH_FORMATS_4CH 1 336 #define AUICH_FORMATS_6CH 2 337 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 338 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 339 2, AUFMT_STEREO, 0, {8000, 48000}}, 340 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 341 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 342 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 343 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 344 }; 345 346 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 347 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 348 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 349 }; 350 351 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 352 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 353 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 354 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 355 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 356 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 357 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 358 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 359 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 360 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 361 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 362 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 363 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 364 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 365 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 366 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 367 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 368 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 369 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 370 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 371 372 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 373 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 374 375 struct auich_devtype { 376 pcireg_t id; 377 const char *name; 378 const char *shortname; /* must be less than 11 characters */ 379 }; 380 381 static const struct auich_devtype auich_audio_devices[] = { 382 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 383 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 384 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 385 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 386 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 387 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 388 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 389 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 390 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 391 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 392 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 393 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 394 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 395 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 396 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 397 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 398 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 399 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 400 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 401 { 0, NULL, NULL }, 402 }; 403 404 static const struct auich_devtype auich_modem_devices[] = { 405 #ifdef AUICH_ATTACH_MODEM 406 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 407 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 408 #endif 409 { 0, NULL, NULL }, 410 }; 411 412 static const struct auich_devtype * 413 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 414 { 415 const struct auich_devtype *d; 416 417 for (d = auich_devices; d->name != NULL; d++) { 418 if (pa->pa_id == d->id) 419 return d; 420 } 421 422 return NULL; 423 } 424 425 static int 426 auich_match(struct device *parent, struct cfdata *match, void *aux) 427 { 428 struct pci_attach_args *pa; 429 430 pa = aux; 431 if (auich_lookup(pa, auich_audio_devices) != NULL) 432 return 1; 433 if (auich_lookup(pa, auich_modem_devices) != NULL) 434 return 1; 435 436 return 0; 437 } 438 439 static void 440 auich_attach(struct device *parent, struct device *self, void *aux) 441 { 442 struct auich_softc *sc; 443 struct pci_attach_args *pa; 444 pcireg_t v, subdev; 445 const char *intrstr; 446 const struct auich_devtype *d; 447 const struct sysctlnode *node, *node_ac97clock; 448 int err, node_mib, i; 449 450 sc = (struct auich_softc *)self; 451 pa = aux; 452 453 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 454 sc->sc_modem_offset = 0x10; 455 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 456 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 457 sc->sc_modem_offset = 0; 458 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 459 } else 460 panic("auich_attach: impossible"); 461 462 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 463 aprint_naive(": Audio controller\n"); 464 else 465 aprint_naive(": Modem controller\n"); 466 467 sc->sc_pc = pa->pa_pc; 468 sc->sc_pt = pa->pa_tag; 469 470 aprint_normal(": %s\n", d->name); 471 472 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 473 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 474 || d->id == PCIID_ICH4MODEM) { 475 /* 476 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 477 */ 478 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 479 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 480 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 481 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 482 v | ICH_CFG_IOSE); 483 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 484 0, &sc->iot, &sc->mix_ioh, NULL, 485 &sc->mix_size)) { 486 aprint_error("%s: can't map codec i/o space\n", 487 sc->sc_dev.dv_xname); 488 return; 489 } 490 } 491 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 492 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 493 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 494 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 495 v | ICH_CFG_IOSE); 496 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 497 0, &sc->iot, &sc->aud_ioh, NULL, 498 &sc->aud_size)) { 499 aprint_error("%s: can't map device i/o space\n", 500 sc->sc_dev.dv_xname); 501 return; 502 } 503 } 504 } else { 505 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 506 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 507 aprint_error("%s: can't map codec i/o space\n", 508 sc->sc_dev.dv_xname); 509 return; 510 } 511 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 512 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 513 aprint_error("%s: can't map device i/o space\n", 514 sc->sc_dev.dv_xname); 515 return; 516 } 517 } 518 sc->dmat = pa->pa_dmat; 519 520 /* enable bus mastering */ 521 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 522 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 523 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 524 525 /* Map and establish the interrupt. */ 526 if (pci_intr_map(pa, &sc->intrh)) { 527 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 528 return; 529 } 530 intrstr = pci_intr_string(pa->pa_pc, sc->intrh); 531 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO, 532 auich_intr, sc); 533 if (sc->sc_ih == NULL) { 534 aprint_error("%s: can't establish interrupt", 535 sc->sc_dev.dv_xname); 536 if (intrstr != NULL) 537 aprint_normal(" at %s", intrstr); 538 aprint_normal("\n"); 539 return; 540 } 541 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 542 543 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 544 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 545 "0x%02x", PCI_REVISION(pa->pa_class)); 546 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 547 548 /* SiS 7012 needs special handling */ 549 if (d->id == PCIID_SIS7012) { 550 sc->sc_sts_reg = ICH_PICB; 551 sc->sc_sample_shift = 0; 552 /* Un-mute output. From Linux. */ 553 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 554 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 555 ICH_SIS_CTL_UNMUTE); 556 } else { 557 sc->sc_sts_reg = ICH_STS; 558 sc->sc_sample_shift = 1; 559 } 560 561 /* Workaround for a 440MX B-stepping erratum */ 562 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 563 if (d->id == PCIID_440MX) { 564 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 565 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 566 } 567 568 /* Set up DMA lists. */ 569 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 570 auich_alloc_cdata(sc); 571 572 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 573 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 574 575 /* Modem codecs are always the secondary codec on ICH */ 576 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 577 578 sc->host_if.arg = sc; 579 sc->host_if.attach = auich_attach_codec; 580 sc->host_if.read = auich_read_codec; 581 sc->host_if.write = auich_write_codec; 582 sc->host_if.reset = auich_reset_codec; 583 sc->host_if.flags = auich_flags_codec; 584 585 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 586 switch (subdev) { 587 case 0x202f161f: /* Gateway 7326GZ */ 588 case 0x203a161f: /* Gateway 4028GZ */ 589 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 590 case 0x8144104d: /* Sony VAIO PCG-TR* */ 591 case 0x81c0104d: /* Sony VAIO type T */ 592 case 0x8197104d: /* Sony S1XP */ 593 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP; 594 break; 595 default: 596 sc->sc_codecflags = 0; 597 break; 598 } 599 600 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 601 return; 602 603 /* setup audio_format */ 604 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 605 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 606 if (!AC97_IS_4CH(sc->codec_if)) 607 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 608 if (!AC97_IS_6CH(sc->codec_if)) 609 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 610 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 611 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 612 sc->sc_audio_formats[i].frequency_type = 1; 613 sc->sc_audio_formats[i].frequency[0] = 48000; 614 } 615 } 616 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 617 &sc->sc_encodings)) 618 return; 619 } else { 620 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 621 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 622 &sc->sc_encodings)) 623 return; 624 } 625 626 627 /* Watch for power change */ 628 sc->sc_suspend = PWR_RESUME; 629 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 630 631 config_interrupts(self, auich_finish_attach); 632 633 /* sysctl setup */ 634 if (AC97_IS_FIXED_RATE(sc->codec_if) && 635 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 636 return; 637 638 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 639 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 640 CTL_HW, CTL_EOL); 641 if (err != 0) 642 goto sysctl_err; 643 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 644 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 645 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 646 if (err != 0) 647 goto sysctl_err; 648 node_mib = node->sysctl_num; 649 650 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 651 /* passing the sc address instead of &sc->sc_ac97_clock */ 652 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 653 CTLFLAG_READWRITE, 654 CTLTYPE_INT, "ac97rate", 655 SYSCTL_DESCR("AC'97 codec link rate"), 656 auich_sysctl_verify, 0, sc, 0, 657 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 658 if (err != 0) 659 goto sysctl_err; 660 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 661 } 662 663 return; 664 665 sysctl_err: 666 printf("%s: failed to add sysctl nodes. (%d)\n", 667 sc->sc_dev.dv_xname, err); 668 return; /* failure of sysctl is not fatal. */ 669 } 670 671 static int 672 auich_activate(struct device *self, enum devact act) 673 { 674 struct auich_softc *sc; 675 int ret; 676 677 sc = (struct auich_softc *)self; 678 ret = 0; 679 switch (act) { 680 case DVACT_ACTIVATE: 681 return EOPNOTSUPP; 682 case DVACT_DEACTIVATE: 683 if (sc->sc_audiodev != NULL) 684 ret = config_deactivate(sc->sc_audiodev); 685 return ret; 686 } 687 return EOPNOTSUPP; 688 } 689 690 static int 691 auich_detach(struct device *self, int flags) 692 { 693 struct auich_softc *sc; 694 695 sc = (struct auich_softc *)self; 696 697 /* audio */ 698 if (sc->sc_audiodev != NULL) 699 config_detach(sc->sc_audiodev, flags); 700 701 /* sysctl */ 702 sysctl_teardown(&sc->sc_log); 703 704 /* audio_encoding_set */ 705 auconv_delete_encodings(sc->sc_encodings); 706 707 /* ac97 */ 708 if (sc->codec_if != NULL) 709 sc->codec_if->vtbl->detach(sc->codec_if); 710 711 /* PCI */ 712 if (sc->sc_ih != NULL) 713 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 714 if (sc->mix_size != 0) 715 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 716 if (sc->aud_size != 0) 717 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 718 return 0; 719 } 720 721 static int 722 auich_sysctl_verify(SYSCTLFN_ARGS) 723 { 724 int error, tmp; 725 struct sysctlnode node; 726 struct auich_softc *sc; 727 728 node = *rnode; 729 sc = rnode->sysctl_data; 730 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 731 tmp = sc->sc_ac97_clock; 732 node.sysctl_data = &tmp; 733 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 734 if (error || newp == NULL) 735 return error; 736 737 if (tmp < 48000 || tmp > 96000) 738 return EINVAL; 739 sc->sc_ac97_clock = tmp; 740 } 741 742 return 0; 743 } 744 745 static void 746 auich_finish_attach(struct device *self) 747 { 748 struct auich_softc *sc; 749 750 sc = (void *)self; 751 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 752 auich_calibrate(sc); 753 754 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 755 756 auich_powerhook(PWR_SUSPEND, sc); 757 758 return; 759 } 760 761 #define ICH_CODECIO_INTERVAL 10 762 static int 763 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 764 { 765 struct auich_softc *sc; 766 int i; 767 uint32_t status; 768 769 sc = v; 770 /* wait for an access semaphore */ 771 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 772 bus_space_read_1(sc->iot, sc->aud_ioh, 773 ICH_CAS + sc->sc_modem_offset) & 1; 774 DELAY(ICH_CODECIO_INTERVAL)); 775 776 if (i > 0) { 777 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 778 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 779 DPRINTF(ICH_DEBUG_CODECIO, 780 ("auich_read_codec(%x, %x)\n", reg, *val)); 781 status = bus_space_read_4(sc->iot, sc->aud_ioh, 782 ICH_GSTS + sc->sc_modem_offset); 783 if (status & ICH_RCS) { 784 bus_space_write_4(sc->iot, sc->aud_ioh, 785 ICH_GSTS + sc->sc_modem_offset, 786 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 787 *val = 0xffff; 788 DPRINTF(ICH_DEBUG_CODECIO, 789 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 790 if (reg == AC97_REG_GPIO_STATUS) 791 auich_clear_cas(sc); 792 return -1; 793 } 794 if (reg == AC97_REG_GPIO_STATUS) 795 auich_clear_cas(sc); 796 return 0; 797 } else { 798 aprint_normal("%s: read_codec timeout\n", sc->sc_dev.dv_xname); 799 if (reg == AC97_REG_GPIO_STATUS) 800 auich_clear_cas(sc); 801 return -1; 802 } 803 } 804 805 static int 806 auich_write_codec(void *v, uint8_t reg, uint16_t val) 807 { 808 struct auich_softc *sc; 809 int i; 810 811 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 812 sc = v; 813 /* wait for an access semaphore */ 814 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 815 bus_space_read_1(sc->iot, sc->aud_ioh, 816 ICH_CAS + sc->sc_modem_offset) & 1; 817 DELAY(ICH_CODECIO_INTERVAL)); 818 819 if (i > 0) { 820 bus_space_write_2(sc->iot, sc->mix_ioh, 821 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 822 return 0; 823 } else { 824 aprint_normal("%s: write_codec timeout\n", sc->sc_dev.dv_xname); 825 return -1; 826 } 827 } 828 829 static int 830 auich_attach_codec(void *v, struct ac97_codec_if *cif) 831 { 832 struct auich_softc *sc; 833 834 sc = v; 835 sc->codec_if = cif; 836 837 return 0; 838 } 839 840 static int 841 auich_reset_codec(void *v) 842 { 843 struct auich_softc *sc; 844 int i; 845 uint32_t control, status; 846 847 sc = v; 848 control = bus_space_read_4(sc->iot, sc->aud_ioh, 849 ICH_GCTRL + sc->sc_modem_offset); 850 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 851 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 852 } else { 853 control &= ~ICH_ACLSO; 854 control |= ICH_GIE; 855 } 856 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 857 bus_space_write_4(sc->iot, sc->aud_ioh, 858 ICH_GCTRL + sc->sc_modem_offset, control); 859 860 for (i = 500000; i >= 0; i--) { 861 status = bus_space_read_4(sc->iot, sc->aud_ioh, 862 ICH_GSTS + sc->sc_modem_offset); 863 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 864 break; 865 DELAY(1); 866 } 867 if (i <= 0) { 868 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 869 return ETIMEDOUT; 870 } 871 #ifdef AUICH_DEBUG 872 if (status & ICH_SCR) 873 printf("%s: The 2nd codec is ready.\n", 874 sc->sc_dev.dv_xname); 875 if (status & ICH_S2CR) 876 printf("%s: The 3rd codec is ready.\n", 877 sc->sc_dev.dv_xname); 878 #endif 879 return 0; 880 } 881 882 static enum ac97_host_flags 883 auich_flags_codec(void *v) 884 { 885 struct auich_softc *sc = v; 886 return sc->sc_codecflags; 887 } 888 889 static int 890 auich_query_encoding(void *v, struct audio_encoding *aep) 891 { 892 struct auich_softc *sc; 893 894 sc = (struct auich_softc *)v; 895 return auconv_query_encoding(sc->sc_encodings, aep); 896 } 897 898 static int 899 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 900 { 901 int ret; 902 u_int ratetmp; 903 904 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 905 ratetmp = srate; 906 if (mode == AUMODE_RECORD) 907 return sc->codec_if->vtbl->set_rate(sc->codec_if, 908 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 909 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 910 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 911 if (ret) 912 return ret; 913 ratetmp = srate; 914 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 915 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 916 if (ret) 917 return ret; 918 ratetmp = srate; 919 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 920 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 921 return ret; 922 } 923 924 static int 925 auich_set_params(void *v, int setmode, int usemode, audio_params_t *play, 926 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 927 { 928 struct auich_softc *sc; 929 audio_params_t *p; 930 stream_filter_list_t *fil; 931 int mode, index; 932 uint32_t control; 933 934 sc = v; 935 for (mode = AUMODE_RECORD; mode != -1; 936 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 937 if ((setmode & mode) == 0) 938 continue; 939 940 p = mode == AUMODE_PLAY ? play : rec; 941 fil = mode == AUMODE_PLAY ? pfil : rfil; 942 if (p == NULL) 943 continue; 944 945 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 946 if (p->sample_rate < 8000 || 947 p->sample_rate > 48000) 948 return EINVAL; 949 950 index = auconv_set_converter(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 951 mode, p, TRUE, fil); 952 } else { 953 if (p->sample_rate != 8000 && p->sample_rate != 16000) 954 return EINVAL; 955 index = auconv_set_converter(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 956 mode, p, TRUE, fil); 957 } 958 if (index < 0) 959 return EINVAL; 960 if (fil->req_size > 0) 961 p = &fil->filters[0].param; 962 /* p represents HW encoding */ 963 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 964 if (sc->sc_audio_formats[index].frequency_type != 1 965 && auich_set_rate(sc, mode, p->sample_rate)) 966 return EINVAL; 967 } else { 968 if (sc->sc_modem_formats[index].frequency_type != 1 969 && auich_set_rate(sc, mode, p->sample_rate)) 970 return EINVAL; 971 auich_write_codec(sc, AC97_REG_LINE1_RATE, 972 p->sample_rate); 973 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 974 } 975 if (mode == AUMODE_PLAY && 976 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 977 control = bus_space_read_4(sc->iot, sc->aud_ioh, 978 ICH_GCTRL + sc->sc_modem_offset); 979 control &= ~ICH_PCM246_MASK; 980 if (p->channels == 4) { 981 control |= ICH_PCM4; 982 } else if (p->channels == 6) { 983 control |= ICH_PCM6; 984 } 985 bus_space_write_4(sc->iot, sc->aud_ioh, 986 ICH_GCTRL + sc->sc_modem_offset, control); 987 } 988 } 989 990 return 0; 991 } 992 993 static int 994 auich_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 995 { 996 997 return blk & ~0x3f; /* keep good alignment */ 998 } 999 1000 static void 1001 auich_halt_pipe(struct auich_softc *sc, int pipe) 1002 { 1003 int i; 1004 uint32_t status; 1005 1006 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 1007 for (i = 0; i < 100; i++) { 1008 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 1009 if (status & ICH_DCH) 1010 break; 1011 DELAY(1); 1012 } 1013 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 1014 1015 #if AUICH_DEBUG 1016 if (i > 0) 1017 printf("auich_halt_pipe: halt took %d cycles\n", i); 1018 #endif 1019 } 1020 1021 static int 1022 auich_halt_output(void *v) 1023 { 1024 struct auich_softc *sc; 1025 1026 sc = v; 1027 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 1028 1029 auich_halt_pipe(sc, ICH_PCMO); 1030 sc->pcmo.intr = NULL; 1031 1032 return 0; 1033 } 1034 1035 static int 1036 auich_halt_input(void *v) 1037 { 1038 struct auich_softc *sc; 1039 1040 sc = v; 1041 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", sc->sc_dev.dv_xname)); 1042 1043 auich_halt_pipe(sc, ICH_PCMI); 1044 sc->pcmi.intr = NULL; 1045 1046 return 0; 1047 } 1048 1049 static int 1050 auich_getdev(void *v, struct audio_device *adp) 1051 { 1052 struct auich_softc *sc; 1053 1054 sc = v; 1055 *adp = sc->sc_audev; 1056 return 0; 1057 } 1058 1059 static int 1060 auich_set_port(void *v, mixer_ctrl_t *cp) 1061 { 1062 struct auich_softc *sc; 1063 1064 sc = v; 1065 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1066 } 1067 1068 static int 1069 auich_get_port(void *v, mixer_ctrl_t *cp) 1070 { 1071 struct auich_softc *sc; 1072 1073 sc = v; 1074 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1075 } 1076 1077 static int 1078 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1079 { 1080 struct auich_softc *sc; 1081 1082 sc = v; 1083 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1084 } 1085 1086 static void * 1087 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 1088 int flags) 1089 { 1090 struct auich_softc *sc; 1091 struct auich_dma *p; 1092 int error; 1093 1094 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1095 return NULL; 1096 1097 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1098 if (p == NULL) 1099 return NULL; 1100 1101 sc = v; 1102 error = auich_allocmem(sc, size, 0, p); 1103 if (error) { 1104 free(p, pool); 1105 return NULL; 1106 } 1107 1108 p->next = sc->sc_dmas; 1109 sc->sc_dmas = p; 1110 1111 return KERNADDR(p); 1112 } 1113 1114 static void 1115 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1116 { 1117 struct auich_softc *sc; 1118 struct auich_dma *p, **pp; 1119 1120 sc = v; 1121 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1122 if (KERNADDR(p) == ptr) { 1123 auich_freemem(sc, p); 1124 *pp = p->next; 1125 free(p, pool); 1126 return; 1127 } 1128 } 1129 } 1130 1131 static size_t 1132 auich_round_buffersize(void *v, int direction, size_t size) 1133 { 1134 1135 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1136 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1137 1138 return size; 1139 } 1140 1141 static paddr_t 1142 auich_mappage(void *v, void *mem, off_t off, int prot) 1143 { 1144 struct auich_softc *sc; 1145 struct auich_dma *p; 1146 1147 if (off < 0) 1148 return -1; 1149 sc = v; 1150 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1151 continue; 1152 if (!p) 1153 return -1; 1154 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1155 off, prot, BUS_DMA_WAITOK); 1156 } 1157 1158 static int 1159 auich_get_props(void *v) 1160 { 1161 struct auich_softc *sc; 1162 int props; 1163 1164 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1165 sc = v; 1166 /* 1167 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1168 * rate because of aurateconv. Applications can't know what rate the 1169 * device can process in the case of mmap(). 1170 */ 1171 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1172 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1173 props |= AUDIO_PROP_MMAP; 1174 return props; 1175 } 1176 1177 static int 1178 auich_intr(void *v) 1179 { 1180 struct auich_softc *sc; 1181 int ret, gsts; 1182 #ifdef DIAGNOSTIC 1183 int csts; 1184 #endif 1185 1186 sc = v; 1187 ret = 0; 1188 #ifdef DIAGNOSTIC 1189 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1190 if (csts & PCI_STATUS_MASTER_ABORT) { 1191 printf("auich_intr: PCI master abort\n"); 1192 } 1193 #endif 1194 1195 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1196 ICH_GSTS + sc->sc_modem_offset); 1197 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1198 1199 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1200 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1201 int sts; 1202 1203 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1204 ICH_PCMO + sc->sc_sts_reg); 1205 DPRINTF(ICH_DEBUG_INTR, 1206 ("auich_intr: osts=0x%x\n", sts)); 1207 1208 if (sts & ICH_FIFOE) 1209 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1210 1211 if (sts & ICH_BCIS) 1212 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1213 1214 /* int ack */ 1215 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1216 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1217 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1218 bus_space_write_4(sc->iot, sc->aud_ioh, 1219 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1220 else 1221 bus_space_write_4(sc->iot, sc->aud_ioh, 1222 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1223 ret++; 1224 } 1225 1226 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1227 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1228 int sts; 1229 1230 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1231 ICH_PCMI + sc->sc_sts_reg); 1232 DPRINTF(ICH_DEBUG_INTR, 1233 ("auich_intr: ists=0x%x\n", sts)); 1234 1235 if (sts & ICH_FIFOE) 1236 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1237 1238 if (sts & ICH_BCIS) 1239 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1240 1241 /* int ack */ 1242 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1243 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1244 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1245 bus_space_write_4(sc->iot, sc->aud_ioh, 1246 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1247 else 1248 bus_space_write_4(sc->iot, sc->aud_ioh, 1249 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1250 ret++; 1251 } 1252 1253 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1254 int sts; 1255 1256 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1257 ICH_MICI + sc->sc_sts_reg); 1258 DPRINTF(ICH_DEBUG_INTR, 1259 ("auich_intr: ists=0x%x\n", sts)); 1260 1261 if (sts & ICH_FIFOE) 1262 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1263 1264 if (sts & ICH_BCIS) 1265 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1266 1267 /* int ack */ 1268 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1269 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1270 bus_space_write_4(sc->iot, sc->aud_ioh, 1271 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1272 ret++; 1273 } 1274 1275 #ifdef AUICH_MODEM_DEBUG 1276 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1277 printf("%s: gsts=0x%x\n", sc->sc_dev.dv_xname, gsts); 1278 /* int ack */ 1279 bus_space_write_4(sc->iot, sc->aud_ioh, 1280 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1281 ret++; 1282 } 1283 #endif 1284 1285 return ret; 1286 } 1287 1288 static void 1289 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1290 { 1291 int blksize, qptr; 1292 struct auich_dmalist *q; 1293 1294 blksize = ring->blksize; 1295 1296 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1297 q = &ring->dmalist[qptr]; 1298 q->base = ring->p; 1299 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1300 1301 ring->p += blksize; 1302 if (ring->p >= ring->end) 1303 ring->p = ring->start; 1304 } 1305 ring->qptr = 0; 1306 1307 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1308 (qptr - 1) & ICH_LVI_MASK); 1309 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1310 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1311 } 1312 1313 static void 1314 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1315 { 1316 int blksize, qptr, nqptr; 1317 struct auich_dmalist *q; 1318 1319 blksize = ring->blksize; 1320 qptr = ring->qptr; 1321 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1322 1323 while (qptr != nqptr) { 1324 q = &ring->dmalist[qptr]; 1325 q->base = ring->p; 1326 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1327 1328 DPRINTF(ICH_DEBUG_INTR, 1329 ("auich_intr: %p, %p = %x @ 0x%x\n", 1330 &ring->dmalist[qptr], q, q->len, q->base)); 1331 1332 ring->p += blksize; 1333 if (ring->p >= ring->end) 1334 ring->p = ring->start; 1335 1336 qptr = (qptr + 1) & ICH_LVI_MASK; 1337 if (ring->intr) 1338 ring->intr(ring->arg); 1339 } 1340 ring->qptr = qptr; 1341 1342 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1343 (qptr - 1) & ICH_LVI_MASK); 1344 } 1345 1346 static int 1347 auich_trigger_output(void *v, void *start, void *end, int blksize, 1348 void (*intr)(void *), void *arg, const audio_params_t *param) 1349 { 1350 struct auich_softc *sc; 1351 struct auich_dma *p; 1352 size_t size; 1353 1354 DPRINTF(ICH_DEBUG_DMA, 1355 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1356 start, end, blksize, intr, arg, param)); 1357 sc = v; 1358 1359 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1360 continue; 1361 if (!p) { 1362 printf("auich_trigger_output: bad addr %p\n", start); 1363 return EINVAL; 1364 } 1365 1366 size = (size_t)((caddr_t)end - (caddr_t)start); 1367 1368 sc->pcmo.intr = intr; 1369 sc->pcmo.arg = arg; 1370 sc->pcmo.start = DMAADDR(p); 1371 sc->pcmo.p = sc->pcmo.start; 1372 sc->pcmo.end = sc->pcmo.start + size; 1373 sc->pcmo.blksize = blksize; 1374 1375 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1376 sc->sc_cddma + ICH_PCMO_OFF(0)); 1377 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1378 1379 return 0; 1380 } 1381 1382 static int 1383 auich_trigger_input(void *v, void *start, void *end, int blksize, 1384 void (*intr)(void *), void *arg, const audio_params_t *param) 1385 { 1386 struct auich_softc *sc; 1387 struct auich_dma *p; 1388 size_t size; 1389 1390 DPRINTF(ICH_DEBUG_DMA, 1391 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1392 start, end, blksize, intr, arg, param)); 1393 sc = v; 1394 1395 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1396 continue; 1397 if (!p) { 1398 printf("auich_trigger_input: bad addr %p\n", start); 1399 return EINVAL; 1400 } 1401 1402 size = (size_t)((caddr_t)end - (caddr_t)start); 1403 1404 sc->pcmi.intr = intr; 1405 sc->pcmi.arg = arg; 1406 sc->pcmi.start = DMAADDR(p); 1407 sc->pcmi.p = sc->pcmi.start; 1408 sc->pcmi.end = sc->pcmi.start + size; 1409 sc->pcmi.blksize = blksize; 1410 1411 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1412 sc->sc_cddma + ICH_PCMI_OFF(0)); 1413 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1414 1415 return 0; 1416 } 1417 1418 static int 1419 auich_powerstate(void *v, int state) 1420 { 1421 struct auich_softc *sc; 1422 int rv; 1423 1424 sc = (struct auich_softc *)v; 1425 rv = 0; 1426 1427 switch (state) { 1428 case AUDIOPOWER_OFF: 1429 auich_powerhook(PWR_SUSPEND, sc); 1430 break; 1431 case AUDIOPOWER_ON: 1432 auich_powerhook(PWR_RESUME, sc); 1433 break; 1434 default: 1435 aprint_error("%s: unknown power state %d\n", 1436 sc->sc_dev.dv_xname, state); 1437 rv = 1; 1438 break; 1439 } 1440 1441 return rv; 1442 } 1443 1444 static int 1445 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1446 struct auich_dma *p) 1447 { 1448 int error; 1449 1450 p->size = size; 1451 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1452 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1453 &p->nsegs, BUS_DMA_NOWAIT); 1454 if (error) 1455 return error; 1456 1457 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1458 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1459 if (error) 1460 goto free; 1461 1462 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1463 0, BUS_DMA_NOWAIT, &p->map); 1464 if (error) 1465 goto unmap; 1466 1467 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1468 BUS_DMA_NOWAIT); 1469 if (error) 1470 goto destroy; 1471 return 0; 1472 1473 destroy: 1474 bus_dmamap_destroy(sc->dmat, p->map); 1475 unmap: 1476 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1477 free: 1478 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1479 return error; 1480 } 1481 1482 static int 1483 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1484 { 1485 1486 bus_dmamap_unload(sc->dmat, p->map); 1487 bus_dmamap_destroy(sc->dmat, p->map); 1488 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1489 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1490 return 0; 1491 } 1492 1493 static int 1494 auich_alloc_cdata(struct auich_softc *sc) 1495 { 1496 bus_dma_segment_t seg; 1497 int error, rseg; 1498 1499 /* 1500 * Allocate the control data structure, and create and load the 1501 * DMA map for it. 1502 */ 1503 if ((error = bus_dmamem_alloc(sc->dmat, 1504 sizeof(struct auich_cdata), 1505 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1506 printf("%s: unable to allocate control data, error = %d\n", 1507 sc->sc_dev.dv_xname, error); 1508 goto fail_0; 1509 } 1510 1511 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1512 sizeof(struct auich_cdata), 1513 (caddr_t *) &sc->sc_cdata, 1514 sc->sc_dmamap_flags)) != 0) { 1515 printf("%s: unable to map control data, error = %d\n", 1516 sc->sc_dev.dv_xname, error); 1517 goto fail_1; 1518 } 1519 1520 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1521 sizeof(struct auich_cdata), 0, 0, 1522 &sc->sc_cddmamap)) != 0) { 1523 printf("%s: unable to create control data DMA map, " 1524 "error = %d\n", sc->sc_dev.dv_xname, error); 1525 goto fail_2; 1526 } 1527 1528 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1529 sc->sc_cdata, sizeof(struct auich_cdata), 1530 NULL, 0)) != 0) { 1531 printf("%s: unable tp load control data DMA map, " 1532 "error = %d\n", sc->sc_dev.dv_xname, error); 1533 goto fail_3; 1534 } 1535 1536 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1537 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1538 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1539 1540 return 0; 1541 1542 fail_3: 1543 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1544 fail_2: 1545 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1546 sizeof(struct auich_cdata)); 1547 fail_1: 1548 bus_dmamem_free(sc->dmat, &seg, rseg); 1549 fail_0: 1550 return error; 1551 } 1552 1553 static void 1554 auich_powerhook(int why, void *addr) 1555 { 1556 struct auich_softc *sc; 1557 const int d0 = PCI_PWR_D0; 1558 const int d3 = PCI_PWR_D3; 1559 int rv; 1560 1561 sc = (struct auich_softc *)addr; 1562 switch (why) { 1563 case PWR_SUSPEND: 1564 case PWR_STANDBY: 1565 /* Power down */ 1566 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1567 1568 /* if we're already asleep, don't try to sleep again */ 1569 if (sc->sc_suspend == PWR_SUSPEND || 1570 sc->sc_suspend == PWR_STANDBY) 1571 break; 1572 sc->sc_suspend = why; 1573 1574 DELAY(1000); 1575 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1576 1577 if (sc->sc_ih != NULL) 1578 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1579 1580 rv = pci_powerstate(sc->sc_pc, sc->sc_pt, &d3, &sc->sc_powerstate); 1581 if (rv) 1582 aprint_error("%s: unable to set power state (err=%d)\n", 1583 sc->sc_dev.dv_xname, rv); 1584 1585 break; 1586 1587 case PWR_RESUME: 1588 /* Wake up */ 1589 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1590 if (sc->sc_suspend == PWR_RESUME) { 1591 printf("%s: resume without suspend.\n", 1592 sc->sc_dev.dv_xname); 1593 sc->sc_suspend = why; 1594 return; 1595 } 1596 1597 rv = pci_powerstate(sc->sc_pc, sc->sc_pt, &d0, &sc->sc_powerstate); 1598 if (rv) 1599 aprint_error("%s: unable to set power state (err=%d)\n", 1600 sc->sc_dev.dv_xname, rv); 1601 1602 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 1603 auich_intr, sc); 1604 if (sc->sc_ih == NULL) { 1605 aprint_error("%s: can't establish interrupt", 1606 sc->sc_dev.dv_xname); 1607 /* XXX jmcneill what should we do here? */ 1608 return; 1609 } 1610 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1611 sc->sc_suspend = why; 1612 auich_reset_codec(sc); 1613 DELAY(1000); 1614 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1615 break; 1616 1617 case PWR_SOFTSUSPEND: 1618 case PWR_SOFTSTANDBY: 1619 case PWR_SOFTRESUME: 1620 break; 1621 } 1622 } 1623 1624 /* 1625 * Calibrate card (some boards are overclocked and need scaling) 1626 */ 1627 static void 1628 auich_calibrate(struct auich_softc *sc) 1629 { 1630 struct timeval t1, t2; 1631 uint8_t ociv, nciv; 1632 uint64_t wait_us; 1633 uint32_t actual_48k_rate, bytes, ac97rate; 1634 void *temp_buffer; 1635 struct auich_dma *p; 1636 u_int rate; 1637 1638 /* 1639 * Grab audio from input for fixed interval and compare how 1640 * much we actually get with what we expect. Interval needs 1641 * to be sufficiently short that no interrupts are 1642 * generated. 1643 */ 1644 1645 /* Force the codec to a known state first. */ 1646 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1647 rate = sc->sc_ac97_clock = 48000; 1648 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1649 &rate); 1650 1651 /* Setup a buffer */ 1652 bytes = 64000; 1653 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1654 1655 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1656 continue; 1657 if (p == NULL) { 1658 printf("auich_calibrate: bad address %p\n", temp_buffer); 1659 return; 1660 } 1661 sc->pcmi.dmalist[0].base = DMAADDR(p); 1662 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1663 1664 /* 1665 * our data format is stereo, 16 bit so each sample is 4 bytes. 1666 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1667 * we're going to start recording with interrupts disabled and measure 1668 * the time taken for one block to complete. we know the block size, 1669 * we know the time in microseconds, we calculate the sample rate: 1670 * 1671 * actual_rate [bps] = bytes / (time [s] * 4) 1672 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1673 * actual_rate [Hz] = (bytes * 250000) / time [us] 1674 */ 1675 1676 /* prepare */ 1677 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1678 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1679 sc->sc_cddma + ICH_PCMI_OFF(0)); 1680 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1681 (0 - 1) & ICH_LVI_MASK); 1682 1683 /* start */ 1684 microtime(&t1); 1685 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1686 1687 /* wait */ 1688 nciv = ociv; 1689 do { 1690 microtime(&t2); 1691 if (t2.tv_sec - t1.tv_sec > 1) 1692 break; 1693 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1694 ICH_PCMI + ICH_CIV); 1695 } while (nciv == ociv); 1696 microtime(&t2); 1697 1698 /* stop */ 1699 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1700 1701 /* reset */ 1702 DELAY(100); 1703 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1704 1705 /* turn time delta into us */ 1706 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1707 1708 auich_freem(sc, temp_buffer, M_DEVBUF); 1709 1710 if (nciv == ociv) { 1711 printf("%s: ac97 link rate calibration timed out after %" 1712 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1713 return; 1714 } 1715 1716 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1717 1718 if (actual_48k_rate < 50000) 1719 ac97rate = 48000; 1720 else 1721 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1722 1723 printf("%s: measured ac97 link rate at %d Hz", 1724 sc->sc_dev.dv_xname, actual_48k_rate); 1725 if (ac97rate != actual_48k_rate) 1726 printf(", will use %d Hz", ac97rate); 1727 printf("\n"); 1728 1729 sc->sc_ac97_clock = ac97rate; 1730 } 1731 1732 static void 1733 auich_clear_cas(struct auich_softc *sc) 1734 { 1735 /* Clear the codec access semaphore */ 1736 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1737 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1738 1739 return; 1740 } 1741
Indexes created Thu Oct 23 22:10:10 GMT 2025