auich.c revision 1.108
1 /* $NetBSD: auich.c,v 1.108 2006/06/17 23:34:26 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.108 2006/06/17 23:34:26 christos Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 pci_intr_handle_t intrh; 187 188 struct ac97_codec_if *codec_if; 189 struct ac97_host_if host_if; 190 int sc_codecnum; 191 int sc_codectype; 192 enum ac97_host_flags sc_codecflags; 193 194 /* DMA scatter-gather lists. */ 195 bus_dmamap_t sc_cddmamap; 196 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 197 198 struct auich_cdata *sc_cdata; 199 200 struct auich_ring { 201 int qptr; 202 struct auich_dmalist *dmalist; 203 204 uint32_t start, p, end; 205 int blksize; 206 207 void (*intr)(void *); 208 void *arg; 209 } pcmo, pcmi, mici; 210 211 struct auich_dma *sc_dmas; 212 213 /* SiS 7012 hack */ 214 int sc_sample_shift; 215 int sc_sts_reg; 216 /* 440MX workaround */ 217 int sc_dmamap_flags; 218 219 /* Power Management */ 220 void *sc_powerhook; 221 int sc_suspend; 222 int sc_powerstate; 223 struct pci_conf_state sc_pciconf; 224 225 /* sysctl */ 226 struct sysctllog *sc_log; 227 uint32_t sc_ac97_clock; 228 int sc_ac97_clock_mib; 229 230 int sc_modem_offset; 231 232 #define AUICH_AUDIO_NFORMATS 3 233 #define AUICH_MODEM_NFORMATS 1 234 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 235 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 236 struct audio_encoding_set *sc_encodings; 237 }; 238 239 /* Debug */ 240 #ifdef AUICH_DEBUG 241 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 242 int auich_debug = 0xfffe; 243 #define ICH_DEBUG_CODECIO 0x0001 244 #define ICH_DEBUG_DMA 0x0002 245 #define ICH_DEBUG_INTR 0x0004 246 #else 247 #define DPRINTF(x,y) /* nothing */ 248 #endif 249 250 static int auich_match(struct device *, struct cfdata *, void *); 251 static void auich_attach(struct device *, struct device *, void *); 252 static int auich_detach(struct device *, int); 253 static int auich_activate(struct device *, enum devact); 254 static int auich_intr(void *); 255 256 CFATTACH_DECL(auich, sizeof(struct auich_softc), 257 auich_match, auich_attach, auich_detach, auich_activate); 258 259 static int auich_query_encoding(void *, struct audio_encoding *); 260 static int auich_set_params(void *, int, int, audio_params_t *, 261 audio_params_t *, stream_filter_list_t *, 262 stream_filter_list_t *); 263 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 264 static void auich_halt_pipe(struct auich_softc *, int); 265 static int auich_halt_output(void *); 266 static int auich_halt_input(void *); 267 static int auich_getdev(void *, struct audio_device *); 268 static int auich_set_port(void *, mixer_ctrl_t *); 269 static int auich_get_port(void *, mixer_ctrl_t *); 270 static int auich_query_devinfo(void *, mixer_devinfo_t *); 271 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 272 static void auich_freem(void *, void *, struct malloc_type *); 273 static size_t auich_round_buffersize(void *, int, size_t); 274 static paddr_t auich_mappage(void *, void *, off_t, int); 275 static int auich_get_props(void *); 276 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 277 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 278 static int auich_trigger_output(void *, void *, void *, int, 279 void (*)(void *), void *, const audio_params_t *); 280 static int auich_trigger_input(void *, void *, void *, int, 281 void (*)(void *), void *, const audio_params_t *); 282 static int auich_powerstate(void *, int); 283 284 static int auich_alloc_cdata(struct auich_softc *); 285 286 static int auich_allocmem(struct auich_softc *, size_t, size_t, 287 struct auich_dma *); 288 static int auich_freemem(struct auich_softc *, struct auich_dma *); 289 290 static void auich_powerhook(int, void *); 291 static int auich_set_rate(struct auich_softc *, int, u_long); 292 static int auich_sysctl_verify(SYSCTLFN_ARGS); 293 static void auich_finish_attach(struct device *); 294 static void auich_calibrate(struct auich_softc *); 295 static void auich_clear_cas(struct auich_softc *); 296 297 static int auich_attach_codec(void *, struct ac97_codec_if *); 298 static int auich_read_codec(void *, uint8_t, uint16_t *); 299 static int auich_write_codec(void *, uint8_t, uint16_t); 300 static int auich_reset_codec(void *); 301 static enum ac97_host_flags auich_flags_codec(void *); 302 303 static const struct audio_hw_if auich_hw_if = { 304 NULL, /* open */ 305 NULL, /* close */ 306 NULL, /* drain */ 307 auich_query_encoding, 308 auich_set_params, 309 auich_round_blocksize, 310 NULL, /* commit_setting */ 311 NULL, /* init_output */ 312 NULL, /* init_input */ 313 NULL, /* start_output */ 314 NULL, /* start_input */ 315 auich_halt_output, 316 auich_halt_input, 317 NULL, /* speaker_ctl */ 318 auich_getdev, 319 NULL, /* getfd */ 320 auich_set_port, 321 auich_get_port, 322 auich_query_devinfo, 323 auich_allocm, 324 auich_freem, 325 auich_round_buffersize, 326 auich_mappage, 327 auich_get_props, 328 auich_trigger_output, 329 auich_trigger_input, 330 NULL, /* dev_ioctl */ 331 auich_powerstate, 332 }; 333 334 #define AUICH_FORMATS_1CH 0 335 #define AUICH_FORMATS_4CH 1 336 #define AUICH_FORMATS_6CH 2 337 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 338 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 339 2, AUFMT_STEREO, 0, {8000, 48000}}, 340 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 341 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 342 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 343 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 344 }; 345 346 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 347 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 348 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 349 }; 350 351 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 352 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 353 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 354 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 355 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 356 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 357 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 358 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 359 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 360 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 361 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 362 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 363 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 364 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 365 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 366 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 367 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 368 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 369 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 370 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 371 372 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 373 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 374 375 struct auich_devtype { 376 pcireg_t id; 377 const char *name; 378 const char *shortname; /* must be less than 11 characters */ 379 }; 380 381 static const struct auich_devtype auich_audio_devices[] = { 382 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 383 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 384 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 385 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 386 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 387 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 388 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 389 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 390 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 391 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 392 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 393 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 394 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 395 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 396 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 397 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 398 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 399 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 400 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 401 { 0, NULL, NULL }, 402 }; 403 404 static const struct auich_devtype auich_modem_devices[] = { 405 #ifdef AUICH_ATTACH_MODEM 406 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 407 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 408 #endif 409 { 0, NULL, NULL }, 410 }; 411 412 static const struct auich_devtype * 413 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 414 { 415 const struct auich_devtype *d; 416 417 for (d = auich_devices; d->name != NULL; d++) { 418 if (pa->pa_id == d->id) 419 return d; 420 } 421 422 return NULL; 423 } 424 425 static int 426 auich_match(struct device *parent, struct cfdata *match, void *aux) 427 { 428 struct pci_attach_args *pa; 429 430 pa = aux; 431 if (auich_lookup(pa, auich_audio_devices) != NULL) 432 return 1; 433 if (auich_lookup(pa, auich_modem_devices) != NULL) 434 return 1; 435 436 return 0; 437 } 438 439 static void 440 auich_attach(struct device *parent, struct device *self, void *aux) 441 { 442 struct auich_softc *sc; 443 struct pci_attach_args *pa; 444 pcireg_t v, subdev; 445 const char *intrstr; 446 const struct auich_devtype *d; 447 const struct sysctlnode *node, *node_ac97clock; 448 int err, node_mib, i; 449 450 sc = (struct auich_softc *)self; 451 pa = aux; 452 453 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 454 sc->sc_modem_offset = 0x10; 455 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 456 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 457 sc->sc_modem_offset = 0; 458 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 459 } else 460 panic("auich_attach: impossible"); 461 462 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 463 aprint_naive(": Audio controller\n"); 464 else 465 aprint_naive(": Modem controller\n"); 466 467 sc->sc_pc = pa->pa_pc; 468 sc->sc_pt = pa->pa_tag; 469 470 aprint_normal(": %s\n", d->name); 471 472 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 473 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 474 || d->id == PCIID_ICH4MODEM) { 475 /* 476 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 477 */ 478 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 479 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 480 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 481 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 482 v | ICH_CFG_IOSE); 483 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 484 0, &sc->iot, &sc->mix_ioh, NULL, 485 &sc->mix_size)) { 486 aprint_error("%s: can't map codec i/o space\n", 487 sc->sc_dev.dv_xname); 488 return; 489 } 490 } 491 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 492 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 493 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 494 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 495 v | ICH_CFG_IOSE); 496 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 497 0, &sc->iot, &sc->aud_ioh, NULL, 498 &sc->aud_size)) { 499 aprint_error("%s: can't map device i/o space\n", 500 sc->sc_dev.dv_xname); 501 return; 502 } 503 } 504 } else { 505 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 506 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 507 aprint_error("%s: can't map codec i/o space\n", 508 sc->sc_dev.dv_xname); 509 return; 510 } 511 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 512 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 513 aprint_error("%s: can't map device i/o space\n", 514 sc->sc_dev.dv_xname); 515 return; 516 } 517 } 518 sc->dmat = pa->pa_dmat; 519 520 /* enable bus mastering */ 521 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 522 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 523 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 524 525 /* Map and establish the interrupt. */ 526 if (pci_intr_map(pa, &sc->intrh)) { 527 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 528 return; 529 } 530 intrstr = pci_intr_string(pa->pa_pc, sc->intrh); 531 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO, 532 auich_intr, sc); 533 if (sc->sc_ih == NULL) { 534 aprint_error("%s: can't establish interrupt", 535 sc->sc_dev.dv_xname); 536 if (intrstr != NULL) 537 aprint_normal(" at %s", intrstr); 538 aprint_normal("\n"); 539 return; 540 } 541 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 542 543 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 544 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 545 "0x%02x", PCI_REVISION(pa->pa_class)); 546 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 547 548 /* SiS 7012 needs special handling */ 549 if (d->id == PCIID_SIS7012) { 550 sc->sc_sts_reg = ICH_PICB; 551 sc->sc_sample_shift = 0; 552 /* Un-mute output. From Linux. */ 553 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 554 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 555 ICH_SIS_CTL_UNMUTE); 556 } else { 557 sc->sc_sts_reg = ICH_STS; 558 sc->sc_sample_shift = 1; 559 } 560 561 /* Workaround for a 440MX B-stepping erratum */ 562 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 563 if (d->id == PCIID_440MX) { 564 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 565 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 566 } 567 568 /* Set up DMA lists. */ 569 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 570 auich_alloc_cdata(sc); 571 572 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 573 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 574 575 /* Modem codecs are always the secondary codec on ICH */ 576 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 577 578 sc->host_if.arg = sc; 579 sc->host_if.attach = auich_attach_codec; 580 sc->host_if.read = auich_read_codec; 581 sc->host_if.write = auich_write_codec; 582 sc->host_if.reset = auich_reset_codec; 583 sc->host_if.flags = auich_flags_codec; 584 585 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 586 switch (subdev) { 587 case 0x202f161f: /* Gateway 7326GZ */ 588 case 0x203a161f: /* Gateway 4028GZ */ 589 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 590 case 0x8144104d: /* Sony VAIO PCG-TR* */ 591 case 0x8197104d: /* Sony S1XP */ 592 case 0x81c0104d: /* Sony VAIO type T */ 593 case 0x81c5104d: /* Sony VAIO VGN-B1XP */ 594 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP; 595 break; 596 default: 597 sc->sc_codecflags = 0; 598 break; 599 } 600 601 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 602 return; 603 604 /* setup audio_format */ 605 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 606 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 607 if (!AC97_IS_4CH(sc->codec_if)) 608 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 609 if (!AC97_IS_6CH(sc->codec_if)) 610 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 611 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 612 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 613 sc->sc_audio_formats[i].frequency_type = 1; 614 sc->sc_audio_formats[i].frequency[0] = 48000; 615 } 616 } 617 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 618 &sc->sc_encodings)) 619 return; 620 } else { 621 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 622 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 623 &sc->sc_encodings)) 624 return; 625 } 626 627 628 /* Watch for power change */ 629 sc->sc_suspend = PWR_RESUME; 630 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 631 632 config_interrupts(self, auich_finish_attach); 633 634 /* sysctl setup */ 635 if (AC97_IS_FIXED_RATE(sc->codec_if) && 636 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 637 return; 638 639 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 640 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 641 CTL_HW, CTL_EOL); 642 if (err != 0) 643 goto sysctl_err; 644 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 645 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 646 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 647 if (err != 0) 648 goto sysctl_err; 649 node_mib = node->sysctl_num; 650 651 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 652 /* passing the sc address instead of &sc->sc_ac97_clock */ 653 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 654 CTLFLAG_READWRITE, 655 CTLTYPE_INT, "ac97rate", 656 SYSCTL_DESCR("AC'97 codec link rate"), 657 auich_sysctl_verify, 0, sc, 0, 658 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 659 if (err != 0) 660 goto sysctl_err; 661 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 662 } 663 664 return; 665 666 sysctl_err: 667 printf("%s: failed to add sysctl nodes. (%d)\n", 668 sc->sc_dev.dv_xname, err); 669 return; /* failure of sysctl is not fatal. */ 670 } 671 672 static int 673 auich_activate(struct device *self, enum devact act) 674 { 675 struct auich_softc *sc; 676 int ret; 677 678 sc = (struct auich_softc *)self; 679 ret = 0; 680 switch (act) { 681 case DVACT_ACTIVATE: 682 return EOPNOTSUPP; 683 case DVACT_DEACTIVATE: 684 if (sc->sc_audiodev != NULL) 685 ret = config_deactivate(sc->sc_audiodev); 686 return ret; 687 } 688 return EOPNOTSUPP; 689 } 690 691 static int 692 auich_detach(struct device *self, int flags) 693 { 694 struct auich_softc *sc; 695 696 sc = (struct auich_softc *)self; 697 698 /* audio */ 699 if (sc->sc_audiodev != NULL) 700 config_detach(sc->sc_audiodev, flags); 701 702 /* sysctl */ 703 sysctl_teardown(&sc->sc_log); 704 705 /* audio_encoding_set */ 706 auconv_delete_encodings(sc->sc_encodings); 707 708 /* ac97 */ 709 if (sc->codec_if != NULL) 710 sc->codec_if->vtbl->detach(sc->codec_if); 711 712 /* PCI */ 713 if (sc->sc_ih != NULL) 714 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 715 if (sc->mix_size != 0) 716 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 717 if (sc->aud_size != 0) 718 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 719 return 0; 720 } 721 722 static int 723 auich_sysctl_verify(SYSCTLFN_ARGS) 724 { 725 int error, tmp; 726 struct sysctlnode node; 727 struct auich_softc *sc; 728 729 node = *rnode; 730 sc = rnode->sysctl_data; 731 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 732 tmp = sc->sc_ac97_clock; 733 node.sysctl_data = &tmp; 734 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 735 if (error || newp == NULL) 736 return error; 737 738 if (tmp < 48000 || tmp > 96000) 739 return EINVAL; 740 sc->sc_ac97_clock = tmp; 741 } 742 743 return 0; 744 } 745 746 static void 747 auich_finish_attach(struct device *self) 748 { 749 struct auich_softc *sc; 750 751 sc = (void *)self; 752 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 753 auich_calibrate(sc); 754 755 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 756 757 #if notyet 758 auich_powerhook(PWR_SUSPEND, sc); 759 #endif 760 761 return; 762 } 763 764 #define ICH_CODECIO_INTERVAL 10 765 static int 766 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 767 { 768 struct auich_softc *sc; 769 int i; 770 uint32_t status; 771 772 sc = v; 773 /* wait for an access semaphore */ 774 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 775 bus_space_read_1(sc->iot, sc->aud_ioh, 776 ICH_CAS + sc->sc_modem_offset) & 1; 777 DELAY(ICH_CODECIO_INTERVAL)); 778 779 if (i > 0) { 780 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 781 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 782 DPRINTF(ICH_DEBUG_CODECIO, 783 ("auich_read_codec(%x, %x)\n", reg, *val)); 784 status = bus_space_read_4(sc->iot, sc->aud_ioh, 785 ICH_GSTS + sc->sc_modem_offset); 786 if (status & ICH_RCS) { 787 bus_space_write_4(sc->iot, sc->aud_ioh, 788 ICH_GSTS + sc->sc_modem_offset, 789 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 790 *val = 0xffff; 791 DPRINTF(ICH_DEBUG_CODECIO, 792 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 793 if (reg == AC97_REG_GPIO_STATUS) 794 auich_clear_cas(sc); 795 return -1; 796 } 797 if (reg == AC97_REG_GPIO_STATUS) 798 auich_clear_cas(sc); 799 return 0; 800 } else { 801 aprint_normal("%s: read_codec timeout\n", sc->sc_dev.dv_xname); 802 if (reg == AC97_REG_GPIO_STATUS) 803 auich_clear_cas(sc); 804 return -1; 805 } 806 } 807 808 static int 809 auich_write_codec(void *v, uint8_t reg, uint16_t val) 810 { 811 struct auich_softc *sc; 812 int i; 813 814 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 815 sc = v; 816 /* wait for an access semaphore */ 817 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 818 bus_space_read_1(sc->iot, sc->aud_ioh, 819 ICH_CAS + sc->sc_modem_offset) & 1; 820 DELAY(ICH_CODECIO_INTERVAL)); 821 822 if (i > 0) { 823 bus_space_write_2(sc->iot, sc->mix_ioh, 824 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 825 return 0; 826 } else { 827 aprint_normal("%s: write_codec timeout\n", sc->sc_dev.dv_xname); 828 return -1; 829 } 830 } 831 832 static int 833 auich_attach_codec(void *v, struct ac97_codec_if *cif) 834 { 835 struct auich_softc *sc; 836 837 sc = v; 838 sc->codec_if = cif; 839 840 return 0; 841 } 842 843 static int 844 auich_reset_codec(void *v) 845 { 846 struct auich_softc *sc; 847 int i; 848 uint32_t control, status; 849 850 sc = v; 851 control = bus_space_read_4(sc->iot, sc->aud_ioh, 852 ICH_GCTRL + sc->sc_modem_offset); 853 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 854 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 855 } else { 856 control &= ~ICH_ACLSO; 857 control |= ICH_GIE; 858 } 859 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 860 bus_space_write_4(sc->iot, sc->aud_ioh, 861 ICH_GCTRL + sc->sc_modem_offset, control); 862 863 for (i = 500000; i >= 0; i--) { 864 status = bus_space_read_4(sc->iot, sc->aud_ioh, 865 ICH_GSTS + sc->sc_modem_offset); 866 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 867 break; 868 DELAY(1); 869 } 870 if (i <= 0) { 871 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 872 return ETIMEDOUT; 873 } 874 #ifdef AUICH_DEBUG 875 if (status & ICH_SCR) 876 printf("%s: The 2nd codec is ready.\n", 877 sc->sc_dev.dv_xname); 878 if (status & ICH_S2CR) 879 printf("%s: The 3rd codec is ready.\n", 880 sc->sc_dev.dv_xname); 881 #endif 882 return 0; 883 } 884 885 static enum ac97_host_flags 886 auich_flags_codec(void *v) 887 { 888 struct auich_softc *sc = v; 889 return sc->sc_codecflags; 890 } 891 892 static int 893 auich_query_encoding(void *v, struct audio_encoding *aep) 894 { 895 struct auich_softc *sc; 896 897 sc = (struct auich_softc *)v; 898 return auconv_query_encoding(sc->sc_encodings, aep); 899 } 900 901 static int 902 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 903 { 904 int ret; 905 u_int ratetmp; 906 907 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 908 ratetmp = srate; 909 if (mode == AUMODE_RECORD) 910 return sc->codec_if->vtbl->set_rate(sc->codec_if, 911 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 912 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 913 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 914 if (ret) 915 return ret; 916 ratetmp = srate; 917 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 918 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 919 if (ret) 920 return ret; 921 ratetmp = srate; 922 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 923 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 924 return ret; 925 } 926 927 static int 928 auich_set_params(void *v, int setmode, int usemode, audio_params_t *play, 929 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 930 { 931 struct auich_softc *sc; 932 audio_params_t *p; 933 stream_filter_list_t *fil; 934 int mode, index; 935 uint32_t control; 936 937 sc = v; 938 for (mode = AUMODE_RECORD; mode != -1; 939 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 940 if ((setmode & mode) == 0) 941 continue; 942 943 p = mode == AUMODE_PLAY ? play : rec; 944 fil = mode == AUMODE_PLAY ? pfil : rfil; 945 if (p == NULL) 946 continue; 947 948 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 949 if (p->sample_rate < 8000 || 950 p->sample_rate > 48000) 951 return EINVAL; 952 953 index = auconv_set_converter(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 954 mode, p, TRUE, fil); 955 } else { 956 if (p->sample_rate != 8000 && p->sample_rate != 16000) 957 return EINVAL; 958 index = auconv_set_converter(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 959 mode, p, TRUE, fil); 960 } 961 if (index < 0) 962 return EINVAL; 963 if (fil->req_size > 0) 964 p = &fil->filters[0].param; 965 /* p represents HW encoding */ 966 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 967 if (sc->sc_audio_formats[index].frequency_type != 1 968 && auich_set_rate(sc, mode, p->sample_rate)) 969 return EINVAL; 970 } else { 971 if (sc->sc_modem_formats[index].frequency_type != 1 972 && auich_set_rate(sc, mode, p->sample_rate)) 973 return EINVAL; 974 auich_write_codec(sc, AC97_REG_LINE1_RATE, 975 p->sample_rate); 976 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 977 } 978 if (mode == AUMODE_PLAY && 979 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 980 control = bus_space_read_4(sc->iot, sc->aud_ioh, 981 ICH_GCTRL + sc->sc_modem_offset); 982 control &= ~ICH_PCM246_MASK; 983 if (p->channels == 4) { 984 control |= ICH_PCM4; 985 } else if (p->channels == 6) { 986 control |= ICH_PCM6; 987 } 988 bus_space_write_4(sc->iot, sc->aud_ioh, 989 ICH_GCTRL + sc->sc_modem_offset, control); 990 } 991 } 992 993 return 0; 994 } 995 996 static int 997 auich_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 998 { 999 1000 return blk & ~0x3f; /* keep good alignment */ 1001 } 1002 1003 static void 1004 auich_halt_pipe(struct auich_softc *sc, int pipe) 1005 { 1006 int i; 1007 uint32_t status; 1008 1009 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 1010 for (i = 0; i < 100; i++) { 1011 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 1012 if (status & ICH_DCH) 1013 break; 1014 DELAY(1); 1015 } 1016 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 1017 1018 #if AUICH_DEBUG 1019 if (i > 0) 1020 printf("auich_halt_pipe: halt took %d cycles\n", i); 1021 #endif 1022 } 1023 1024 static int 1025 auich_halt_output(void *v) 1026 { 1027 struct auich_softc *sc; 1028 1029 sc = v; 1030 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 1031 1032 auich_halt_pipe(sc, ICH_PCMO); 1033 sc->pcmo.intr = NULL; 1034 1035 return 0; 1036 } 1037 1038 static int 1039 auich_halt_input(void *v) 1040 { 1041 struct auich_softc *sc; 1042 1043 sc = v; 1044 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", sc->sc_dev.dv_xname)); 1045 1046 auich_halt_pipe(sc, ICH_PCMI); 1047 sc->pcmi.intr = NULL; 1048 1049 return 0; 1050 } 1051 1052 static int 1053 auich_getdev(void *v, struct audio_device *adp) 1054 { 1055 struct auich_softc *sc; 1056 1057 sc = v; 1058 *adp = sc->sc_audev; 1059 return 0; 1060 } 1061 1062 static int 1063 auich_set_port(void *v, mixer_ctrl_t *cp) 1064 { 1065 struct auich_softc *sc; 1066 1067 sc = v; 1068 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1069 } 1070 1071 static int 1072 auich_get_port(void *v, mixer_ctrl_t *cp) 1073 { 1074 struct auich_softc *sc; 1075 1076 sc = v; 1077 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1078 } 1079 1080 static int 1081 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1082 { 1083 struct auich_softc *sc; 1084 1085 sc = v; 1086 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1087 } 1088 1089 static void * 1090 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 1091 int flags) 1092 { 1093 struct auich_softc *sc; 1094 struct auich_dma *p; 1095 int error; 1096 1097 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1098 return NULL; 1099 1100 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1101 if (p == NULL) 1102 return NULL; 1103 1104 sc = v; 1105 error = auich_allocmem(sc, size, 0, p); 1106 if (error) { 1107 free(p, pool); 1108 return NULL; 1109 } 1110 1111 p->next = sc->sc_dmas; 1112 sc->sc_dmas = p; 1113 1114 return KERNADDR(p); 1115 } 1116 1117 static void 1118 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1119 { 1120 struct auich_softc *sc; 1121 struct auich_dma *p, **pp; 1122 1123 sc = v; 1124 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1125 if (KERNADDR(p) == ptr) { 1126 auich_freemem(sc, p); 1127 *pp = p->next; 1128 free(p, pool); 1129 return; 1130 } 1131 } 1132 } 1133 1134 static size_t 1135 auich_round_buffersize(void *v, int direction, size_t size) 1136 { 1137 1138 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1139 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1140 1141 return size; 1142 } 1143 1144 static paddr_t 1145 auich_mappage(void *v, void *mem, off_t off, int prot) 1146 { 1147 struct auich_softc *sc; 1148 struct auich_dma *p; 1149 1150 if (off < 0) 1151 return -1; 1152 sc = v; 1153 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1154 continue; 1155 if (!p) 1156 return -1; 1157 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1158 off, prot, BUS_DMA_WAITOK); 1159 } 1160 1161 static int 1162 auich_get_props(void *v) 1163 { 1164 struct auich_softc *sc; 1165 int props; 1166 1167 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1168 sc = v; 1169 /* 1170 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1171 * rate because of aurateconv. Applications can't know what rate the 1172 * device can process in the case of mmap(). 1173 */ 1174 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1175 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1176 props |= AUDIO_PROP_MMAP; 1177 return props; 1178 } 1179 1180 static int 1181 auich_intr(void *v) 1182 { 1183 struct auich_softc *sc; 1184 int ret, gsts; 1185 #ifdef DIAGNOSTIC 1186 int csts; 1187 #endif 1188 1189 sc = v; 1190 ret = 0; 1191 #ifdef DIAGNOSTIC 1192 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1193 if (csts & PCI_STATUS_MASTER_ABORT) { 1194 printf("auich_intr: PCI master abort\n"); 1195 } 1196 #endif 1197 1198 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1199 ICH_GSTS + sc->sc_modem_offset); 1200 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1201 1202 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1203 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1204 int sts; 1205 1206 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1207 ICH_PCMO + sc->sc_sts_reg); 1208 DPRINTF(ICH_DEBUG_INTR, 1209 ("auich_intr: osts=0x%x\n", sts)); 1210 1211 if (sts & ICH_FIFOE) 1212 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1213 1214 if (sts & ICH_BCIS) 1215 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1216 1217 /* int ack */ 1218 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1219 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1220 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1221 bus_space_write_4(sc->iot, sc->aud_ioh, 1222 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1223 else 1224 bus_space_write_4(sc->iot, sc->aud_ioh, 1225 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1226 ret++; 1227 } 1228 1229 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1230 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1231 int sts; 1232 1233 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1234 ICH_PCMI + sc->sc_sts_reg); 1235 DPRINTF(ICH_DEBUG_INTR, 1236 ("auich_intr: ists=0x%x\n", sts)); 1237 1238 if (sts & ICH_FIFOE) 1239 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1240 1241 if (sts & ICH_BCIS) 1242 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1243 1244 /* int ack */ 1245 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1246 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1247 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1248 bus_space_write_4(sc->iot, sc->aud_ioh, 1249 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1250 else 1251 bus_space_write_4(sc->iot, sc->aud_ioh, 1252 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1253 ret++; 1254 } 1255 1256 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1257 int sts; 1258 1259 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1260 ICH_MICI + sc->sc_sts_reg); 1261 DPRINTF(ICH_DEBUG_INTR, 1262 ("auich_intr: ists=0x%x\n", sts)); 1263 1264 if (sts & ICH_FIFOE) 1265 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1266 1267 if (sts & ICH_BCIS) 1268 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1269 1270 /* int ack */ 1271 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1272 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1273 bus_space_write_4(sc->iot, sc->aud_ioh, 1274 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1275 ret++; 1276 } 1277 1278 #ifdef AUICH_MODEM_DEBUG 1279 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1280 printf("%s: gsts=0x%x\n", sc->sc_dev.dv_xname, gsts); 1281 /* int ack */ 1282 bus_space_write_4(sc->iot, sc->aud_ioh, 1283 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1284 ret++; 1285 } 1286 #endif 1287 1288 return ret; 1289 } 1290 1291 static void 1292 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1293 { 1294 int blksize, qptr; 1295 struct auich_dmalist *q; 1296 1297 blksize = ring->blksize; 1298 1299 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1300 q = &ring->dmalist[qptr]; 1301 q->base = ring->p; 1302 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1303 1304 ring->p += blksize; 1305 if (ring->p >= ring->end) 1306 ring->p = ring->start; 1307 } 1308 ring->qptr = 0; 1309 1310 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1311 (qptr - 1) & ICH_LVI_MASK); 1312 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1313 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1314 } 1315 1316 static void 1317 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1318 { 1319 int blksize, qptr, nqptr; 1320 struct auich_dmalist *q; 1321 1322 blksize = ring->blksize; 1323 qptr = ring->qptr; 1324 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1325 1326 while (qptr != nqptr) { 1327 q = &ring->dmalist[qptr]; 1328 q->base = ring->p; 1329 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1330 1331 DPRINTF(ICH_DEBUG_INTR, 1332 ("auich_intr: %p, %p = %x @ 0x%x\n", 1333 &ring->dmalist[qptr], q, q->len, q->base)); 1334 1335 ring->p += blksize; 1336 if (ring->p >= ring->end) 1337 ring->p = ring->start; 1338 1339 qptr = (qptr + 1) & ICH_LVI_MASK; 1340 if (ring->intr) 1341 ring->intr(ring->arg); 1342 } 1343 ring->qptr = qptr; 1344 1345 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1346 (qptr - 1) & ICH_LVI_MASK); 1347 } 1348 1349 static int 1350 auich_trigger_output(void *v, void *start, void *end, int blksize, 1351 void (*intr)(void *), void *arg, const audio_params_t *param) 1352 { 1353 struct auich_softc *sc; 1354 struct auich_dma *p; 1355 size_t size; 1356 1357 DPRINTF(ICH_DEBUG_DMA, 1358 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1359 start, end, blksize, intr, arg, param)); 1360 sc = v; 1361 1362 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1363 continue; 1364 if (!p) { 1365 printf("auich_trigger_output: bad addr %p\n", start); 1366 return EINVAL; 1367 } 1368 1369 size = (size_t)((caddr_t)end - (caddr_t)start); 1370 1371 sc->pcmo.intr = intr; 1372 sc->pcmo.arg = arg; 1373 sc->pcmo.start = DMAADDR(p); 1374 sc->pcmo.p = sc->pcmo.start; 1375 sc->pcmo.end = sc->pcmo.start + size; 1376 sc->pcmo.blksize = blksize; 1377 1378 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1379 sc->sc_cddma + ICH_PCMO_OFF(0)); 1380 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1381 1382 return 0; 1383 } 1384 1385 static int 1386 auich_trigger_input(void *v, void *start, void *end, int blksize, 1387 void (*intr)(void *), void *arg, const audio_params_t *param) 1388 { 1389 struct auich_softc *sc; 1390 struct auich_dma *p; 1391 size_t size; 1392 1393 DPRINTF(ICH_DEBUG_DMA, 1394 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1395 start, end, blksize, intr, arg, param)); 1396 sc = v; 1397 1398 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1399 continue; 1400 if (!p) { 1401 printf("auich_trigger_input: bad addr %p\n", start); 1402 return EINVAL; 1403 } 1404 1405 size = (size_t)((caddr_t)end - (caddr_t)start); 1406 1407 sc->pcmi.intr = intr; 1408 sc->pcmi.arg = arg; 1409 sc->pcmi.start = DMAADDR(p); 1410 sc->pcmi.p = sc->pcmi.start; 1411 sc->pcmi.end = sc->pcmi.start + size; 1412 sc->pcmi.blksize = blksize; 1413 1414 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1415 sc->sc_cddma + ICH_PCMI_OFF(0)); 1416 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1417 1418 return 0; 1419 } 1420 1421 static int 1422 auich_powerstate(void *v, int state) 1423 { 1424 #if notyet 1425 struct auich_softc *sc; 1426 int rv; 1427 1428 sc = (struct auich_softc *)v; 1429 rv = 0; 1430 1431 switch (state) { 1432 case AUDIOPOWER_OFF: 1433 auich_powerhook(PWR_SUSPEND, sc); 1434 break; 1435 case AUDIOPOWER_ON: 1436 auich_powerhook(PWR_RESUME, sc); 1437 break; 1438 default: 1439 aprint_error("%s: unknown power state %d\n", 1440 sc->sc_dev.dv_xname, state); 1441 rv = 1; 1442 break; 1443 } 1444 1445 return rv; 1446 #else 1447 return 0; 1448 #endif 1449 } 1450 1451 static int 1452 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1453 struct auich_dma *p) 1454 { 1455 int error; 1456 1457 p->size = size; 1458 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1459 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1460 &p->nsegs, BUS_DMA_NOWAIT); 1461 if (error) 1462 return error; 1463 1464 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1465 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1466 if (error) 1467 goto free; 1468 1469 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1470 0, BUS_DMA_NOWAIT, &p->map); 1471 if (error) 1472 goto unmap; 1473 1474 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1475 BUS_DMA_NOWAIT); 1476 if (error) 1477 goto destroy; 1478 return 0; 1479 1480 destroy: 1481 bus_dmamap_destroy(sc->dmat, p->map); 1482 unmap: 1483 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1484 free: 1485 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1486 return error; 1487 } 1488 1489 static int 1490 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1491 { 1492 1493 bus_dmamap_unload(sc->dmat, p->map); 1494 bus_dmamap_destroy(sc->dmat, p->map); 1495 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1496 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1497 return 0; 1498 } 1499 1500 static int 1501 auich_alloc_cdata(struct auich_softc *sc) 1502 { 1503 bus_dma_segment_t seg; 1504 int error, rseg; 1505 1506 /* 1507 * Allocate the control data structure, and create and load the 1508 * DMA map for it. 1509 */ 1510 if ((error = bus_dmamem_alloc(sc->dmat, 1511 sizeof(struct auich_cdata), 1512 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1513 printf("%s: unable to allocate control data, error = %d\n", 1514 sc->sc_dev.dv_xname, error); 1515 goto fail_0; 1516 } 1517 1518 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1519 sizeof(struct auich_cdata), 1520 (caddr_t *) &sc->sc_cdata, 1521 sc->sc_dmamap_flags)) != 0) { 1522 printf("%s: unable to map control data, error = %d\n", 1523 sc->sc_dev.dv_xname, error); 1524 goto fail_1; 1525 } 1526 1527 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1528 sizeof(struct auich_cdata), 0, 0, 1529 &sc->sc_cddmamap)) != 0) { 1530 printf("%s: unable to create control data DMA map, " 1531 "error = %d\n", sc->sc_dev.dv_xname, error); 1532 goto fail_2; 1533 } 1534 1535 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1536 sc->sc_cdata, sizeof(struct auich_cdata), 1537 NULL, 0)) != 0) { 1538 printf("%s: unable tp load control data DMA map, " 1539 "error = %d\n", sc->sc_dev.dv_xname, error); 1540 goto fail_3; 1541 } 1542 1543 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1544 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1545 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1546 1547 return 0; 1548 1549 fail_3: 1550 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1551 fail_2: 1552 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1553 sizeof(struct auich_cdata)); 1554 fail_1: 1555 bus_dmamem_free(sc->dmat, &seg, rseg); 1556 fail_0: 1557 return error; 1558 } 1559 1560 static void 1561 auich_powerhook(int why, void *addr) 1562 { 1563 struct auich_softc *sc; 1564 int rv; 1565 1566 sc = (struct auich_softc *)addr; 1567 switch (why) { 1568 case PWR_SUSPEND: 1569 case PWR_STANDBY: 1570 /* Power down */ 1571 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1572 1573 /* if we're already asleep, don't try to sleep again */ 1574 if (sc->sc_suspend == PWR_SUSPEND || 1575 sc->sc_suspend == PWR_STANDBY) 1576 break; 1577 sc->sc_suspend = why; 1578 1579 DELAY(1000); 1580 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1581 1582 if (sc->sc_ih != NULL) 1583 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1584 1585 rv = pci_get_powerstate(sc->sc_pc, sc->sc_pt, &sc->sc_powerstate); 1586 if (rv) 1587 aprint_error("%s: unable to get power state (err=%d)\n", 1588 sc->sc_dev.dv_xname, rv); 1589 rv = pci_set_powerstate(sc->sc_pc, sc->sc_pt, PCI_PMCSR_STATE_D3); 1590 if (rv) 1591 aprint_error("%s: unable to set power state (err=%d)\n", 1592 sc->sc_dev.dv_xname, rv); 1593 1594 break; 1595 1596 case PWR_RESUME: 1597 /* Wake up */ 1598 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1599 if (sc->sc_suspend == PWR_RESUME) { 1600 printf("%s: resume without suspend.\n", 1601 sc->sc_dev.dv_xname); 1602 sc->sc_suspend = why; 1603 return; 1604 } 1605 1606 rv = pci_set_powerstate(sc->sc_pc, sc->sc_pt, sc->sc_powerstate); 1607 if (rv) 1608 aprint_error("%s: unable to set power state (err=%d)\n", 1609 sc->sc_dev.dv_xname, rv); 1610 1611 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 1612 auich_intr, sc); 1613 if (sc->sc_ih == NULL) { 1614 aprint_error("%s: can't establish interrupt", 1615 sc->sc_dev.dv_xname); 1616 /* XXX jmcneill what should we do here? */ 1617 return; 1618 } 1619 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1620 sc->sc_suspend = why; 1621 auich_reset_codec(sc); 1622 DELAY(1000); 1623 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1624 break; 1625 1626 case PWR_SOFTSUSPEND: 1627 case PWR_SOFTSTANDBY: 1628 case PWR_SOFTRESUME: 1629 break; 1630 } 1631 } 1632 1633 /* 1634 * Calibrate card (some boards are overclocked and need scaling) 1635 */ 1636 static void 1637 auich_calibrate(struct auich_softc *sc) 1638 { 1639 struct timeval t1, t2; 1640 uint8_t ociv, nciv; 1641 uint64_t wait_us; 1642 uint32_t actual_48k_rate, bytes, ac97rate; 1643 void *temp_buffer; 1644 struct auich_dma *p; 1645 u_int rate; 1646 1647 /* 1648 * Grab audio from input for fixed interval and compare how 1649 * much we actually get with what we expect. Interval needs 1650 * to be sufficiently short that no interrupts are 1651 * generated. 1652 */ 1653 1654 /* Force the codec to a known state first. */ 1655 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1656 rate = sc->sc_ac97_clock = 48000; 1657 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1658 &rate); 1659 1660 /* Setup a buffer */ 1661 bytes = 64000; 1662 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1663 1664 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1665 continue; 1666 if (p == NULL) { 1667 printf("auich_calibrate: bad address %p\n", temp_buffer); 1668 return; 1669 } 1670 sc->pcmi.dmalist[0].base = DMAADDR(p); 1671 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1672 1673 /* 1674 * our data format is stereo, 16 bit so each sample is 4 bytes. 1675 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1676 * we're going to start recording with interrupts disabled and measure 1677 * the time taken for one block to complete. we know the block size, 1678 * we know the time in microseconds, we calculate the sample rate: 1679 * 1680 * actual_rate [bps] = bytes / (time [s] * 4) 1681 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1682 * actual_rate [Hz] = (bytes * 250000) / time [us] 1683 */ 1684 1685 /* prepare */ 1686 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1687 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1688 sc->sc_cddma + ICH_PCMI_OFF(0)); 1689 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1690 (0 - 1) & ICH_LVI_MASK); 1691 1692 /* start */ 1693 microtime(&t1); 1694 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1695 1696 /* wait */ 1697 nciv = ociv; 1698 do { 1699 microtime(&t2); 1700 if (t2.tv_sec - t1.tv_sec > 1) 1701 break; 1702 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1703 ICH_PCMI + ICH_CIV); 1704 } while (nciv == ociv); 1705 microtime(&t2); 1706 1707 /* stop */ 1708 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1709 1710 /* reset */ 1711 DELAY(100); 1712 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1713 1714 /* turn time delta into us */ 1715 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1716 1717 auich_freem(sc, temp_buffer, M_DEVBUF); 1718 1719 if (nciv == ociv) { 1720 printf("%s: ac97 link rate calibration timed out after %" 1721 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1722 return; 1723 } 1724 1725 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1726 1727 if (actual_48k_rate < 50000) 1728 ac97rate = 48000; 1729 else 1730 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1731 1732 printf("%s: measured ac97 link rate at %d Hz", 1733 sc->sc_dev.dv_xname, actual_48k_rate); 1734 if (ac97rate != actual_48k_rate) 1735 printf(", will use %d Hz", ac97rate); 1736 printf("\n"); 1737 1738 sc->sc_ac97_clock = ac97rate; 1739 } 1740 1741 static void 1742 auich_clear_cas(struct auich_softc *sc) 1743 { 1744 /* Clear the codec access semaphore */ 1745 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1746 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1747 1748 return; 1749 } 1750
Indexes created Sun Sep 28 16:09:52 GMT 2025