auich.c revision 1.109
1 /* $NetBSD: auich.c,v 1.109 2006/07/28 07:41:39 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.109 2006/07/28 07:41:39 kent Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 pci_intr_handle_t intrh; 187 188 struct ac97_codec_if *codec_if; 189 struct ac97_host_if host_if; 190 int sc_codecnum; 191 int sc_codectype; 192 enum ac97_host_flags sc_codecflags; 193 boolean_t sc_spdif; 194 195 /* DMA scatter-gather lists. */ 196 bus_dmamap_t sc_cddmamap; 197 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 198 199 struct auich_cdata *sc_cdata; 200 201 struct auich_ring { 202 int qptr; 203 struct auich_dmalist *dmalist; 204 205 uint32_t start, p, end; 206 int blksize; 207 208 void (*intr)(void *); 209 void *arg; 210 } pcmo, pcmi, mici; 211 212 struct auich_dma *sc_dmas; 213 214 /* SiS 7012 hack */ 215 int sc_sample_shift; 216 int sc_sts_reg; 217 /* 440MX workaround */ 218 int sc_dmamap_flags; 219 220 /* Power Management */ 221 void *sc_powerhook; 222 int sc_suspend; 223 int sc_powerstate; 224 struct pci_conf_state sc_pciconf; 225 226 /* sysctl */ 227 struct sysctllog *sc_log; 228 uint32_t sc_ac97_clock; 229 int sc_ac97_clock_mib; 230 231 int sc_modem_offset; 232 233 #define AUICH_AUDIO_NFORMATS 3 234 #define AUICH_MODEM_NFORMATS 1 235 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 236 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 237 struct audio_encoding_set *sc_encodings; 238 struct audio_encoding_set *sc_spdif_encodings; 239 }; 240 241 /* Debug */ 242 #ifdef AUICH_DEBUG 243 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 244 int auich_debug = 0xfffe; 245 #define ICH_DEBUG_CODECIO 0x0001 246 #define ICH_DEBUG_DMA 0x0002 247 #define ICH_DEBUG_INTR 0x0004 248 #else 249 #define DPRINTF(x,y) /* nothing */ 250 #endif 251 252 static int auich_match(struct device *, struct cfdata *, void *); 253 static void auich_attach(struct device *, struct device *, void *); 254 static int auich_detach(struct device *, int); 255 static int auich_activate(struct device *, enum devact); 256 static int auich_intr(void *); 257 258 CFATTACH_DECL(auich, sizeof(struct auich_softc), 259 auich_match, auich_attach, auich_detach, auich_activate); 260 261 static int auich_open(void *, int); 262 static void auich_close(void *); 263 static int auich_query_encoding(void *, struct audio_encoding *); 264 static int auich_set_params(void *, int, int, audio_params_t *, 265 audio_params_t *, stream_filter_list_t *, 266 stream_filter_list_t *); 267 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 268 static void auich_halt_pipe(struct auich_softc *, int); 269 static int auich_halt_output(void *); 270 static int auich_halt_input(void *); 271 static int auich_getdev(void *, struct audio_device *); 272 static int auich_set_port(void *, mixer_ctrl_t *); 273 static int auich_get_port(void *, mixer_ctrl_t *); 274 static int auich_query_devinfo(void *, mixer_devinfo_t *); 275 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 276 static void auich_freem(void *, void *, struct malloc_type *); 277 static size_t auich_round_buffersize(void *, int, size_t); 278 static paddr_t auich_mappage(void *, void *, off_t, int); 279 static int auich_get_props(void *); 280 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 281 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 282 static int auich_trigger_output(void *, void *, void *, int, 283 void (*)(void *), void *, const audio_params_t *); 284 static int auich_trigger_input(void *, void *, void *, int, 285 void (*)(void *), void *, const audio_params_t *); 286 static int auich_powerstate(void *, int); 287 288 static int auich_alloc_cdata(struct auich_softc *); 289 290 static int auich_allocmem(struct auich_softc *, size_t, size_t, 291 struct auich_dma *); 292 static int auich_freemem(struct auich_softc *, struct auich_dma *); 293 294 static void auich_powerhook(int, void *); 295 static int auich_set_rate(struct auich_softc *, int, u_long); 296 static int auich_sysctl_verify(SYSCTLFN_ARGS); 297 static void auich_finish_attach(struct device *); 298 static void auich_calibrate(struct auich_softc *); 299 static void auich_clear_cas(struct auich_softc *); 300 301 static int auich_attach_codec(void *, struct ac97_codec_if *); 302 static int auich_read_codec(void *, uint8_t, uint16_t *); 303 static int auich_write_codec(void *, uint8_t, uint16_t); 304 static int auich_reset_codec(void *); 305 static enum ac97_host_flags auich_flags_codec(void *); 306 static void auich_spdif_event(void *, boolean_t); 307 308 static const struct audio_hw_if auich_hw_if = { 309 auich_open, 310 auich_close, 311 NULL, /* drain */ 312 auich_query_encoding, 313 auich_set_params, 314 auich_round_blocksize, 315 NULL, /* commit_setting */ 316 NULL, /* init_output */ 317 NULL, /* init_input */ 318 NULL, /* start_output */ 319 NULL, /* start_input */ 320 auich_halt_output, 321 auich_halt_input, 322 NULL, /* speaker_ctl */ 323 auich_getdev, 324 NULL, /* getfd */ 325 auich_set_port, 326 auich_get_port, 327 auich_query_devinfo, 328 auich_allocm, 329 auich_freem, 330 auich_round_buffersize, 331 auich_mappage, 332 auich_get_props, 333 auich_trigger_output, 334 auich_trigger_input, 335 NULL, /* dev_ioctl */ 336 auich_powerstate, 337 }; 338 339 #define AUICH_FORMATS_1CH 0 340 #define AUICH_FORMATS_4CH 1 341 #define AUICH_FORMATS_6CH 2 342 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 343 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 344 2, AUFMT_STEREO, 0, {8000, 48000}}, 345 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 346 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 347 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 348 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 349 }; 350 351 #define AUICH_SPDIF_NFORMATS 1 352 static const struct audio_format auich_spdif_formats[AUICH_SPDIF_NFORMATS] = { 353 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 354 2, AUFMT_STEREO, 1, {48000}}, 355 }; 356 357 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 358 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 359 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 360 }; 361 362 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 363 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 364 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 365 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 366 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 367 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 368 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 369 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 370 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 371 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 372 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 373 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 374 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 375 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 376 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 377 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 378 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 379 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 380 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 381 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 382 383 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 384 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 385 386 struct auich_devtype { 387 pcireg_t id; 388 const char *name; 389 const char *shortname; /* must be less than 11 characters */ 390 }; 391 392 static const struct auich_devtype auich_audio_devices[] = { 393 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 394 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 395 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 396 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 397 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 398 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 399 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 400 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 401 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 402 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 403 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 404 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 405 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 406 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 407 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 408 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 409 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 410 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 411 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 412 { 0, NULL, NULL }, 413 }; 414 415 static const struct auich_devtype auich_modem_devices[] = { 416 #ifdef AUICH_ATTACH_MODEM 417 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 418 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 419 #endif 420 { 0, NULL, NULL }, 421 }; 422 423 static const struct auich_devtype * 424 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 425 { 426 const struct auich_devtype *d; 427 428 for (d = auich_devices; d->name != NULL; d++) { 429 if (pa->pa_id == d->id) 430 return d; 431 } 432 433 return NULL; 434 } 435 436 static int 437 auich_match(struct device *parent, struct cfdata *match, void *aux) 438 { 439 struct pci_attach_args *pa; 440 441 pa = aux; 442 if (auich_lookup(pa, auich_audio_devices) != NULL) 443 return 1; 444 if (auich_lookup(pa, auich_modem_devices) != NULL) 445 return 1; 446 447 return 0; 448 } 449 450 static void 451 auich_attach(struct device *parent, struct device *self, void *aux) 452 { 453 struct auich_softc *sc; 454 struct pci_attach_args *pa; 455 pcireg_t v, subdev; 456 const char *intrstr; 457 const struct auich_devtype *d; 458 const struct sysctlnode *node, *node_ac97clock; 459 int err, node_mib, i; 460 461 sc = (struct auich_softc *)self; 462 pa = aux; 463 464 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 465 sc->sc_modem_offset = 0x10; 466 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 467 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 468 sc->sc_modem_offset = 0; 469 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 470 } else 471 panic("auich_attach: impossible"); 472 473 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 474 aprint_naive(": Audio controller\n"); 475 else 476 aprint_naive(": Modem controller\n"); 477 478 sc->sc_pc = pa->pa_pc; 479 sc->sc_pt = pa->pa_tag; 480 481 aprint_normal(": %s\n", d->name); 482 483 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 484 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 485 || d->id == PCIID_ICH4MODEM) { 486 /* 487 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 488 */ 489 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 490 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 491 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 492 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 493 v | ICH_CFG_IOSE); 494 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 495 0, &sc->iot, &sc->mix_ioh, NULL, 496 &sc->mix_size)) { 497 aprint_error("%s: can't map codec i/o space\n", 498 sc->sc_dev.dv_xname); 499 return; 500 } 501 } 502 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 503 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 504 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 505 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 506 v | ICH_CFG_IOSE); 507 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 508 0, &sc->iot, &sc->aud_ioh, NULL, 509 &sc->aud_size)) { 510 aprint_error("%s: can't map device i/o space\n", 511 sc->sc_dev.dv_xname); 512 return; 513 } 514 } 515 } else { 516 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 517 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 518 aprint_error("%s: can't map codec i/o space\n", 519 sc->sc_dev.dv_xname); 520 return; 521 } 522 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 523 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 524 aprint_error("%s: can't map device i/o space\n", 525 sc->sc_dev.dv_xname); 526 return; 527 } 528 } 529 sc->dmat = pa->pa_dmat; 530 531 /* enable bus mastering */ 532 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 533 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 534 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 535 536 /* Map and establish the interrupt. */ 537 if (pci_intr_map(pa, &sc->intrh)) { 538 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 539 return; 540 } 541 intrstr = pci_intr_string(pa->pa_pc, sc->intrh); 542 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO, 543 auich_intr, sc); 544 if (sc->sc_ih == NULL) { 545 aprint_error("%s: can't establish interrupt", 546 sc->sc_dev.dv_xname); 547 if (intrstr != NULL) 548 aprint_normal(" at %s", intrstr); 549 aprint_normal("\n"); 550 return; 551 } 552 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 553 554 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 555 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 556 "0x%02x", PCI_REVISION(pa->pa_class)); 557 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 558 559 /* SiS 7012 needs special handling */ 560 if (d->id == PCIID_SIS7012) { 561 sc->sc_sts_reg = ICH_PICB; 562 sc->sc_sample_shift = 0; 563 /* Un-mute output. From Linux. */ 564 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 565 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 566 ICH_SIS_CTL_UNMUTE); 567 } else { 568 sc->sc_sts_reg = ICH_STS; 569 sc->sc_sample_shift = 1; 570 } 571 572 /* Workaround for a 440MX B-stepping erratum */ 573 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 574 if (d->id == PCIID_440MX) { 575 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 576 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 577 } 578 579 /* Set up DMA lists. */ 580 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 581 auich_alloc_cdata(sc); 582 583 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 584 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 585 586 /* Modem codecs are always the secondary codec on ICH */ 587 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 588 589 sc->host_if.arg = sc; 590 sc->host_if.attach = auich_attach_codec; 591 sc->host_if.read = auich_read_codec; 592 sc->host_if.write = auich_write_codec; 593 sc->host_if.reset = auich_reset_codec; 594 sc->host_if.flags = auich_flags_codec; 595 sc->host_if.spdif_event = auich_spdif_event; 596 597 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 598 switch (subdev) { 599 case 0x202f161f: /* Gateway 7326GZ */ 600 case 0x203a161f: /* Gateway 4028GZ */ 601 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 602 case 0x8144104d: /* Sony VAIO PCG-TR* */ 603 case 0x8197104d: /* Sony S1XP */ 604 case 0x81c0104d: /* Sony VAIO type T */ 605 case 0x81c5104d: /* Sony VAIO VGN-B1XP */ 606 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP; 607 break; 608 default: 609 sc->sc_codecflags = 0; 610 break; 611 } 612 613 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 614 return; 615 sc->codec_if->vtbl->unlock(sc->codec_if); 616 617 /* setup audio_format */ 618 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 619 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 620 if (!AC97_IS_4CH(sc->codec_if)) 621 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 622 if (!AC97_IS_6CH(sc->codec_if)) 623 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 624 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 625 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 626 sc->sc_audio_formats[i].frequency_type = 1; 627 sc->sc_audio_formats[i].frequency[0] = 48000; 628 } 629 } 630 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 631 &sc->sc_encodings)) 632 return; 633 if (0 != auconv_create_encodings(auich_spdif_formats, AUICH_SPDIF_NFORMATS, 634 &sc->sc_spdif_encodings)) 635 return; 636 } else { 637 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 638 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 639 &sc->sc_encodings)) 640 return; 641 } 642 643 644 /* Watch for power change */ 645 sc->sc_suspend = PWR_RESUME; 646 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 647 648 config_interrupts(self, auich_finish_attach); 649 650 /* sysctl setup */ 651 if (AC97_IS_FIXED_RATE(sc->codec_if) && 652 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 653 return; 654 655 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 656 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 657 CTL_HW, CTL_EOL); 658 if (err != 0) 659 goto sysctl_err; 660 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 661 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 662 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 663 if (err != 0) 664 goto sysctl_err; 665 node_mib = node->sysctl_num; 666 667 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 668 /* passing the sc address instead of &sc->sc_ac97_clock */ 669 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 670 CTLFLAG_READWRITE, 671 CTLTYPE_INT, "ac97rate", 672 SYSCTL_DESCR("AC'97 codec link rate"), 673 auich_sysctl_verify, 0, sc, 0, 674 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 675 if (err != 0) 676 goto sysctl_err; 677 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 678 } 679 680 return; 681 682 sysctl_err: 683 printf("%s: failed to add sysctl nodes. (%d)\n", 684 sc->sc_dev.dv_xname, err); 685 return; /* failure of sysctl is not fatal. */ 686 } 687 688 static int 689 auich_activate(struct device *self, enum devact act) 690 { 691 struct auich_softc *sc; 692 int ret; 693 694 sc = (struct auich_softc *)self; 695 ret = 0; 696 switch (act) { 697 case DVACT_ACTIVATE: 698 return EOPNOTSUPP; 699 case DVACT_DEACTIVATE: 700 if (sc->sc_audiodev != NULL) 701 ret = config_deactivate(sc->sc_audiodev); 702 return ret; 703 } 704 return EOPNOTSUPP; 705 } 706 707 static int 708 auich_detach(struct device *self, int flags) 709 { 710 struct auich_softc *sc; 711 712 sc = (struct auich_softc *)self; 713 714 /* audio */ 715 if (sc->sc_audiodev != NULL) 716 config_detach(sc->sc_audiodev, flags); 717 718 /* sysctl */ 719 sysctl_teardown(&sc->sc_log); 720 721 /* audio_encoding_set */ 722 auconv_delete_encodings(sc->sc_encodings); 723 auconv_delete_encodings(sc->sc_spdif_encodings); 724 725 /* ac97 */ 726 if (sc->codec_if != NULL) 727 sc->codec_if->vtbl->detach(sc->codec_if); 728 729 /* PCI */ 730 if (sc->sc_ih != NULL) 731 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 732 if (sc->mix_size != 0) 733 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 734 if (sc->aud_size != 0) 735 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 736 return 0; 737 } 738 739 static int 740 auich_sysctl_verify(SYSCTLFN_ARGS) 741 { 742 int error, tmp; 743 struct sysctlnode node; 744 struct auich_softc *sc; 745 746 node = *rnode; 747 sc = rnode->sysctl_data; 748 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 749 tmp = sc->sc_ac97_clock; 750 node.sysctl_data = &tmp; 751 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 752 if (error || newp == NULL) 753 return error; 754 755 if (tmp < 48000 || tmp > 96000) 756 return EINVAL; 757 sc->sc_ac97_clock = tmp; 758 } 759 760 return 0; 761 } 762 763 static void 764 auich_finish_attach(struct device *self) 765 { 766 struct auich_softc *sc; 767 768 sc = (void *)self; 769 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 770 auich_calibrate(sc); 771 772 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 773 774 #if notyet 775 auich_powerhook(PWR_SUSPEND, sc); 776 #endif 777 778 return; 779 } 780 781 #define ICH_CODECIO_INTERVAL 10 782 static int 783 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 784 { 785 struct auich_softc *sc; 786 int i; 787 uint32_t status; 788 789 sc = v; 790 /* wait for an access semaphore */ 791 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 792 bus_space_read_1(sc->iot, sc->aud_ioh, 793 ICH_CAS + sc->sc_modem_offset) & 1; 794 DELAY(ICH_CODECIO_INTERVAL)); 795 796 if (i > 0) { 797 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 798 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 799 DPRINTF(ICH_DEBUG_CODECIO, 800 ("auich_read_codec(%x, %x)\n", reg, *val)); 801 status = bus_space_read_4(sc->iot, sc->aud_ioh, 802 ICH_GSTS + sc->sc_modem_offset); 803 if (status & ICH_RCS) { 804 bus_space_write_4(sc->iot, sc->aud_ioh, 805 ICH_GSTS + sc->sc_modem_offset, 806 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 807 *val = 0xffff; 808 DPRINTF(ICH_DEBUG_CODECIO, 809 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 810 if (reg == AC97_REG_GPIO_STATUS) 811 auich_clear_cas(sc); 812 return -1; 813 } 814 if (reg == AC97_REG_GPIO_STATUS) 815 auich_clear_cas(sc); 816 return 0; 817 } else { 818 aprint_normal("%s: read_codec timeout\n", sc->sc_dev.dv_xname); 819 if (reg == AC97_REG_GPIO_STATUS) 820 auich_clear_cas(sc); 821 return -1; 822 } 823 } 824 825 static int 826 auich_write_codec(void *v, uint8_t reg, uint16_t val) 827 { 828 struct auich_softc *sc; 829 int i; 830 831 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 832 sc = v; 833 /* wait for an access semaphore */ 834 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 835 bus_space_read_1(sc->iot, sc->aud_ioh, 836 ICH_CAS + sc->sc_modem_offset) & 1; 837 DELAY(ICH_CODECIO_INTERVAL)); 838 839 if (i > 0) { 840 bus_space_write_2(sc->iot, sc->mix_ioh, 841 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 842 return 0; 843 } else { 844 aprint_normal("%s: write_codec timeout\n", sc->sc_dev.dv_xname); 845 return -1; 846 } 847 } 848 849 static int 850 auich_attach_codec(void *v, struct ac97_codec_if *cif) 851 { 852 struct auich_softc *sc; 853 854 sc = v; 855 sc->codec_if = cif; 856 857 return 0; 858 } 859 860 static int 861 auich_reset_codec(void *v) 862 { 863 struct auich_softc *sc; 864 int i; 865 uint32_t control, status; 866 867 sc = v; 868 control = bus_space_read_4(sc->iot, sc->aud_ioh, 869 ICH_GCTRL + sc->sc_modem_offset); 870 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 871 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 872 } else { 873 control &= ~ICH_ACLSO; 874 control |= ICH_GIE; 875 } 876 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 877 bus_space_write_4(sc->iot, sc->aud_ioh, 878 ICH_GCTRL + sc->sc_modem_offset, control); 879 880 for (i = 500000; i >= 0; i--) { 881 status = bus_space_read_4(sc->iot, sc->aud_ioh, 882 ICH_GSTS + sc->sc_modem_offset); 883 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 884 break; 885 DELAY(1); 886 } 887 if (i <= 0) { 888 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 889 return ETIMEDOUT; 890 } 891 #ifdef AUICH_DEBUG 892 if (status & ICH_SCR) 893 printf("%s: The 2nd codec is ready.\n", 894 sc->sc_dev.dv_xname); 895 if (status & ICH_S2CR) 896 printf("%s: The 3rd codec is ready.\n", 897 sc->sc_dev.dv_xname); 898 #endif 899 return 0; 900 } 901 902 static enum ac97_host_flags 903 auich_flags_codec(void *v) 904 { 905 struct auich_softc *sc = v; 906 return sc->sc_codecflags; 907 } 908 909 static void 910 auich_spdif_event(void *addr, boolean_t flag) 911 { 912 struct auich_softc *sc; 913 914 sc = addr; 915 sc->sc_spdif = flag; 916 } 917 918 static int 919 auich_open(void *addr, int flags) 920 { 921 struct auich_softc *sc; 922 923 sc = (struct auich_softc *)addr; 924 sc->codec_if->vtbl->lock(sc->codec_if); 925 return 0; 926 } 927 928 static void 929 auich_close(void *addr) 930 { 931 struct auich_softc *sc; 932 933 sc = (struct auich_softc *)addr; 934 sc->codec_if->vtbl->unlock(sc->codec_if); 935 } 936 937 static int 938 auich_query_encoding(void *v, struct audio_encoding *aep) 939 { 940 struct auich_softc *sc; 941 942 sc = (struct auich_softc *)v; 943 return auconv_query_encoding( 944 sc->sc_spdif ? sc->sc_spdif_encodings : sc->sc_encodings, aep); 945 } 946 947 static int 948 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 949 { 950 int ret; 951 u_int ratetmp; 952 953 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 954 ratetmp = srate; 955 if (mode == AUMODE_RECORD) 956 return sc->codec_if->vtbl->set_rate(sc->codec_if, 957 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 958 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 959 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 960 if (ret) 961 return ret; 962 ratetmp = srate; 963 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 964 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 965 if (ret) 966 return ret; 967 ratetmp = srate; 968 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 969 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 970 return ret; 971 } 972 973 static int 974 auich_set_params(void *v, int setmode, int usemode, audio_params_t *play, 975 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 976 { 977 struct auich_softc *sc; 978 audio_params_t *p; 979 stream_filter_list_t *fil; 980 int mode, index; 981 uint32_t control; 982 983 sc = v; 984 for (mode = AUMODE_RECORD; mode != -1; 985 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 986 if ((setmode & mode) == 0) 987 continue; 988 989 p = mode == AUMODE_PLAY ? play : rec; 990 fil = mode == AUMODE_PLAY ? pfil : rfil; 991 if (p == NULL) 992 continue; 993 994 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 995 if (p->sample_rate < 8000 || 996 p->sample_rate > 48000) 997 return EINVAL; 998 999 if (sc->sc_spdif) 1000 index = auconv_set_converter(sc->sc_audio_formats, 1001 AUICH_AUDIO_NFORMATS, mode, p, TRUE, fil); 1002 else 1003 index = auconv_set_converter(auich_spdif_formats, 1004 AUICH_SPDIF_NFORMATS, mode, p, TRUE, fil); 1005 } else { 1006 if (p->sample_rate != 8000 && p->sample_rate != 16000) 1007 return EINVAL; 1008 index = auconv_set_converter(sc->sc_modem_formats, 1009 AUICH_MODEM_NFORMATS, mode, p, TRUE, fil); 1010 } 1011 if (index < 0) 1012 return EINVAL; 1013 if (fil->req_size > 0) 1014 p = &fil->filters[0].param; 1015 /* p represents HW encoding */ 1016 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1017 if (sc->sc_audio_formats[index].frequency_type != 1 1018 && auich_set_rate(sc, mode, p->sample_rate)) 1019 return EINVAL; 1020 } else { 1021 if (sc->sc_modem_formats[index].frequency_type != 1 1022 && auich_set_rate(sc, mode, p->sample_rate)) 1023 return EINVAL; 1024 auich_write_codec(sc, AC97_REG_LINE1_RATE, 1025 p->sample_rate); 1026 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 1027 } 1028 if (mode == AUMODE_PLAY && 1029 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1030 control = bus_space_read_4(sc->iot, sc->aud_ioh, 1031 ICH_GCTRL + sc->sc_modem_offset); 1032 control &= ~ICH_PCM246_MASK; 1033 if (p->channels == 4) { 1034 control |= ICH_PCM4; 1035 } else if (p->channels == 6) { 1036 control |= ICH_PCM6; 1037 } 1038 bus_space_write_4(sc->iot, sc->aud_ioh, 1039 ICH_GCTRL + sc->sc_modem_offset, control); 1040 } 1041 } 1042 1043 return 0; 1044 } 1045 1046 static int 1047 auich_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 1048 { 1049 1050 return blk & ~0x3f; /* keep good alignment */ 1051 } 1052 1053 static void 1054 auich_halt_pipe(struct auich_softc *sc, int pipe) 1055 { 1056 int i; 1057 uint32_t status; 1058 1059 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 1060 for (i = 0; i < 100; i++) { 1061 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 1062 if (status & ICH_DCH) 1063 break; 1064 DELAY(1); 1065 } 1066 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 1067 1068 #if AUICH_DEBUG 1069 if (i > 0) 1070 printf("auich_halt_pipe: halt took %d cycles\n", i); 1071 #endif 1072 } 1073 1074 static int 1075 auich_halt_output(void *v) 1076 { 1077 struct auich_softc *sc; 1078 1079 sc = v; 1080 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 1081 1082 auich_halt_pipe(sc, ICH_PCMO); 1083 sc->pcmo.intr = NULL; 1084 1085 return 0; 1086 } 1087 1088 static int 1089 auich_halt_input(void *v) 1090 { 1091 struct auich_softc *sc; 1092 1093 sc = v; 1094 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", sc->sc_dev.dv_xname)); 1095 1096 auich_halt_pipe(sc, ICH_PCMI); 1097 sc->pcmi.intr = NULL; 1098 1099 return 0; 1100 } 1101 1102 static int 1103 auich_getdev(void *v, struct audio_device *adp) 1104 { 1105 struct auich_softc *sc; 1106 1107 sc = v; 1108 *adp = sc->sc_audev; 1109 return 0; 1110 } 1111 1112 static int 1113 auich_set_port(void *v, mixer_ctrl_t *cp) 1114 { 1115 struct auich_softc *sc; 1116 1117 sc = v; 1118 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1119 } 1120 1121 static int 1122 auich_get_port(void *v, mixer_ctrl_t *cp) 1123 { 1124 struct auich_softc *sc; 1125 1126 sc = v; 1127 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1128 } 1129 1130 static int 1131 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1132 { 1133 struct auich_softc *sc; 1134 1135 sc = v; 1136 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1137 } 1138 1139 static void * 1140 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 1141 int flags) 1142 { 1143 struct auich_softc *sc; 1144 struct auich_dma *p; 1145 int error; 1146 1147 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1148 return NULL; 1149 1150 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1151 if (p == NULL) 1152 return NULL; 1153 1154 sc = v; 1155 error = auich_allocmem(sc, size, 0, p); 1156 if (error) { 1157 free(p, pool); 1158 return NULL; 1159 } 1160 1161 p->next = sc->sc_dmas; 1162 sc->sc_dmas = p; 1163 1164 return KERNADDR(p); 1165 } 1166 1167 static void 1168 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1169 { 1170 struct auich_softc *sc; 1171 struct auich_dma *p, **pp; 1172 1173 sc = v; 1174 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1175 if (KERNADDR(p) == ptr) { 1176 auich_freemem(sc, p); 1177 *pp = p->next; 1178 free(p, pool); 1179 return; 1180 } 1181 } 1182 } 1183 1184 static size_t 1185 auich_round_buffersize(void *v, int direction, size_t size) 1186 { 1187 1188 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1189 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1190 1191 return size; 1192 } 1193 1194 static paddr_t 1195 auich_mappage(void *v, void *mem, off_t off, int prot) 1196 { 1197 struct auich_softc *sc; 1198 struct auich_dma *p; 1199 1200 if (off < 0) 1201 return -1; 1202 sc = v; 1203 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1204 continue; 1205 if (!p) 1206 return -1; 1207 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1208 off, prot, BUS_DMA_WAITOK); 1209 } 1210 1211 static int 1212 auich_get_props(void *v) 1213 { 1214 struct auich_softc *sc; 1215 int props; 1216 1217 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1218 sc = v; 1219 /* 1220 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1221 * rate because of aurateconv. Applications can't know what rate the 1222 * device can process in the case of mmap(). 1223 */ 1224 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1225 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1226 props |= AUDIO_PROP_MMAP; 1227 return props; 1228 } 1229 1230 static int 1231 auich_intr(void *v) 1232 { 1233 struct auich_softc *sc; 1234 int ret, gsts; 1235 #ifdef DIAGNOSTIC 1236 int csts; 1237 #endif 1238 1239 sc = v; 1240 ret = 0; 1241 #ifdef DIAGNOSTIC 1242 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1243 if (csts & PCI_STATUS_MASTER_ABORT) { 1244 printf("auich_intr: PCI master abort\n"); 1245 } 1246 #endif 1247 1248 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1249 ICH_GSTS + sc->sc_modem_offset); 1250 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1251 1252 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1253 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1254 int sts; 1255 1256 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1257 ICH_PCMO + sc->sc_sts_reg); 1258 DPRINTF(ICH_DEBUG_INTR, 1259 ("auich_intr: osts=0x%x\n", sts)); 1260 1261 if (sts & ICH_FIFOE) 1262 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1263 1264 if (sts & ICH_BCIS) 1265 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1266 1267 /* int ack */ 1268 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1269 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1270 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1271 bus_space_write_4(sc->iot, sc->aud_ioh, 1272 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1273 else 1274 bus_space_write_4(sc->iot, sc->aud_ioh, 1275 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1276 ret++; 1277 } 1278 1279 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1280 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1281 int sts; 1282 1283 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1284 ICH_PCMI + sc->sc_sts_reg); 1285 DPRINTF(ICH_DEBUG_INTR, 1286 ("auich_intr: ists=0x%x\n", sts)); 1287 1288 if (sts & ICH_FIFOE) 1289 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1290 1291 if (sts & ICH_BCIS) 1292 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1293 1294 /* int ack */ 1295 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1296 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1297 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1298 bus_space_write_4(sc->iot, sc->aud_ioh, 1299 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1300 else 1301 bus_space_write_4(sc->iot, sc->aud_ioh, 1302 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1303 ret++; 1304 } 1305 1306 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1307 int sts; 1308 1309 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1310 ICH_MICI + sc->sc_sts_reg); 1311 DPRINTF(ICH_DEBUG_INTR, 1312 ("auich_intr: ists=0x%x\n", sts)); 1313 1314 if (sts & ICH_FIFOE) 1315 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1316 1317 if (sts & ICH_BCIS) 1318 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1319 1320 /* int ack */ 1321 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1322 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1323 bus_space_write_4(sc->iot, sc->aud_ioh, 1324 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1325 ret++; 1326 } 1327 1328 #ifdef AUICH_MODEM_DEBUG 1329 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1330 printf("%s: gsts=0x%x\n", sc->sc_dev.dv_xname, gsts); 1331 /* int ack */ 1332 bus_space_write_4(sc->iot, sc->aud_ioh, 1333 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1334 ret++; 1335 } 1336 #endif 1337 1338 return ret; 1339 } 1340 1341 static void 1342 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1343 { 1344 int blksize, qptr; 1345 struct auich_dmalist *q; 1346 1347 blksize = ring->blksize; 1348 1349 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1350 q = &ring->dmalist[qptr]; 1351 q->base = ring->p; 1352 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1353 1354 ring->p += blksize; 1355 if (ring->p >= ring->end) 1356 ring->p = ring->start; 1357 } 1358 ring->qptr = 0; 1359 1360 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1361 (qptr - 1) & ICH_LVI_MASK); 1362 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1363 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1364 } 1365 1366 static void 1367 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1368 { 1369 int blksize, qptr, nqptr; 1370 struct auich_dmalist *q; 1371 1372 blksize = ring->blksize; 1373 qptr = ring->qptr; 1374 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1375 1376 while (qptr != nqptr) { 1377 q = &ring->dmalist[qptr]; 1378 q->base = ring->p; 1379 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1380 1381 DPRINTF(ICH_DEBUG_INTR, 1382 ("auich_intr: %p, %p = %x @ 0x%x\n", 1383 &ring->dmalist[qptr], q, q->len, q->base)); 1384 1385 ring->p += blksize; 1386 if (ring->p >= ring->end) 1387 ring->p = ring->start; 1388 1389 qptr = (qptr + 1) & ICH_LVI_MASK; 1390 if (ring->intr) 1391 ring->intr(ring->arg); 1392 } 1393 ring->qptr = qptr; 1394 1395 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1396 (qptr - 1) & ICH_LVI_MASK); 1397 } 1398 1399 static int 1400 auich_trigger_output(void *v, void *start, void *end, int blksize, 1401 void (*intr)(void *), void *arg, const audio_params_t *param) 1402 { 1403 struct auich_softc *sc; 1404 struct auich_dma *p; 1405 size_t size; 1406 1407 DPRINTF(ICH_DEBUG_DMA, 1408 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1409 start, end, blksize, intr, arg, param)); 1410 sc = v; 1411 1412 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1413 continue; 1414 if (!p) { 1415 printf("auich_trigger_output: bad addr %p\n", start); 1416 return EINVAL; 1417 } 1418 1419 size = (size_t)((caddr_t)end - (caddr_t)start); 1420 1421 sc->pcmo.intr = intr; 1422 sc->pcmo.arg = arg; 1423 sc->pcmo.start = DMAADDR(p); 1424 sc->pcmo.p = sc->pcmo.start; 1425 sc->pcmo.end = sc->pcmo.start + size; 1426 sc->pcmo.blksize = blksize; 1427 1428 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1429 sc->sc_cddma + ICH_PCMO_OFF(0)); 1430 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1431 1432 return 0; 1433 } 1434 1435 static int 1436 auich_trigger_input(void *v, void *start, void *end, int blksize, 1437 void (*intr)(void *), void *arg, const audio_params_t *param) 1438 { 1439 struct auich_softc *sc; 1440 struct auich_dma *p; 1441 size_t size; 1442 1443 DPRINTF(ICH_DEBUG_DMA, 1444 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1445 start, end, blksize, intr, arg, param)); 1446 sc = v; 1447 1448 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1449 continue; 1450 if (!p) { 1451 printf("auich_trigger_input: bad addr %p\n", start); 1452 return EINVAL; 1453 } 1454 1455 size = (size_t)((caddr_t)end - (caddr_t)start); 1456 1457 sc->pcmi.intr = intr; 1458 sc->pcmi.arg = arg; 1459 sc->pcmi.start = DMAADDR(p); 1460 sc->pcmi.p = sc->pcmi.start; 1461 sc->pcmi.end = sc->pcmi.start + size; 1462 sc->pcmi.blksize = blksize; 1463 1464 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1465 sc->sc_cddma + ICH_PCMI_OFF(0)); 1466 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1467 1468 return 0; 1469 } 1470 1471 static int 1472 auich_powerstate(void *v, int state) 1473 { 1474 #if notyet 1475 struct auich_softc *sc; 1476 int rv; 1477 1478 sc = (struct auich_softc *)v; 1479 rv = 0; 1480 1481 switch (state) { 1482 case AUDIOPOWER_OFF: 1483 auich_powerhook(PWR_SUSPEND, sc); 1484 break; 1485 case AUDIOPOWER_ON: 1486 auich_powerhook(PWR_RESUME, sc); 1487 break; 1488 default: 1489 aprint_error("%s: unknown power state %d\n", 1490 sc->sc_dev.dv_xname, state); 1491 rv = 1; 1492 break; 1493 } 1494 1495 return rv; 1496 #else 1497 return 0; 1498 #endif 1499 } 1500 1501 static int 1502 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1503 struct auich_dma *p) 1504 { 1505 int error; 1506 1507 p->size = size; 1508 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1509 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1510 &p->nsegs, BUS_DMA_NOWAIT); 1511 if (error) 1512 return error; 1513 1514 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1515 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1516 if (error) 1517 goto free; 1518 1519 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1520 0, BUS_DMA_NOWAIT, &p->map); 1521 if (error) 1522 goto unmap; 1523 1524 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1525 BUS_DMA_NOWAIT); 1526 if (error) 1527 goto destroy; 1528 return 0; 1529 1530 destroy: 1531 bus_dmamap_destroy(sc->dmat, p->map); 1532 unmap: 1533 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1534 free: 1535 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1536 return error; 1537 } 1538 1539 static int 1540 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1541 { 1542 1543 bus_dmamap_unload(sc->dmat, p->map); 1544 bus_dmamap_destroy(sc->dmat, p->map); 1545 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1546 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1547 return 0; 1548 } 1549 1550 static int 1551 auich_alloc_cdata(struct auich_softc *sc) 1552 { 1553 bus_dma_segment_t seg; 1554 int error, rseg; 1555 1556 /* 1557 * Allocate the control data structure, and create and load the 1558 * DMA map for it. 1559 */ 1560 if ((error = bus_dmamem_alloc(sc->dmat, 1561 sizeof(struct auich_cdata), 1562 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1563 printf("%s: unable to allocate control data, error = %d\n", 1564 sc->sc_dev.dv_xname, error); 1565 goto fail_0; 1566 } 1567 1568 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1569 sizeof(struct auich_cdata), 1570 (caddr_t *) &sc->sc_cdata, 1571 sc->sc_dmamap_flags)) != 0) { 1572 printf("%s: unable to map control data, error = %d\n", 1573 sc->sc_dev.dv_xname, error); 1574 goto fail_1; 1575 } 1576 1577 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1578 sizeof(struct auich_cdata), 0, 0, 1579 &sc->sc_cddmamap)) != 0) { 1580 printf("%s: unable to create control data DMA map, " 1581 "error = %d\n", sc->sc_dev.dv_xname, error); 1582 goto fail_2; 1583 } 1584 1585 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1586 sc->sc_cdata, sizeof(struct auich_cdata), 1587 NULL, 0)) != 0) { 1588 printf("%s: unable tp load control data DMA map, " 1589 "error = %d\n", sc->sc_dev.dv_xname, error); 1590 goto fail_3; 1591 } 1592 1593 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1594 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1595 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1596 1597 return 0; 1598 1599 fail_3: 1600 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1601 fail_2: 1602 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1603 sizeof(struct auich_cdata)); 1604 fail_1: 1605 bus_dmamem_free(sc->dmat, &seg, rseg); 1606 fail_0: 1607 return error; 1608 } 1609 1610 static void 1611 auich_powerhook(int why, void *addr) 1612 { 1613 struct auich_softc *sc; 1614 int rv; 1615 1616 sc = (struct auich_softc *)addr; 1617 switch (why) { 1618 case PWR_SUSPEND: 1619 case PWR_STANDBY: 1620 /* Power down */ 1621 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1622 1623 /* if we're already asleep, don't try to sleep again */ 1624 if (sc->sc_suspend == PWR_SUSPEND || 1625 sc->sc_suspend == PWR_STANDBY) 1626 break; 1627 sc->sc_suspend = why; 1628 1629 DELAY(1000); 1630 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1631 1632 if (sc->sc_ih != NULL) 1633 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1634 1635 rv = pci_get_powerstate(sc->sc_pc, sc->sc_pt, &sc->sc_powerstate); 1636 if (rv) 1637 aprint_error("%s: unable to get power state (err=%d)\n", 1638 sc->sc_dev.dv_xname, rv); 1639 rv = pci_set_powerstate(sc->sc_pc, sc->sc_pt, PCI_PMCSR_STATE_D3); 1640 if (rv) 1641 aprint_error("%s: unable to set power state (err=%d)\n", 1642 sc->sc_dev.dv_xname, rv); 1643 1644 break; 1645 1646 case PWR_RESUME: 1647 /* Wake up */ 1648 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1649 if (sc->sc_suspend == PWR_RESUME) { 1650 printf("%s: resume without suspend.\n", 1651 sc->sc_dev.dv_xname); 1652 sc->sc_suspend = why; 1653 return; 1654 } 1655 1656 rv = pci_set_powerstate(sc->sc_pc, sc->sc_pt, sc->sc_powerstate); 1657 if (rv) 1658 aprint_error("%s: unable to set power state (err=%d)\n", 1659 sc->sc_dev.dv_xname, rv); 1660 1661 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 1662 auich_intr, sc); 1663 if (sc->sc_ih == NULL) { 1664 aprint_error("%s: can't establish interrupt", 1665 sc->sc_dev.dv_xname); 1666 /* XXX jmcneill what should we do here? */ 1667 return; 1668 } 1669 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1670 sc->sc_suspend = why; 1671 auich_reset_codec(sc); 1672 DELAY(1000); 1673 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1674 break; 1675 1676 case PWR_SOFTSUSPEND: 1677 case PWR_SOFTSTANDBY: 1678 case PWR_SOFTRESUME: 1679 break; 1680 } 1681 } 1682 1683 /* 1684 * Calibrate card (some boards are overclocked and need scaling) 1685 */ 1686 static void 1687 auich_calibrate(struct auich_softc *sc) 1688 { 1689 struct timeval t1, t2; 1690 uint8_t ociv, nciv; 1691 uint64_t wait_us; 1692 uint32_t actual_48k_rate, bytes, ac97rate; 1693 void *temp_buffer; 1694 struct auich_dma *p; 1695 u_int rate; 1696 1697 /* 1698 * Grab audio from input for fixed interval and compare how 1699 * much we actually get with what we expect. Interval needs 1700 * to be sufficiently short that no interrupts are 1701 * generated. 1702 */ 1703 1704 /* Force the codec to a known state first. */ 1705 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1706 rate = sc->sc_ac97_clock = 48000; 1707 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1708 &rate); 1709 1710 /* Setup a buffer */ 1711 bytes = 64000; 1712 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1713 1714 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1715 continue; 1716 if (p == NULL) { 1717 printf("auich_calibrate: bad address %p\n", temp_buffer); 1718 return; 1719 } 1720 sc->pcmi.dmalist[0].base = DMAADDR(p); 1721 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1722 1723 /* 1724 * our data format is stereo, 16 bit so each sample is 4 bytes. 1725 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1726 * we're going to start recording with interrupts disabled and measure 1727 * the time taken for one block to complete. we know the block size, 1728 * we know the time in microseconds, we calculate the sample rate: 1729 * 1730 * actual_rate [bps] = bytes / (time [s] * 4) 1731 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1732 * actual_rate [Hz] = (bytes * 250000) / time [us] 1733 */ 1734 1735 /* prepare */ 1736 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1737 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1738 sc->sc_cddma + ICH_PCMI_OFF(0)); 1739 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1740 (0 - 1) & ICH_LVI_MASK); 1741 1742 /* start */ 1743 microtime(&t1); 1744 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1745 1746 /* wait */ 1747 nciv = ociv; 1748 do { 1749 microtime(&t2); 1750 if (t2.tv_sec - t1.tv_sec > 1) 1751 break; 1752 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1753 ICH_PCMI + ICH_CIV); 1754 } while (nciv == ociv); 1755 microtime(&t2); 1756 1757 /* stop */ 1758 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1759 1760 /* reset */ 1761 DELAY(100); 1762 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1763 1764 /* turn time delta into us */ 1765 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1766 1767 auich_freem(sc, temp_buffer, M_DEVBUF); 1768 1769 if (nciv == ociv) { 1770 printf("%s: ac97 link rate calibration timed out after %" 1771 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1772 return; 1773 } 1774 1775 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1776 1777 if (actual_48k_rate < 50000) 1778 ac97rate = 48000; 1779 else 1780 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1781 1782 printf("%s: measured ac97 link rate at %d Hz", 1783 sc->sc_dev.dv_xname, actual_48k_rate); 1784 if (ac97rate != actual_48k_rate) 1785 printf(", will use %d Hz", ac97rate); 1786 printf("\n"); 1787 1788 sc->sc_ac97_clock = ac97rate; 1789 } 1790 1791 static void 1792 auich_clear_cas(struct auich_softc *sc) 1793 { 1794 /* Clear the codec access semaphore */ 1795 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1796 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1797 1798 return; 1799 } 1800
Indexes created Fri Oct 31 11:10:07 GMT 2025