auich.c revision 1.11
1 /* $NetBSD: auich.c,v 1.11 2002/02/14 12:52:01 augustss Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* #define ICH_DEBUG */ 70 /* 71 * AC'97 audio found on Intel 810/820/440MX chipsets. 72 * http://developer.intel.com/design/chipsets/datashts/290655.htm 73 * http://developer.intel.com/design/chipsets/manuals/298028.htm 74 * 75 * TODO: 76 * 77 * - Probe codecs for supported sample rates. 78 * 79 * - Add support for the microphone input. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.11 2002/02/14 12:52:01 augustss Exp $"); 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/malloc.h> 89 #include <sys/device.h> 90 #include <sys/fcntl.h> 91 #include <sys/proc.h> 92 93 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 94 95 #include <dev/pci/pcidevs.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/auichreg.h> 98 99 #include <sys/audioio.h> 100 #include <dev/audio_if.h> 101 #include <dev/mulaw.h> 102 #include <dev/auconv.h> 103 104 #include <machine/bus.h> 105 106 #include <dev/ic/ac97reg.h> 107 #include <dev/ic/ac97var.h> 108 109 struct auich_dma { 110 bus_dmamap_t map; 111 caddr_t addr; 112 bus_dma_segment_t segs[1]; 113 int nsegs; 114 size_t size; 115 struct auich_dma *next; 116 }; 117 118 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 119 #define KERNADDR(p) ((void *)((p)->addr)) 120 121 struct auich_cdata { 122 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 123 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 124 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 125 }; 126 127 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 128 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 129 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 130 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 131 132 struct auich_softc { 133 struct device sc_dev; 134 void *sc_ih; 135 136 audio_device_t sc_audev; 137 138 bus_space_tag_t iot; 139 bus_space_handle_t mix_ioh; 140 bus_space_handle_t aud_ioh; 141 bus_dma_tag_t dmat; 142 143 struct ac97_codec_if *codec_if; 144 struct ac97_host_if host_if; 145 146 /* DMA scatter-gather lists. */ 147 bus_dmamap_t sc_cddmamap; 148 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 149 150 struct auich_cdata *sc_cdata; 151 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 152 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 153 #define dmalist_mici sc_cdata->ic_dmalist_mici 154 155 int ptr_pcmo, 156 ptr_pcmi, 157 ptr_mici; 158 159 /* i/o buffer pointers */ 160 u_int32_t pcmo_start, pcmo_p, pcmo_end; 161 int pcmo_blksize, pcmo_fifoe; 162 163 u_int32_t pcmi_start, pcmi_p, pcmi_end; 164 int pcmi_blksize, pcmi_fifoe; 165 166 u_int32_t mici_start, mici_p, mici_end; 167 int mici_blksize, mici_fifoe; 168 169 struct auich_dma *sc_dmas; 170 171 int sc_fixed_rate; 172 173 void (*sc_pintr)(void *); 174 void *sc_parg; 175 176 void (*sc_rintr)(void *); 177 void *sc_rarg; 178 179 /* Power Management */ 180 void *sc_powerhook; 181 int sc_suspend; 182 u_int16_t ext_status; 183 }; 184 185 /* Debug */ 186 #ifdef AUDIO_DEBUG 187 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 188 int auich_debug = 0xfffe; 189 #define ICH_DEBUG_CODECIO 0x0001 190 #define ICH_DEBUG_DMA 0x0002 191 #define ICH_DEBUG_PARAM 0x0004 192 #else 193 #define DPRINTF(x,y) /* nothing */ 194 #endif 195 196 int auich_match(struct device *, struct cfdata *, void *); 197 void auich_attach(struct device *, struct device *, void *); 198 int auich_intr(void *); 199 200 struct cfattach auich_ca = { 201 sizeof(struct auich_softc), auich_match, auich_attach 202 }; 203 204 int auich_open(void *, int); 205 void auich_close(void *); 206 int auich_query_encoding(void *, struct audio_encoding *); 207 int auich_set_params(void *, int, int, struct audio_params *, 208 struct audio_params *); 209 int auich_round_blocksize(void *, int); 210 int auich_halt_output(void *); 211 int auich_halt_input(void *); 212 int auich_getdev(void *, struct audio_device *); 213 int auich_set_port(void *, mixer_ctrl_t *); 214 int auich_get_port(void *, mixer_ctrl_t *); 215 int auich_query_devinfo(void *, mixer_devinfo_t *); 216 void *auich_allocm(void *, int, size_t, int, int); 217 void auich_freem(void *, void *, int); 218 size_t auich_round_buffersize(void *, int, size_t); 219 paddr_t auich_mappage(void *, void *, off_t, int); 220 int auich_get_props(void *); 221 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 222 void *, struct audio_params *); 223 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 224 void *, struct audio_params *); 225 226 int auich_alloc_cdata(struct auich_softc *); 227 228 int auich_allocmem(struct auich_softc *, size_t, size_t, 229 struct auich_dma *); 230 int auich_freemem(struct auich_softc *, struct auich_dma *); 231 232 void auich_powerhook(int, void *); 233 234 struct audio_hw_if auich_hw_if = { 235 auich_open, 236 auich_close, 237 NULL, /* drain */ 238 auich_query_encoding, 239 auich_set_params, 240 auich_round_blocksize, 241 NULL, /* commit_setting */ 242 NULL, /* init_output */ 243 NULL, /* init_input */ 244 NULL, /* start_output */ 245 NULL, /* start_input */ 246 auich_halt_output, 247 auich_halt_input, 248 NULL, /* speaker_ctl */ 249 auich_getdev, 250 NULL, /* getfd */ 251 auich_set_port, 252 auich_get_port, 253 auich_query_devinfo, 254 auich_allocm, 255 auich_freem, 256 auich_round_buffersize, 257 auich_mappage, 258 auich_get_props, 259 auich_trigger_output, 260 auich_trigger_input, 261 NULL, /* dev_ioctl */ 262 }; 263 264 int auich_attach_codec(void *, struct ac97_codec_if *); 265 int auich_read_codec(void *, u_int8_t, u_int16_t *); 266 int auich_write_codec(void *, u_int8_t, u_int16_t); 267 void auich_reset_codec(void *); 268 269 static const struct auich_devtype { 270 int product; 271 const char *name; 272 const char *shortname; 273 } auich_devices[] = { 274 { PCI_PRODUCT_INTEL_82801AA_ACA, 275 "i82801AA (ICH) AC-97 Audio", "ICH" }, 276 { PCI_PRODUCT_INTEL_82801AB_ACA, 277 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 278 { PCI_PRODUCT_INTEL_82801BA_ACA, 279 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 280 { PCI_PRODUCT_INTEL_82440MX_ACA, 281 "i82440MX AC-97 Audio", "440MX" }, 282 { PCI_PRODUCT_INTEL_82801CA_AC, 283 "i82801CA AC-97 Audio", "i830M" }, 284 285 { 0, 286 NULL, NULL }, 287 }; 288 289 static const struct auich_devtype * 290 auich_lookup(struct pci_attach_args *pa) 291 { 292 const struct auich_devtype *d; 293 294 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 295 return (NULL); 296 297 for (d = auich_devices; d->name != NULL; d++) { 298 if (PCI_PRODUCT(pa->pa_id) == d->product) 299 return (d); 300 } 301 302 return (NULL); 303 } 304 305 int 306 auich_match(struct device *parent, struct cfdata *match, void *aux) 307 { 308 struct pci_attach_args *pa = aux; 309 310 if (auich_lookup(pa) != NULL) 311 return (1); 312 313 return (0); 314 } 315 316 void 317 auich_attach(struct device *parent, struct device *self, void *aux) 318 { 319 struct auich_softc *sc = (struct auich_softc *)self; 320 struct pci_attach_args *pa = aux; 321 pci_intr_handle_t ih; 322 bus_size_t mix_size, aud_size; 323 pcireg_t csr; 324 const char *intrstr; 325 const struct auich_devtype *d; 326 u_int16_t ext_id, ext_status; 327 328 d = auich_lookup(pa); 329 if (d == NULL) 330 panic("auich_attach: impossible"); 331 332 printf(": %s\n", d->name); 333 334 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 335 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 336 printf("%s: can't map codec i/o space\n", 337 sc->sc_dev.dv_xname); 338 return; 339 } 340 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 341 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 342 printf("%s: can't map device i/o space\n", 343 sc->sc_dev.dv_xname); 344 return; 345 } 346 sc->dmat = pa->pa_dmat; 347 348 /* enable bus mastering */ 349 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 350 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 351 csr | PCI_COMMAND_MASTER_ENABLE); 352 353 /* Map and establish the interrupt. */ 354 if (pci_intr_map(pa, &ih)) { 355 printf("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 356 return; 357 } 358 intrstr = pci_intr_string(pa->pa_pc, ih); 359 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 360 auich_intr, sc); 361 if (sc->sc_ih == NULL) { 362 printf("%s: can't establish interrupt", sc->sc_dev.dv_xname); 363 if (intrstr != NULL) 364 printf(" at %s", intrstr); 365 printf("\n"); 366 return; 367 } 368 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 369 370 sprintf(sc->sc_audev.name, "%s AC97", d->shortname); 371 sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class)); 372 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 373 374 /* Set up DMA lists. */ 375 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 376 auich_alloc_cdata(sc); 377 378 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 379 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 380 381 /* Reset codec and AC'97 */ 382 auich_reset_codec(sc); 383 384 sc->host_if.arg = sc; 385 sc->host_if.attach = auich_attach_codec; 386 sc->host_if.read = auich_read_codec; 387 sc->host_if.write = auich_write_codec; 388 sc->host_if.reset = auich_reset_codec; 389 390 if (ac97_attach(&sc->host_if) != 0) 391 return; 392 393 auich_read_codec(sc, AC97_REG_EXTENDED_ID, &ext_id); 394 if ((ext_id & (AC97_CODEC_DOES_VRA | AC97_CODEC_DOES_MICVRA)) != 0) { 395 auich_read_codec(sc, AC97_REG_EXTENDED_STATUS, &ext_status); 396 if ((ext_id & AC97_CODEC_DOES_VRA) !=0) 397 ext_status |= AC97_ENAB_VRA; 398 if ((ext_id & AC97_CODEC_DOES_MICVRA) !=0) 399 ext_status |= AC97_ENAB_MICVRA; 400 auich_write_codec(sc, AC97_REG_EXTENDED_STATUS, ext_status); 401 sc->sc_fixed_rate = 0; 402 } else { 403 sc->sc_fixed_rate = 48000; 404 printf("%s: warning, fixed rate codec\n", sc->sc_dev.dv_xname); 405 } 406 407 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 408 409 /* Watch for power change */ 410 sc->sc_suspend = PWR_RESUME; 411 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 412 } 413 414 int 415 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 416 { 417 struct auich_softc *sc = v; 418 int i; 419 420 /* wait for an access semaphore */ 421 for (i = ICH_SEMATIMO; i-- && 422 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; DELAY(1)); 423 424 if (i > 0) { 425 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 426 DPRINTF(ICH_DEBUG_CODECIO, 427 ("auich_read_codec(%x, %x)\n", reg, *val)); 428 429 return 0; 430 } else { 431 DPRINTF(ICH_DEBUG_CODECIO, 432 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 433 return -1; 434 } 435 } 436 437 int 438 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 439 { 440 struct auich_softc *sc = v; 441 int i; 442 443 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 444 445 /* wait for an access semaphore */ 446 for (i = ICH_SEMATIMO; i-- && 447 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; DELAY(1)); 448 449 if (i > 0) { 450 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 451 return 0; 452 } else { 453 DPRINTF(ICH_DEBUG_CODECIO, 454 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 455 return -1; 456 } 457 } 458 459 int 460 auich_attach_codec(void *v, struct ac97_codec_if *cif) 461 { 462 struct auich_softc *sc = v; 463 464 sc->codec_if = cif; 465 return 0; 466 } 467 468 void 469 auich_reset_codec(void *v) 470 { 471 struct auich_softc *sc = v; 472 473 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, 0); 474 DELAY(10); 475 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, ICH_CRESET); 476 } 477 478 int 479 auich_open(void *v, int flags) 480 { 481 482 return 0; 483 } 484 485 void 486 auich_close(void *v) 487 { 488 struct auich_softc *sc = v; 489 490 auich_halt_output(sc); 491 auich_halt_input(sc); 492 493 sc->sc_pintr = NULL; 494 sc->sc_rintr = NULL; 495 } 496 497 int 498 auich_query_encoding(void *v, struct audio_encoding *aep) 499 { 500 501 #if 0 /* XXX Not until we emulate it. */ 502 switch (aep->index) { 503 case 0: 504 strcpy(aep->name, AudioEulinear); 505 aep->encoding = AUDIO_ENCODING_ULINEAR; 506 aep->precision = 8; 507 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 508 return (0); 509 #else 510 switch (aep->index + 1) { 511 #endif 512 case 1: 513 strcpy(aep->name, AudioEmulaw); 514 aep->encoding = AUDIO_ENCODING_ULAW; 515 aep->precision = 8; 516 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 517 return (0); 518 case 2: 519 strcpy(aep->name, AudioEalaw); 520 aep->encoding = AUDIO_ENCODING_ALAW; 521 aep->precision = 8; 522 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 523 return (0); 524 case 3: 525 strcpy(aep->name, AudioEslinear); 526 aep->encoding = AUDIO_ENCODING_SLINEAR; 527 aep->precision = 8; 528 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 529 return (0); 530 case 4: 531 strcpy(aep->name, AudioEslinear_le); 532 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 533 aep->precision = 16; 534 aep->flags = 0; 535 return (0); 536 case 5: 537 strcpy(aep->name, AudioEulinear_le); 538 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 539 aep->precision = 16; 540 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 541 return (0); 542 case 6: 543 strcpy(aep->name, AudioEslinear_be); 544 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 545 aep->precision = 16; 546 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 547 return (0); 548 case 7: 549 strcpy(aep->name, AudioEulinear_be); 550 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 551 aep->precision = 16; 552 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 553 return (0); 554 default: 555 return (EINVAL); 556 } 557 } 558 559 int 560 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 561 struct audio_params *rec) 562 { 563 struct auich_softc *sc = v; 564 struct audio_params *p; 565 int mode; 566 u_int16_t val, rate, inout; 567 568 for (mode = AUMODE_RECORD; mode != -1; 569 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 570 if ((setmode & mode) == 0) 571 continue; 572 573 p = mode == AUMODE_PLAY ? play : rec; 574 if (p == NULL) 575 continue; 576 577 inout = mode == AUMODE_PLAY ? ICH_PM_PCMO : ICH_PM_PCMI; 578 579 if ((p->sample_rate != 8000) && 580 (p->sample_rate != 11025) && 581 (p->sample_rate != 16000) && 582 (p->sample_rate != 22050) && 583 (p->sample_rate != 32000) && 584 (p->sample_rate != 44100) && 585 (p->sample_rate != 48000)) 586 return (EINVAL); 587 588 p->factor = 1; 589 p->sw_code = NULL; 590 switch (p->encoding) { 591 case AUDIO_ENCODING_SLINEAR_BE: 592 if (p->precision == 16) 593 p->sw_code = swap_bytes; 594 else { 595 if (mode == AUMODE_PLAY) 596 p->sw_code = linear8_to_linear16_le; 597 else 598 p->sw_code = linear16_to_linear8_le; 599 } 600 break; 601 602 case AUDIO_ENCODING_SLINEAR_LE: 603 if (p->precision != 16) { 604 if (mode == AUMODE_PLAY) 605 p->sw_code = linear8_to_linear16_le; 606 else 607 p->sw_code = linear16_to_linear8_le; 608 } 609 break; 610 611 case AUDIO_ENCODING_ULINEAR_BE: 612 if (p->precision == 16) { 613 if (mode == AUMODE_PLAY) 614 p->sw_code = 615 swap_bytes_change_sign16_le; 616 else 617 p->sw_code = 618 change_sign16_swap_bytes_le; 619 } else { 620 /* 621 * XXX ulinear8_to_slinear16_le 622 */ 623 return (EINVAL); 624 } 625 break; 626 627 case AUDIO_ENCODING_ULINEAR_LE: 628 if (p->precision == 16) 629 p->sw_code = change_sign16_le; 630 else { 631 /* 632 * XXX ulinear8_to_slinear16_le 633 */ 634 return (EINVAL); 635 } 636 break; 637 638 case AUDIO_ENCODING_ULAW: 639 if (mode == AUMODE_PLAY) { 640 p->factor = 2; 641 p->sw_code = mulaw_to_slinear16_le; 642 } else { 643 /* 644 * XXX slinear16_le_to_mulaw 645 */ 646 return (EINVAL); 647 } 648 break; 649 650 case AUDIO_ENCODING_ALAW: 651 if (mode == AUMODE_PLAY) { 652 p->factor = 2; 653 p->sw_code = alaw_to_slinear16_le; 654 } else { 655 /* 656 * XXX slinear16_le_to_alaw 657 */ 658 return (EINVAL); 659 } 660 break; 661 662 default: 663 return (EINVAL); 664 } 665 666 auich_read_codec(sc, AC97_REG_POWER, &val); 667 auich_write_codec(sc, AC97_REG_POWER, val | inout); 668 669 if (sc->sc_fixed_rate) { 670 p->sample_rate = sc->sc_fixed_rate; 671 } else { 672 auich_write_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, 673 p->sample_rate); 674 auich_read_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, 675 &rate); 676 p->sample_rate = rate; 677 } 678 679 auich_write_codec(sc, AC97_REG_POWER, val); 680 } 681 682 return (0); 683 } 684 685 int 686 auich_round_blocksize(void *v, int blk) 687 { 688 689 return (blk & ~0x3f); /* keep good alignment */ 690 } 691 692 int 693 auich_halt_output(void *v) 694 { 695 struct auich_softc *sc = v; 696 697 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 698 699 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 700 701 return (0); 702 } 703 704 int 705 auich_halt_input(void *v) 706 { 707 struct auich_softc *sc = v; 708 709 DPRINTF(ICH_DEBUG_DMA, 710 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 711 712 /* XXX halt both unless known otherwise */ 713 714 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 715 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 716 717 return (0); 718 } 719 720 int 721 auich_getdev(void *v, struct audio_device *adp) 722 { 723 struct auich_softc *sc = v; 724 725 *adp = sc->sc_audev; 726 return (0); 727 } 728 729 int 730 auich_set_port(void *v, mixer_ctrl_t *cp) 731 { 732 struct auich_softc *sc = v; 733 734 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 735 } 736 737 int 738 auich_get_port(void *v, mixer_ctrl_t *cp) 739 { 740 struct auich_softc *sc = v; 741 742 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 743 } 744 745 int 746 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 747 { 748 struct auich_softc *sc = v; 749 750 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 751 } 752 753 void * 754 auich_allocm(void *v, int direction, size_t size, int pool, int flags) 755 { 756 struct auich_softc *sc = v; 757 struct auich_dma *p; 758 int error; 759 760 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 761 return (NULL); 762 763 p = malloc(sizeof(*p), pool, flags|M_ZERO); 764 if (p == NULL) 765 return (NULL); 766 767 error = auich_allocmem(sc, size, 0, p); 768 if (error) { 769 free(p, pool); 770 return (NULL); 771 } 772 773 p->next = sc->sc_dmas; 774 sc->sc_dmas = p; 775 776 return (KERNADDR(p)); 777 } 778 779 void 780 auich_freem(void *v, void *ptr, int pool) 781 { 782 struct auich_softc *sc = v; 783 struct auich_dma *p, **pp; 784 785 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 786 if (KERNADDR(p) == ptr) { 787 auich_freemem(sc, p); 788 *pp = p->next; 789 free(p, pool); 790 return; 791 } 792 } 793 } 794 795 size_t 796 auich_round_buffersize(void *v, int direction, size_t size) 797 { 798 799 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 800 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 801 802 return size; 803 } 804 805 paddr_t 806 auich_mappage(void *v, void *mem, off_t off, int prot) 807 { 808 struct auich_softc *sc = v; 809 struct auich_dma *p; 810 811 if (off < 0) 812 return (-1); 813 814 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 815 ; 816 if (!p) 817 return (-1); 818 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 819 off, prot, BUS_DMA_WAITOK)); 820 } 821 822 int 823 auich_get_props(void *v) 824 { 825 826 return (AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | 827 AUDIO_PROP_FULLDUPLEX); 828 } 829 830 int 831 auich_intr(void *v) 832 { 833 struct auich_softc *sc = v; 834 int ret = 0, sts, gsts, i, qptr; 835 836 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 837 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 838 839 if (gsts & ICH_POINT) { 840 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+ICH_STS); 841 DPRINTF(ICH_DEBUG_DMA, 842 ("auich_intr: osts=0x%x\n", sts)); 843 844 if (sts & ICH_FIFOE) { 845 printf("%s: fifo underrun # %u\n", 846 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 847 } 848 849 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 850 if (sts & (ICH_LVBCI | ICH_CELV)) { 851 struct auich_dmalist *q; 852 853 qptr = sc->ptr_pcmo; 854 855 while (qptr != i) { 856 q = &sc->dmalist_pcmo[qptr]; 857 858 q->base = sc->pcmo_p; 859 q->len = (sc->pcmo_blksize / 2) | ICH_DMAF_IOC; 860 DPRINTF(ICH_DEBUG_DMA, 861 ("auich_intr: %p, %p = %x @ 0x%x\n", 862 &sc->dmalist_pcmo[i], q, 863 sc->pcmo_blksize / 2, sc->pcmo_p)); 864 865 sc->pcmo_p += sc->pcmo_blksize; 866 if (sc->pcmo_p >= sc->pcmo_end) 867 sc->pcmo_p = sc->pcmo_start; 868 869 if (++qptr == ICH_DMALIST_MAX) 870 qptr = 0; 871 } 872 873 sc->ptr_pcmo = qptr; 874 bus_space_write_1(sc->iot, sc->aud_ioh, 875 ICH_PCMO + ICH_LVI, 876 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 877 } 878 879 if (sts & ICH_BCIS && sc->sc_pintr) 880 sc->sc_pintr(sc->sc_parg); 881 882 /* int ack */ 883 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_STS, 884 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 885 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 886 ret++; 887 } 888 889 if (gsts & ICH_PIINT) { 890 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+ICH_STS); 891 DPRINTF(ICH_DEBUG_DMA, 892 ("auich_intr: ists=0x%x\n", sts)); 893 894 if (sts & ICH_FIFOE) { 895 printf("%s: fifo overrun # %u\n", 896 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 897 } 898 899 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 900 if (sts & (ICH_LVBCI | ICH_CELV)) { 901 struct auich_dmalist *q; 902 903 qptr = sc->ptr_pcmi; 904 905 while (qptr != i) { 906 q = &sc->dmalist_pcmi[qptr]; 907 908 q->base = sc->pcmi_p; 909 q->len = (sc->pcmi_blksize / 2) | ICH_DMAF_IOC; 910 DPRINTF(ICH_DEBUG_DMA, 911 ("auich_intr: %p, %p = %x @ 0x%x\n", 912 &sc->dmalist_pcmi[i], q, 913 sc->pcmi_blksize / 2, sc->pcmi_p)); 914 915 sc->pcmi_p += sc->pcmi_blksize; 916 if (sc->pcmi_p >= sc->pcmi_end) 917 sc->pcmi_p = sc->pcmi_start; 918 919 if (++qptr == ICH_DMALIST_MAX) 920 qptr = 0; 921 } 922 923 sc->ptr_pcmi = qptr; 924 bus_space_write_1(sc->iot, sc->aud_ioh, 925 ICH_PCMI + ICH_LVI, 926 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 927 } 928 929 if (sts & ICH_BCIS && sc->sc_rintr) 930 sc->sc_rintr(sc->sc_rarg); 931 932 /* int ack */ 933 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_STS, 934 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 935 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 936 ret++; 937 } 938 939 if (gsts & ICH_MIINT) { 940 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+ICH_STS); 941 DPRINTF(ICH_DEBUG_DMA, 942 ("auich_intr: ists=0x%x\n", sts)); 943 if (sts & ICH_FIFOE) 944 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 945 946 /* TODO mic input dma */ 947 948 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 949 } 950 951 return ret; 952 } 953 954 int 955 auich_trigger_output(void *v, void *start, void *end, int blksize, 956 void (*intr)(void *), void *arg, struct audio_params *param) 957 { 958 struct auich_softc *sc = v; 959 struct auich_dmalist *q; 960 struct auich_dma *p; 961 size_t size; 962 963 DPRINTF(ICH_DEBUG_DMA, 964 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 965 start, end, blksize, intr, arg, param)); 966 967 sc->sc_pintr = intr; 968 sc->sc_parg = arg; 969 970 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 971 ; 972 if (!p) { 973 printf("auich_trigger_output: bad addr %p\n", start); 974 return (EINVAL); 975 } 976 977 size = (size_t)((caddr_t)end - (caddr_t)start); 978 979 /* 980 * The logic behind this is: 981 * setup one buffer to play, then LVI dump out the rest 982 * to the scatter-gather chain. 983 */ 984 sc->pcmo_start = DMAADDR(p); 985 sc->pcmo_p = sc->pcmo_start + blksize; 986 sc->pcmo_end = sc->pcmo_start + size; 987 sc->pcmo_blksize = blksize; 988 989 sc->ptr_pcmo = 0; 990 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 991 q->base = sc->pcmo_start; 992 q->len = (blksize / 2) | ICH_DMAF_IOC; 993 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 994 sc->ptr_pcmo = 0; 995 996 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 997 sc->sc_cddma + ICH_PCMO_OFF(0)); 998 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 999 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1000 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1001 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1002 1003 return (0); 1004 } 1005 1006 int 1007 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1008 void *v; 1009 void *start, *end; 1010 int blksize; 1011 void (*intr)(void *); 1012 void *arg; 1013 struct audio_params *param; 1014 { 1015 struct auich_softc *sc = v; 1016 struct auich_dmalist *q; 1017 struct auich_dma *p; 1018 size_t size; 1019 1020 DPRINTF(ICH_DEBUG_DMA, 1021 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1022 start, end, blksize, intr, arg, param)); 1023 1024 sc->sc_rintr = intr; 1025 sc->sc_rarg = arg; 1026 1027 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1028 ; 1029 if (!p) { 1030 printf("auich_trigger_input: bad addr %p\n", start); 1031 return (EINVAL); 1032 } 1033 1034 size = (size_t)((caddr_t)end - (caddr_t)start); 1035 1036 /* 1037 * The logic behind this is: 1038 * setup one buffer to play, then LVI dump out the rest 1039 * to the scatter-gather chain. 1040 */ 1041 sc->pcmi_start = DMAADDR(p); 1042 sc->pcmi_p = sc->pcmi_start + blksize; 1043 sc->pcmi_end = sc->pcmi_start + size; 1044 sc->pcmi_blksize = blksize; 1045 1046 sc->ptr_pcmi = 0; 1047 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1048 q->base = sc->pcmi_start; 1049 q->len = (blksize / 2) | ICH_DMAF_IOC; 1050 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1051 sc->ptr_pcmi = 0; 1052 1053 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1054 sc->sc_cddma + ICH_PCMI_OFF(0)); 1055 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1056 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1057 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1058 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1059 1060 return (0); 1061 } 1062 1063 int 1064 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1065 struct auich_dma *p) 1066 { 1067 int error; 1068 1069 p->size = size; 1070 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1071 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1072 &p->nsegs, BUS_DMA_NOWAIT); 1073 if (error) 1074 return (error); 1075 1076 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1077 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1078 if (error) 1079 goto free; 1080 1081 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1082 0, BUS_DMA_NOWAIT, &p->map); 1083 if (error) 1084 goto unmap; 1085 1086 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1087 BUS_DMA_NOWAIT); 1088 if (error) 1089 goto destroy; 1090 return (0); 1091 1092 destroy: 1093 bus_dmamap_destroy(sc->dmat, p->map); 1094 unmap: 1095 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1096 free: 1097 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1098 return (error); 1099 } 1100 1101 int 1102 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1103 { 1104 1105 bus_dmamap_unload(sc->dmat, p->map); 1106 bus_dmamap_destroy(sc->dmat, p->map); 1107 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1108 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1109 return (0); 1110 } 1111 1112 int 1113 auich_alloc_cdata(struct auich_softc *sc) 1114 { 1115 bus_dma_segment_t seg; 1116 int error, rseg; 1117 1118 /* 1119 * Allocate the control data structure, and create and load the 1120 * DMA map for it. 1121 */ 1122 if ((error = bus_dmamem_alloc(sc->dmat, 1123 sizeof(struct auich_cdata), 1124 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1125 printf("%s: unable to allocate control data, error = %d\n", 1126 sc->sc_dev.dv_xname, error); 1127 goto fail_0; 1128 } 1129 1130 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1131 sizeof(struct auich_cdata), 1132 (caddr_t *) &sc->sc_cdata, 1133 BUS_DMA_COHERENT)) != 0) { 1134 printf("%s: unable to map control data, error = %d\n", 1135 sc->sc_dev.dv_xname, error); 1136 goto fail_1; 1137 } 1138 1139 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1140 sizeof(struct auich_cdata), 0, 0, 1141 &sc->sc_cddmamap)) != 0) { 1142 printf("%s: unable to create control data DMA map, " 1143 "error = %d\n", sc->sc_dev.dv_xname, error); 1144 goto fail_2; 1145 } 1146 1147 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1148 sc->sc_cdata, sizeof(struct auich_cdata), 1149 NULL, 0)) != 0) { 1150 printf("%s: unable tp load control data DMA map, " 1151 "error = %d\n", sc->sc_dev.dv_xname, error); 1152 goto fail_3; 1153 } 1154 1155 return (0); 1156 1157 fail_3: 1158 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1159 fail_2: 1160 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1161 sizeof(struct auich_cdata)); 1162 fail_1: 1163 bus_dmamem_free(sc->dmat, &seg, rseg); 1164 fail_0: 1165 return (error); 1166 } 1167 1168 void 1169 auich_powerhook(int why, void *addr) 1170 { 1171 struct auich_softc *sc = (struct auich_softc *)addr; 1172 1173 switch (why) { 1174 case PWR_SUSPEND: 1175 case PWR_STANDBY: 1176 /* Power down */ 1177 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1178 sc->sc_suspend = why; 1179 auich_read_codec(sc, AC97_REG_EXTENDED_STATUS, &sc->ext_status); 1180 break; 1181 1182 case PWR_RESUME: 1183 /* Wake up */ 1184 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1185 if (sc->sc_suspend == PWR_RESUME) { 1186 printf("%s: resume without suspend.\n", 1187 sc->sc_dev.dv_xname); 1188 sc->sc_suspend = why; 1189 return; 1190 } 1191 sc->sc_suspend = why; 1192 auich_reset_codec(sc); 1193 DELAY(1000); 1194 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1195 auich_write_codec(sc, AC97_REG_EXTENDED_STATUS, sc->ext_status); 1196 break; 1197 1198 case PWR_SOFTSUSPEND: 1199 case PWR_SOFTSTANDBY: 1200 case PWR_SOFTRESUME: 1201 break; 1202 } 1203 } 1204
Indexes created Thu Oct 23 22:10:10 GMT 2025