auich.c revision 1.113
1 /* $NetBSD: auich.c,v 1.113 2006/09/25 23:11:07 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.113 2006/09/25 23:11:07 jmcneill Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 pci_intr_handle_t intrh; 187 188 struct ac97_codec_if *codec_if; 189 struct ac97_host_if host_if; 190 int sc_codecnum; 191 int sc_codectype; 192 enum ac97_host_flags sc_codecflags; 193 boolean_t sc_spdif; 194 195 /* DMA scatter-gather lists. */ 196 bus_dmamap_t sc_cddmamap; 197 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 198 199 struct auich_cdata *sc_cdata; 200 201 struct auich_ring { 202 int qptr; 203 struct auich_dmalist *dmalist; 204 205 uint32_t start, p, end; 206 int blksize; 207 208 void (*intr)(void *); 209 void *arg; 210 } pcmo, pcmi, mici; 211 212 struct auich_dma *sc_dmas; 213 214 /* SiS 7012 hack */ 215 int sc_sample_shift; 216 int sc_sts_reg; 217 /* 440MX workaround */ 218 int sc_dmamap_flags; 219 220 /* Power Management */ 221 void *sc_powerhook; 222 int sc_suspend; 223 int sc_powerstate; 224 struct pci_conf_state sc_pciconf; 225 226 /* sysctl */ 227 struct sysctllog *sc_log; 228 uint32_t sc_ac97_clock; 229 int sc_ac97_clock_mib; 230 231 int sc_modem_offset; 232 233 #define AUICH_AUDIO_NFORMATS 3 234 #define AUICH_MODEM_NFORMATS 1 235 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 236 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 237 struct audio_encoding_set *sc_encodings; 238 struct audio_encoding_set *sc_spdif_encodings; 239 }; 240 241 /* Debug */ 242 #ifdef AUICH_DEBUG 243 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 244 int auich_debug = 0xfffe; 245 #define ICH_DEBUG_CODECIO 0x0001 246 #define ICH_DEBUG_DMA 0x0002 247 #define ICH_DEBUG_INTR 0x0004 248 #else 249 #define DPRINTF(x,y) /* nothing */ 250 #endif 251 252 static int auich_match(struct device *, struct cfdata *, void *); 253 static void auich_attach(struct device *, struct device *, void *); 254 static int auich_detach(struct device *, int); 255 static int auich_activate(struct device *, enum devact); 256 static int auich_intr(void *); 257 258 CFATTACH_DECL(auich, sizeof(struct auich_softc), 259 auich_match, auich_attach, auich_detach, auich_activate); 260 261 static int auich_open(void *, int); 262 static void auich_close(void *); 263 static int auich_query_encoding(void *, struct audio_encoding *); 264 static int auich_set_params(void *, int, int, audio_params_t *, 265 audio_params_t *, stream_filter_list_t *, 266 stream_filter_list_t *); 267 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 268 static void auich_halt_pipe(struct auich_softc *, int); 269 static int auich_halt_output(void *); 270 static int auich_halt_input(void *); 271 static int auich_getdev(void *, struct audio_device *); 272 static int auich_set_port(void *, mixer_ctrl_t *); 273 static int auich_get_port(void *, mixer_ctrl_t *); 274 static int auich_query_devinfo(void *, mixer_devinfo_t *); 275 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 276 static void auich_freem(void *, void *, struct malloc_type *); 277 static size_t auich_round_buffersize(void *, int, size_t); 278 static paddr_t auich_mappage(void *, void *, off_t, int); 279 static int auich_get_props(void *); 280 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 281 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 282 static int auich_trigger_output(void *, void *, void *, int, 283 void (*)(void *), void *, const audio_params_t *); 284 static int auich_trigger_input(void *, void *, void *, int, 285 void (*)(void *), void *, const audio_params_t *); 286 static int auich_powerstate(void *, int); 287 288 static int auich_alloc_cdata(struct auich_softc *); 289 290 static int auich_allocmem(struct auich_softc *, size_t, size_t, 291 struct auich_dma *); 292 static int auich_freemem(struct auich_softc *, struct auich_dma *); 293 294 static void auich_powerhook(int, void *); 295 static int auich_set_rate(struct auich_softc *, int, u_long); 296 static int auich_sysctl_verify(SYSCTLFN_ARGS); 297 static void auich_finish_attach(struct device *); 298 static void auich_calibrate(struct auich_softc *); 299 static void auich_clear_cas(struct auich_softc *); 300 301 static int auich_attach_codec(void *, struct ac97_codec_if *); 302 static int auich_read_codec(void *, uint8_t, uint16_t *); 303 static int auich_write_codec(void *, uint8_t, uint16_t); 304 static int auich_reset_codec(void *); 305 static enum ac97_host_flags auich_flags_codec(void *); 306 static void auich_spdif_event(void *, boolean_t); 307 308 static const struct audio_hw_if auich_hw_if = { 309 auich_open, 310 auich_close, 311 NULL, /* drain */ 312 auich_query_encoding, 313 auich_set_params, 314 auich_round_blocksize, 315 NULL, /* commit_setting */ 316 NULL, /* init_output */ 317 NULL, /* init_input */ 318 NULL, /* start_output */ 319 NULL, /* start_input */ 320 auich_halt_output, 321 auich_halt_input, 322 NULL, /* speaker_ctl */ 323 auich_getdev, 324 NULL, /* getfd */ 325 auich_set_port, 326 auich_get_port, 327 auich_query_devinfo, 328 auich_allocm, 329 auich_freem, 330 auich_round_buffersize, 331 auich_mappage, 332 auich_get_props, 333 auich_trigger_output, 334 auich_trigger_input, 335 NULL, /* dev_ioctl */ 336 auich_powerstate, 337 }; 338 339 #define AUICH_FORMATS_1CH 0 340 #define AUICH_FORMATS_4CH 1 341 #define AUICH_FORMATS_6CH 2 342 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 343 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 344 2, AUFMT_STEREO, 0, {8000, 48000}}, 345 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 346 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 347 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 348 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 349 }; 350 351 #define AUICH_SPDIF_NFORMATS 1 352 static const struct audio_format auich_spdif_formats[AUICH_SPDIF_NFORMATS] = { 353 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 354 2, AUFMT_STEREO, 1, {48000}}, 355 }; 356 357 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 358 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 359 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 360 }; 361 362 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 363 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 364 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 365 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 366 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 367 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 368 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 369 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 370 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 371 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 372 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 373 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 374 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 375 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 376 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 377 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 378 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 379 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 380 #define PCIID_NFORCE430 PCI_ID_CODE0(NVIDIA, NFORCE430_AC) 381 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 382 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 383 384 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 385 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 386 387 struct auich_devtype { 388 pcireg_t id; 389 const char *name; 390 const char *shortname; /* must be less than 11 characters */ 391 }; 392 393 static const struct auich_devtype auich_audio_devices[] = { 394 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 395 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 396 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 397 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 398 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 399 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 400 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 401 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 402 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 403 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 404 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 405 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 406 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 407 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 408 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 409 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 410 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 411 { PCIID_NFORCE430, "nForce430 (MCP51) AC-97 Audio", "nForce430" }, 412 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 413 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 414 { 0, NULL, NULL }, 415 }; 416 417 static const struct auich_devtype auich_modem_devices[] = { 418 #ifdef AUICH_ATTACH_MODEM 419 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 420 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 421 #endif 422 { 0, NULL, NULL }, 423 }; 424 425 static const struct auich_devtype * 426 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 427 { 428 const struct auich_devtype *d; 429 430 for (d = auich_devices; d->name != NULL; d++) { 431 if (pa->pa_id == d->id) 432 return d; 433 } 434 435 return NULL; 436 } 437 438 static int 439 auich_match(struct device *parent, struct cfdata *match, void *aux) 440 { 441 struct pci_attach_args *pa; 442 443 pa = aux; 444 if (auich_lookup(pa, auich_audio_devices) != NULL) 445 return 1; 446 if (auich_lookup(pa, auich_modem_devices) != NULL) 447 return 1; 448 449 return 0; 450 } 451 452 static void 453 auich_attach(struct device *parent, struct device *self, void *aux) 454 { 455 struct auich_softc *sc; 456 struct pci_attach_args *pa; 457 pcireg_t v, subdev; 458 const char *intrstr; 459 const struct auich_devtype *d; 460 const struct sysctlnode *node, *node_ac97clock; 461 int err, node_mib, i; 462 463 sc = (struct auich_softc *)self; 464 pa = aux; 465 466 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 467 sc->sc_modem_offset = 0x10; 468 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 469 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 470 sc->sc_modem_offset = 0; 471 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 472 } else 473 panic("auich_attach: impossible"); 474 475 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 476 aprint_naive(": Audio controller\n"); 477 else 478 aprint_naive(": Modem controller\n"); 479 480 sc->sc_pc = pa->pa_pc; 481 sc->sc_pt = pa->pa_tag; 482 483 aprint_normal(": %s\n", d->name); 484 485 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 486 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 487 || d->id == PCIID_ICH4MODEM) { 488 /* 489 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 490 */ 491 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 492 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 493 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 494 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 495 v | ICH_CFG_IOSE); 496 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 497 0, &sc->iot, &sc->mix_ioh, NULL, 498 &sc->mix_size)) { 499 aprint_error("%s: can't map codec i/o space\n", 500 sc->sc_dev.dv_xname); 501 return; 502 } 503 } 504 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 505 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 506 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 507 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 508 v | ICH_CFG_IOSE); 509 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 510 0, &sc->iot, &sc->aud_ioh, NULL, 511 &sc->aud_size)) { 512 aprint_error("%s: can't map device i/o space\n", 513 sc->sc_dev.dv_xname); 514 return; 515 } 516 } 517 } else { 518 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 519 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 520 aprint_error("%s: can't map codec i/o space\n", 521 sc->sc_dev.dv_xname); 522 return; 523 } 524 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 525 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 526 aprint_error("%s: can't map device i/o space\n", 527 sc->sc_dev.dv_xname); 528 return; 529 } 530 } 531 sc->dmat = pa->pa_dmat; 532 533 /* enable bus mastering */ 534 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 535 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 536 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 537 538 /* Map and establish the interrupt. */ 539 if (pci_intr_map(pa, &sc->intrh)) { 540 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 541 return; 542 } 543 intrstr = pci_intr_string(pa->pa_pc, sc->intrh); 544 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO, 545 auich_intr, sc); 546 if (sc->sc_ih == NULL) { 547 aprint_error("%s: can't establish interrupt", 548 sc->sc_dev.dv_xname); 549 if (intrstr != NULL) 550 aprint_normal(" at %s", intrstr); 551 aprint_normal("\n"); 552 return; 553 } 554 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 555 556 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 557 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 558 "0x%02x", PCI_REVISION(pa->pa_class)); 559 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 560 561 /* SiS 7012 needs special handling */ 562 if (d->id == PCIID_SIS7012) { 563 sc->sc_sts_reg = ICH_PICB; 564 sc->sc_sample_shift = 0; 565 /* Un-mute output. From Linux. */ 566 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 567 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 568 ICH_SIS_CTL_UNMUTE); 569 } else { 570 sc->sc_sts_reg = ICH_STS; 571 sc->sc_sample_shift = 1; 572 } 573 574 /* Workaround for a 440MX B-stepping erratum */ 575 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 576 if (d->id == PCIID_440MX) { 577 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 578 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 579 } 580 581 /* Set up DMA lists. */ 582 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 583 auich_alloc_cdata(sc); 584 585 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 586 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 587 588 /* Modem codecs are always the secondary codec on ICH */ 589 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 590 591 sc->host_if.arg = sc; 592 sc->host_if.attach = auich_attach_codec; 593 sc->host_if.read = auich_read_codec; 594 sc->host_if.write = auich_write_codec; 595 sc->host_if.reset = auich_reset_codec; 596 sc->host_if.flags = auich_flags_codec; 597 sc->host_if.spdif_event = auich_spdif_event; 598 599 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 600 switch (subdev) { 601 case 0x202f161f: /* Gateway 7326GZ */ 602 case 0x203a161f: /* Gateway 4028GZ */ 603 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 604 case 0x8144104d: /* Sony VAIO PCG-TR* */ 605 case 0x8197104d: /* Sony S1XP */ 606 case 0x81c0104d: /* Sony VAIO type T */ 607 case 0x81c5104d: /* Sony VAIO VGN-B1XP */ 608 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP; 609 break; 610 default: 611 sc->sc_codecflags = 0; 612 break; 613 } 614 615 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 616 return; 617 sc->codec_if->vtbl->unlock(sc->codec_if); 618 619 /* setup audio_format */ 620 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 621 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 622 if (!AC97_IS_4CH(sc->codec_if)) 623 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 624 if (!AC97_IS_6CH(sc->codec_if)) 625 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 626 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 627 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 628 sc->sc_audio_formats[i].frequency_type = 1; 629 sc->sc_audio_formats[i].frequency[0] = 48000; 630 } 631 } 632 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 633 &sc->sc_encodings)) 634 return; 635 if (0 != auconv_create_encodings(auich_spdif_formats, AUICH_SPDIF_NFORMATS, 636 &sc->sc_spdif_encodings)) 637 return; 638 } else { 639 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 640 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 641 &sc->sc_encodings)) 642 return; 643 } 644 645 646 /* Watch for power change */ 647 sc->sc_suspend = PWR_RESUME; 648 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 649 auich_powerhook, sc); 650 651 config_interrupts(self, auich_finish_attach); 652 653 /* sysctl setup */ 654 if (AC97_IS_FIXED_RATE(sc->codec_if) && 655 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 656 return; 657 658 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 659 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 660 CTL_HW, CTL_EOL); 661 if (err != 0) 662 goto sysctl_err; 663 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 664 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 665 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 666 if (err != 0) 667 goto sysctl_err; 668 node_mib = node->sysctl_num; 669 670 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 671 /* passing the sc address instead of &sc->sc_ac97_clock */ 672 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 673 CTLFLAG_READWRITE, 674 CTLTYPE_INT, "ac97rate", 675 SYSCTL_DESCR("AC'97 codec link rate"), 676 auich_sysctl_verify, 0, sc, 0, 677 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 678 if (err != 0) 679 goto sysctl_err; 680 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 681 } 682 683 return; 684 685 sysctl_err: 686 printf("%s: failed to add sysctl nodes. (%d)\n", 687 sc->sc_dev.dv_xname, err); 688 return; /* failure of sysctl is not fatal. */ 689 } 690 691 static int 692 auich_activate(struct device *self, enum devact act) 693 { 694 struct auich_softc *sc; 695 int ret; 696 697 sc = (struct auich_softc *)self; 698 ret = 0; 699 switch (act) { 700 case DVACT_ACTIVATE: 701 return EOPNOTSUPP; 702 case DVACT_DEACTIVATE: 703 if (sc->sc_audiodev != NULL) 704 ret = config_deactivate(sc->sc_audiodev); 705 return ret; 706 } 707 return EOPNOTSUPP; 708 } 709 710 static int 711 auich_detach(struct device *self, int flags) 712 { 713 struct auich_softc *sc; 714 715 sc = (struct auich_softc *)self; 716 717 /* audio */ 718 if (sc->sc_audiodev != NULL) 719 config_detach(sc->sc_audiodev, flags); 720 721 /* sysctl */ 722 sysctl_teardown(&sc->sc_log); 723 724 /* audio_encoding_set */ 725 auconv_delete_encodings(sc->sc_encodings); 726 auconv_delete_encodings(sc->sc_spdif_encodings); 727 728 /* ac97 */ 729 if (sc->codec_if != NULL) 730 sc->codec_if->vtbl->detach(sc->codec_if); 731 732 /* PCI */ 733 if (sc->sc_ih != NULL) 734 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 735 if (sc->mix_size != 0) 736 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 737 if (sc->aud_size != 0) 738 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 739 return 0; 740 } 741 742 static int 743 auich_sysctl_verify(SYSCTLFN_ARGS) 744 { 745 int error, tmp; 746 struct sysctlnode node; 747 struct auich_softc *sc; 748 749 node = *rnode; 750 sc = rnode->sysctl_data; 751 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 752 tmp = sc->sc_ac97_clock; 753 node.sysctl_data = &tmp; 754 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 755 if (error || newp == NULL) 756 return error; 757 758 if (tmp < 48000 || tmp > 96000) 759 return EINVAL; 760 sc->sc_ac97_clock = tmp; 761 } 762 763 return 0; 764 } 765 766 static void 767 auich_finish_attach(struct device *self) 768 { 769 struct auich_softc *sc; 770 771 sc = (void *)self; 772 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 773 auich_calibrate(sc); 774 775 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 776 777 #if notyet 778 auich_powerhook(PWR_SUSPEND, sc); 779 #endif 780 781 return; 782 } 783 784 #define ICH_CODECIO_INTERVAL 10 785 static int 786 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 787 { 788 struct auich_softc *sc; 789 int i; 790 uint32_t status; 791 792 sc = v; 793 /* wait for an access semaphore */ 794 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 795 bus_space_read_1(sc->iot, sc->aud_ioh, 796 ICH_CAS + sc->sc_modem_offset) & 1; 797 DELAY(ICH_CODECIO_INTERVAL)); 798 799 if (i > 0) { 800 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 801 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 802 DPRINTF(ICH_DEBUG_CODECIO, 803 ("auich_read_codec(%x, %x)\n", reg, *val)); 804 status = bus_space_read_4(sc->iot, sc->aud_ioh, 805 ICH_GSTS + sc->sc_modem_offset); 806 if (status & ICH_RCS) { 807 bus_space_write_4(sc->iot, sc->aud_ioh, 808 ICH_GSTS + sc->sc_modem_offset, 809 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 810 *val = 0xffff; 811 DPRINTF(ICH_DEBUG_CODECIO, 812 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 813 if (reg == AC97_REG_GPIO_STATUS) 814 auich_clear_cas(sc); 815 return -1; 816 } 817 if (reg == AC97_REG_GPIO_STATUS) 818 auich_clear_cas(sc); 819 return 0; 820 } else { 821 aprint_normal("%s: read_codec timeout\n", sc->sc_dev.dv_xname); 822 if (reg == AC97_REG_GPIO_STATUS) 823 auich_clear_cas(sc); 824 return -1; 825 } 826 } 827 828 static int 829 auich_write_codec(void *v, uint8_t reg, uint16_t val) 830 { 831 struct auich_softc *sc; 832 int i; 833 834 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 835 sc = v; 836 /* wait for an access semaphore */ 837 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 838 bus_space_read_1(sc->iot, sc->aud_ioh, 839 ICH_CAS + sc->sc_modem_offset) & 1; 840 DELAY(ICH_CODECIO_INTERVAL)); 841 842 if (i > 0) { 843 bus_space_write_2(sc->iot, sc->mix_ioh, 844 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 845 return 0; 846 } else { 847 aprint_normal("%s: write_codec timeout\n", sc->sc_dev.dv_xname); 848 return -1; 849 } 850 } 851 852 static int 853 auich_attach_codec(void *v, struct ac97_codec_if *cif) 854 { 855 struct auich_softc *sc; 856 857 sc = v; 858 sc->codec_if = cif; 859 860 return 0; 861 } 862 863 static int 864 auich_reset_codec(void *v) 865 { 866 struct auich_softc *sc; 867 int i; 868 uint32_t control, status; 869 870 sc = v; 871 control = bus_space_read_4(sc->iot, sc->aud_ioh, 872 ICH_GCTRL + sc->sc_modem_offset); 873 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 874 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 875 } else { 876 control &= ~ICH_ACLSO; 877 control |= ICH_GIE; 878 } 879 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 880 bus_space_write_4(sc->iot, sc->aud_ioh, 881 ICH_GCTRL + sc->sc_modem_offset, control); 882 883 for (i = 500000; i >= 0; i--) { 884 status = bus_space_read_4(sc->iot, sc->aud_ioh, 885 ICH_GSTS + sc->sc_modem_offset); 886 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 887 break; 888 DELAY(1); 889 } 890 if (i <= 0) { 891 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 892 return ETIMEDOUT; 893 } 894 #ifdef AUICH_DEBUG 895 if (status & ICH_SCR) 896 printf("%s: The 2nd codec is ready.\n", 897 sc->sc_dev.dv_xname); 898 if (status & ICH_S2CR) 899 printf("%s: The 3rd codec is ready.\n", 900 sc->sc_dev.dv_xname); 901 #endif 902 return 0; 903 } 904 905 static enum ac97_host_flags 906 auich_flags_codec(void *v) 907 { 908 struct auich_softc *sc = v; 909 return sc->sc_codecflags; 910 } 911 912 static void 913 auich_spdif_event(void *addr, boolean_t flag) 914 { 915 struct auich_softc *sc; 916 917 sc = addr; 918 sc->sc_spdif = flag; 919 } 920 921 static int 922 auich_open(void *addr, int flags) 923 { 924 struct auich_softc *sc; 925 926 sc = (struct auich_softc *)addr; 927 sc->codec_if->vtbl->lock(sc->codec_if); 928 return 0; 929 } 930 931 static void 932 auich_close(void *addr) 933 { 934 struct auich_softc *sc; 935 936 sc = (struct auich_softc *)addr; 937 sc->codec_if->vtbl->unlock(sc->codec_if); 938 } 939 940 static int 941 auich_query_encoding(void *v, struct audio_encoding *aep) 942 { 943 struct auich_softc *sc; 944 945 sc = (struct auich_softc *)v; 946 return auconv_query_encoding( 947 sc->sc_spdif ? sc->sc_spdif_encodings : sc->sc_encodings, aep); 948 } 949 950 static int 951 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 952 { 953 int ret; 954 u_int ratetmp; 955 956 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 957 ratetmp = srate; 958 if (mode == AUMODE_RECORD) 959 return sc->codec_if->vtbl->set_rate(sc->codec_if, 960 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 961 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 962 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 963 if (ret) 964 return ret; 965 ratetmp = srate; 966 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 967 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 968 if (ret) 969 return ret; 970 ratetmp = srate; 971 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 972 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 973 return ret; 974 } 975 976 static int 977 auich_set_params(void *v, int setmode, int usemode, audio_params_t *play, 978 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 979 { 980 struct auich_softc *sc; 981 audio_params_t *p; 982 stream_filter_list_t *fil; 983 int mode, index; 984 uint32_t control; 985 986 sc = v; 987 for (mode = AUMODE_RECORD; mode != -1; 988 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 989 if ((setmode & mode) == 0) 990 continue; 991 992 p = mode == AUMODE_PLAY ? play : rec; 993 fil = mode == AUMODE_PLAY ? pfil : rfil; 994 if (p == NULL) 995 continue; 996 997 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 998 if (p->sample_rate < 8000 || 999 p->sample_rate > 48000) 1000 return EINVAL; 1001 1002 if (sc->sc_spdif) 1003 index = auconv_set_converter(sc->sc_audio_formats, 1004 AUICH_AUDIO_NFORMATS, mode, p, TRUE, fil); 1005 else 1006 index = auconv_set_converter(auich_spdif_formats, 1007 AUICH_SPDIF_NFORMATS, mode, p, TRUE, fil); 1008 } else { 1009 if (p->sample_rate != 8000 && p->sample_rate != 16000) 1010 return EINVAL; 1011 index = auconv_set_converter(sc->sc_modem_formats, 1012 AUICH_MODEM_NFORMATS, mode, p, TRUE, fil); 1013 } 1014 if (index < 0) 1015 return EINVAL; 1016 if (fil->req_size > 0) 1017 p = &fil->filters[0].param; 1018 /* p represents HW encoding */ 1019 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1020 if (sc->sc_audio_formats[index].frequency_type != 1 1021 && auich_set_rate(sc, mode, p->sample_rate)) 1022 return EINVAL; 1023 } else { 1024 if (sc->sc_modem_formats[index].frequency_type != 1 1025 && auich_set_rate(sc, mode, p->sample_rate)) 1026 return EINVAL; 1027 auich_write_codec(sc, AC97_REG_LINE1_RATE, 1028 p->sample_rate); 1029 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 1030 } 1031 if (mode == AUMODE_PLAY && 1032 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1033 control = bus_space_read_4(sc->iot, sc->aud_ioh, 1034 ICH_GCTRL + sc->sc_modem_offset); 1035 control &= ~ICH_PCM246_MASK; 1036 if (p->channels == 4) { 1037 control |= ICH_PCM4; 1038 } else if (p->channels == 6) { 1039 control |= ICH_PCM6; 1040 } 1041 bus_space_write_4(sc->iot, sc->aud_ioh, 1042 ICH_GCTRL + sc->sc_modem_offset, control); 1043 } 1044 } 1045 1046 return 0; 1047 } 1048 1049 static int 1050 auich_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 1051 { 1052 1053 return blk & ~0x3f; /* keep good alignment */ 1054 } 1055 1056 static void 1057 auich_halt_pipe(struct auich_softc *sc, int pipe) 1058 { 1059 int i; 1060 uint32_t status; 1061 1062 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 1063 for (i = 0; i < 100; i++) { 1064 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 1065 if (status & ICH_DCH) 1066 break; 1067 DELAY(1); 1068 } 1069 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 1070 1071 #if AUICH_DEBUG 1072 if (i > 0) 1073 printf("auich_halt_pipe: halt took %d cycles\n", i); 1074 #endif 1075 } 1076 1077 static int 1078 auich_halt_output(void *v) 1079 { 1080 struct auich_softc *sc; 1081 1082 sc = v; 1083 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 1084 1085 auich_halt_pipe(sc, ICH_PCMO); 1086 sc->pcmo.intr = NULL; 1087 1088 return 0; 1089 } 1090 1091 static int 1092 auich_halt_input(void *v) 1093 { 1094 struct auich_softc *sc; 1095 1096 sc = v; 1097 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", sc->sc_dev.dv_xname)); 1098 1099 auich_halt_pipe(sc, ICH_PCMI); 1100 sc->pcmi.intr = NULL; 1101 1102 return 0; 1103 } 1104 1105 static int 1106 auich_getdev(void *v, struct audio_device *adp) 1107 { 1108 struct auich_softc *sc; 1109 1110 sc = v; 1111 *adp = sc->sc_audev; 1112 return 0; 1113 } 1114 1115 static int 1116 auich_set_port(void *v, mixer_ctrl_t *cp) 1117 { 1118 struct auich_softc *sc; 1119 1120 sc = v; 1121 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1122 } 1123 1124 static int 1125 auich_get_port(void *v, mixer_ctrl_t *cp) 1126 { 1127 struct auich_softc *sc; 1128 1129 sc = v; 1130 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1131 } 1132 1133 static int 1134 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1135 { 1136 struct auich_softc *sc; 1137 1138 sc = v; 1139 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1140 } 1141 1142 static void * 1143 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 1144 int flags) 1145 { 1146 struct auich_softc *sc; 1147 struct auich_dma *p; 1148 int error; 1149 1150 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1151 return NULL; 1152 1153 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1154 if (p == NULL) 1155 return NULL; 1156 1157 sc = v; 1158 error = auich_allocmem(sc, size, 0, p); 1159 if (error) { 1160 free(p, pool); 1161 return NULL; 1162 } 1163 1164 p->next = sc->sc_dmas; 1165 sc->sc_dmas = p; 1166 1167 return KERNADDR(p); 1168 } 1169 1170 static void 1171 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1172 { 1173 struct auich_softc *sc; 1174 struct auich_dma *p, **pp; 1175 1176 sc = v; 1177 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1178 if (KERNADDR(p) == ptr) { 1179 auich_freemem(sc, p); 1180 *pp = p->next; 1181 free(p, pool); 1182 return; 1183 } 1184 } 1185 } 1186 1187 static size_t 1188 auich_round_buffersize(void *v, int direction, size_t size) 1189 { 1190 1191 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1192 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1193 1194 return size; 1195 } 1196 1197 static paddr_t 1198 auich_mappage(void *v, void *mem, off_t off, int prot) 1199 { 1200 struct auich_softc *sc; 1201 struct auich_dma *p; 1202 1203 if (off < 0) 1204 return -1; 1205 sc = v; 1206 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1207 continue; 1208 if (!p) 1209 return -1; 1210 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1211 off, prot, BUS_DMA_WAITOK); 1212 } 1213 1214 static int 1215 auich_get_props(void *v) 1216 { 1217 struct auich_softc *sc; 1218 int props; 1219 1220 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1221 sc = v; 1222 /* 1223 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1224 * rate because of aurateconv. Applications can't know what rate the 1225 * device can process in the case of mmap(). 1226 */ 1227 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1228 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1229 props |= AUDIO_PROP_MMAP; 1230 return props; 1231 } 1232 1233 static int 1234 auich_intr(void *v) 1235 { 1236 struct auich_softc *sc; 1237 int ret, gsts; 1238 #ifdef DIAGNOSTIC 1239 int csts; 1240 #endif 1241 1242 sc = v; 1243 ret = 0; 1244 #ifdef DIAGNOSTIC 1245 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1246 if (csts & PCI_STATUS_MASTER_ABORT) { 1247 printf("auich_intr: PCI master abort\n"); 1248 } 1249 #endif 1250 1251 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1252 ICH_GSTS + sc->sc_modem_offset); 1253 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1254 1255 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1256 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1257 int sts; 1258 1259 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1260 ICH_PCMO + sc->sc_sts_reg); 1261 DPRINTF(ICH_DEBUG_INTR, 1262 ("auich_intr: osts=0x%x\n", sts)); 1263 1264 if (sts & ICH_FIFOE) 1265 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1266 1267 if (sts & ICH_BCIS) 1268 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1269 1270 /* int ack */ 1271 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1272 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1273 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1274 bus_space_write_4(sc->iot, sc->aud_ioh, 1275 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1276 else 1277 bus_space_write_4(sc->iot, sc->aud_ioh, 1278 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1279 ret++; 1280 } 1281 1282 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1283 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1284 int sts; 1285 1286 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1287 ICH_PCMI + sc->sc_sts_reg); 1288 DPRINTF(ICH_DEBUG_INTR, 1289 ("auich_intr: ists=0x%x\n", sts)); 1290 1291 if (sts & ICH_FIFOE) 1292 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1293 1294 if (sts & ICH_BCIS) 1295 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1296 1297 /* int ack */ 1298 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1299 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1300 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1301 bus_space_write_4(sc->iot, sc->aud_ioh, 1302 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1303 else 1304 bus_space_write_4(sc->iot, sc->aud_ioh, 1305 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1306 ret++; 1307 } 1308 1309 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1310 int sts; 1311 1312 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1313 ICH_MICI + sc->sc_sts_reg); 1314 DPRINTF(ICH_DEBUG_INTR, 1315 ("auich_intr: ists=0x%x\n", sts)); 1316 1317 if (sts & ICH_FIFOE) 1318 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1319 1320 if (sts & ICH_BCIS) 1321 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1322 1323 /* int ack */ 1324 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1325 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1326 bus_space_write_4(sc->iot, sc->aud_ioh, 1327 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1328 ret++; 1329 } 1330 1331 #ifdef AUICH_MODEM_DEBUG 1332 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1333 printf("%s: gsts=0x%x\n", sc->sc_dev.dv_xname, gsts); 1334 /* int ack */ 1335 bus_space_write_4(sc->iot, sc->aud_ioh, 1336 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1337 ret++; 1338 } 1339 #endif 1340 1341 return ret; 1342 } 1343 1344 static void 1345 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1346 { 1347 int blksize, qptr; 1348 struct auich_dmalist *q; 1349 1350 blksize = ring->blksize; 1351 1352 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1353 q = &ring->dmalist[qptr]; 1354 q->base = ring->p; 1355 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1356 1357 ring->p += blksize; 1358 if (ring->p >= ring->end) 1359 ring->p = ring->start; 1360 } 1361 ring->qptr = 0; 1362 1363 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1364 (qptr - 1) & ICH_LVI_MASK); 1365 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1366 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1367 } 1368 1369 static void 1370 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1371 { 1372 int blksize, qptr, nqptr; 1373 struct auich_dmalist *q; 1374 1375 blksize = ring->blksize; 1376 qptr = ring->qptr; 1377 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1378 1379 while (qptr != nqptr) { 1380 q = &ring->dmalist[qptr]; 1381 q->base = ring->p; 1382 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1383 1384 DPRINTF(ICH_DEBUG_INTR, 1385 ("auich_intr: %p, %p = %x @ 0x%x\n", 1386 &ring->dmalist[qptr], q, q->len, q->base)); 1387 1388 ring->p += blksize; 1389 if (ring->p >= ring->end) 1390 ring->p = ring->start; 1391 1392 qptr = (qptr + 1) & ICH_LVI_MASK; 1393 if (ring->intr) 1394 ring->intr(ring->arg); 1395 } 1396 ring->qptr = qptr; 1397 1398 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1399 (qptr - 1) & ICH_LVI_MASK); 1400 } 1401 1402 static int 1403 auich_trigger_output(void *v, void *start, void *end, int blksize, 1404 void (*intr)(void *), void *arg, const audio_params_t *param) 1405 { 1406 struct auich_softc *sc; 1407 struct auich_dma *p; 1408 size_t size; 1409 1410 DPRINTF(ICH_DEBUG_DMA, 1411 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1412 start, end, blksize, intr, arg, param)); 1413 sc = v; 1414 1415 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1416 continue; 1417 if (!p) { 1418 printf("auich_trigger_output: bad addr %p\n", start); 1419 return EINVAL; 1420 } 1421 1422 size = (size_t)((caddr_t)end - (caddr_t)start); 1423 1424 sc->pcmo.intr = intr; 1425 sc->pcmo.arg = arg; 1426 sc->pcmo.start = DMAADDR(p); 1427 sc->pcmo.p = sc->pcmo.start; 1428 sc->pcmo.end = sc->pcmo.start + size; 1429 sc->pcmo.blksize = blksize; 1430 1431 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1432 sc->sc_cddma + ICH_PCMO_OFF(0)); 1433 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1434 1435 return 0; 1436 } 1437 1438 static int 1439 auich_trigger_input(void *v, void *start, void *end, int blksize, 1440 void (*intr)(void *), void *arg, const audio_params_t *param) 1441 { 1442 struct auich_softc *sc; 1443 struct auich_dma *p; 1444 size_t size; 1445 1446 DPRINTF(ICH_DEBUG_DMA, 1447 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1448 start, end, blksize, intr, arg, param)); 1449 sc = v; 1450 1451 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1452 continue; 1453 if (!p) { 1454 printf("auich_trigger_input: bad addr %p\n", start); 1455 return EINVAL; 1456 } 1457 1458 size = (size_t)((caddr_t)end - (caddr_t)start); 1459 1460 sc->pcmi.intr = intr; 1461 sc->pcmi.arg = arg; 1462 sc->pcmi.start = DMAADDR(p); 1463 sc->pcmi.p = sc->pcmi.start; 1464 sc->pcmi.end = sc->pcmi.start + size; 1465 sc->pcmi.blksize = blksize; 1466 1467 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1468 sc->sc_cddma + ICH_PCMI_OFF(0)); 1469 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1470 1471 return 0; 1472 } 1473 1474 static int 1475 auich_powerstate(void *v, int state) 1476 { 1477 #if notyet 1478 struct auich_softc *sc; 1479 int rv; 1480 1481 sc = (struct auich_softc *)v; 1482 rv = 0; 1483 1484 switch (state) { 1485 case AUDIOPOWER_OFF: 1486 auich_powerhook(PWR_SUSPEND, sc); 1487 break; 1488 case AUDIOPOWER_ON: 1489 auich_powerhook(PWR_RESUME, sc); 1490 break; 1491 default: 1492 aprint_error("%s: unknown power state %d\n", 1493 sc->sc_dev.dv_xname, state); 1494 rv = 1; 1495 break; 1496 } 1497 1498 return rv; 1499 #else 1500 return 0; 1501 #endif 1502 } 1503 1504 static int 1505 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1506 struct auich_dma *p) 1507 { 1508 int error; 1509 1510 p->size = size; 1511 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1512 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1513 &p->nsegs, BUS_DMA_NOWAIT); 1514 if (error) 1515 return error; 1516 1517 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1518 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1519 if (error) 1520 goto free; 1521 1522 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1523 0, BUS_DMA_NOWAIT, &p->map); 1524 if (error) 1525 goto unmap; 1526 1527 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1528 BUS_DMA_NOWAIT); 1529 if (error) 1530 goto destroy; 1531 return 0; 1532 1533 destroy: 1534 bus_dmamap_destroy(sc->dmat, p->map); 1535 unmap: 1536 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1537 free: 1538 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1539 return error; 1540 } 1541 1542 static int 1543 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1544 { 1545 1546 bus_dmamap_unload(sc->dmat, p->map); 1547 bus_dmamap_destroy(sc->dmat, p->map); 1548 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1549 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1550 return 0; 1551 } 1552 1553 static int 1554 auich_alloc_cdata(struct auich_softc *sc) 1555 { 1556 bus_dma_segment_t seg; 1557 int error, rseg; 1558 1559 /* 1560 * Allocate the control data structure, and create and load the 1561 * DMA map for it. 1562 */ 1563 if ((error = bus_dmamem_alloc(sc->dmat, 1564 sizeof(struct auich_cdata), 1565 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1566 printf("%s: unable to allocate control data, error = %d\n", 1567 sc->sc_dev.dv_xname, error); 1568 goto fail_0; 1569 } 1570 1571 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1572 sizeof(struct auich_cdata), 1573 (caddr_t *) &sc->sc_cdata, 1574 sc->sc_dmamap_flags)) != 0) { 1575 printf("%s: unable to map control data, error = %d\n", 1576 sc->sc_dev.dv_xname, error); 1577 goto fail_1; 1578 } 1579 1580 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1581 sizeof(struct auich_cdata), 0, 0, 1582 &sc->sc_cddmamap)) != 0) { 1583 printf("%s: unable to create control data DMA map, " 1584 "error = %d\n", sc->sc_dev.dv_xname, error); 1585 goto fail_2; 1586 } 1587 1588 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1589 sc->sc_cdata, sizeof(struct auich_cdata), 1590 NULL, 0)) != 0) { 1591 printf("%s: unable tp load control data DMA map, " 1592 "error = %d\n", sc->sc_dev.dv_xname, error); 1593 goto fail_3; 1594 } 1595 1596 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1597 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1598 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1599 1600 return 0; 1601 1602 fail_3: 1603 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1604 fail_2: 1605 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1606 sizeof(struct auich_cdata)); 1607 fail_1: 1608 bus_dmamem_free(sc->dmat, &seg, rseg); 1609 fail_0: 1610 return error; 1611 } 1612 1613 static void 1614 auich_powerhook(int why, void *addr) 1615 { 1616 struct auich_softc *sc; 1617 1618 sc = (struct auich_softc *)addr; 1619 switch (why) { 1620 case PWR_SUSPEND: 1621 case PWR_STANDBY: 1622 /* Power down */ 1623 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1624 1625 /* if we're already asleep, don't try to sleep again */ 1626 if (sc->sc_suspend == PWR_SUSPEND || 1627 sc->sc_suspend == PWR_STANDBY) 1628 break; 1629 sc->sc_suspend = why; 1630 1631 DELAY(1000); 1632 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1633 1634 if (sc->sc_ih != NULL) 1635 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1636 1637 break; 1638 1639 case PWR_RESUME: 1640 /* Wake up */ 1641 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1642 if (sc->sc_suspend == PWR_RESUME) { 1643 printf("%s: resume without suspend.\n", 1644 sc->sc_dev.dv_xname); 1645 sc->sc_suspend = why; 1646 return; 1647 } 1648 1649 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 1650 auich_intr, sc); 1651 if (sc->sc_ih == NULL) { 1652 aprint_error("%s: can't establish interrupt", 1653 sc->sc_dev.dv_xname); 1654 /* XXX jmcneill what should we do here? */ 1655 return; 1656 } 1657 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1658 sc->sc_suspend = why; 1659 auich_reset_codec(sc); 1660 DELAY(1000); 1661 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1662 break; 1663 1664 case PWR_SOFTSUSPEND: 1665 case PWR_SOFTSTANDBY: 1666 case PWR_SOFTRESUME: 1667 break; 1668 } 1669 } 1670 1671 /* 1672 * Calibrate card (some boards are overclocked and need scaling) 1673 */ 1674 static void 1675 auich_calibrate(struct auich_softc *sc) 1676 { 1677 struct timeval t1, t2; 1678 uint8_t ociv, nciv; 1679 uint64_t wait_us; 1680 uint32_t actual_48k_rate, bytes, ac97rate; 1681 void *temp_buffer; 1682 struct auich_dma *p; 1683 u_int rate; 1684 1685 /* 1686 * Grab audio from input for fixed interval and compare how 1687 * much we actually get with what we expect. Interval needs 1688 * to be sufficiently short that no interrupts are 1689 * generated. 1690 */ 1691 1692 /* Force the codec to a known state first. */ 1693 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1694 rate = sc->sc_ac97_clock = 48000; 1695 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1696 &rate); 1697 1698 /* Setup a buffer */ 1699 bytes = 64000; 1700 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1701 1702 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1703 continue; 1704 if (p == NULL) { 1705 printf("auich_calibrate: bad address %p\n", temp_buffer); 1706 return; 1707 } 1708 sc->pcmi.dmalist[0].base = DMAADDR(p); 1709 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1710 1711 /* 1712 * our data format is stereo, 16 bit so each sample is 4 bytes. 1713 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1714 * we're going to start recording with interrupts disabled and measure 1715 * the time taken for one block to complete. we know the block size, 1716 * we know the time in microseconds, we calculate the sample rate: 1717 * 1718 * actual_rate [bps] = bytes / (time [s] * 4) 1719 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1720 * actual_rate [Hz] = (bytes * 250000) / time [us] 1721 */ 1722 1723 /* prepare */ 1724 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1725 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1726 sc->sc_cddma + ICH_PCMI_OFF(0)); 1727 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1728 (0 - 1) & ICH_LVI_MASK); 1729 1730 /* start */ 1731 microtime(&t1); 1732 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1733 1734 /* wait */ 1735 nciv = ociv; 1736 do { 1737 microtime(&t2); 1738 if (t2.tv_sec - t1.tv_sec > 1) 1739 break; 1740 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1741 ICH_PCMI + ICH_CIV); 1742 } while (nciv == ociv); 1743 microtime(&t2); 1744 1745 /* stop */ 1746 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1747 1748 /* reset */ 1749 DELAY(100); 1750 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1751 1752 /* turn time delta into us */ 1753 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1754 1755 auich_freem(sc, temp_buffer, M_DEVBUF); 1756 1757 if (nciv == ociv) { 1758 printf("%s: ac97 link rate calibration timed out after %" 1759 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1760 return; 1761 } 1762 1763 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1764 1765 if (actual_48k_rate < 50000) 1766 ac97rate = 48000; 1767 else 1768 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1769 1770 printf("%s: measured ac97 link rate at %d Hz", 1771 sc->sc_dev.dv_xname, actual_48k_rate); 1772 if (ac97rate != actual_48k_rate) 1773 printf(", will use %d Hz", ac97rate); 1774 printf("\n"); 1775 1776 sc->sc_ac97_clock = ac97rate; 1777 } 1778 1779 static void 1780 auich_clear_cas(struct auich_softc *sc) 1781 { 1782 /* Clear the codec access semaphore */ 1783 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1784 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1785 1786 return; 1787 } 1788
Indexes created Wed Oct 22 13:09:56 GMT 2025