auich.c revision 1.114
1 /* $NetBSD: auich.c,v 1.114 2006/10/12 01:31:28 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.114 2006/10/12 01:31:28 christos Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 pci_intr_handle_t intrh; 187 188 struct ac97_codec_if *codec_if; 189 struct ac97_host_if host_if; 190 int sc_codecnum; 191 int sc_codectype; 192 enum ac97_host_flags sc_codecflags; 193 boolean_t sc_spdif; 194 195 /* DMA scatter-gather lists. */ 196 bus_dmamap_t sc_cddmamap; 197 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 198 199 struct auich_cdata *sc_cdata; 200 201 struct auich_ring { 202 int qptr; 203 struct auich_dmalist *dmalist; 204 205 uint32_t start, p, end; 206 int blksize; 207 208 void (*intr)(void *); 209 void *arg; 210 } pcmo, pcmi, mici; 211 212 struct auich_dma *sc_dmas; 213 214 /* SiS 7012 hack */ 215 int sc_sample_shift; 216 int sc_sts_reg; 217 /* 440MX workaround */ 218 int sc_dmamap_flags; 219 220 /* Power Management */ 221 void *sc_powerhook; 222 int sc_suspend; 223 int sc_powerstate; 224 struct pci_conf_state sc_pciconf; 225 226 /* sysctl */ 227 struct sysctllog *sc_log; 228 uint32_t sc_ac97_clock; 229 int sc_ac97_clock_mib; 230 231 int sc_modem_offset; 232 233 #define AUICH_AUDIO_NFORMATS 3 234 #define AUICH_MODEM_NFORMATS 1 235 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 236 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 237 struct audio_encoding_set *sc_encodings; 238 struct audio_encoding_set *sc_spdif_encodings; 239 }; 240 241 /* Debug */ 242 #ifdef AUICH_DEBUG 243 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 244 int auich_debug = 0xfffe; 245 #define ICH_DEBUG_CODECIO 0x0001 246 #define ICH_DEBUG_DMA 0x0002 247 #define ICH_DEBUG_INTR 0x0004 248 #else 249 #define DPRINTF(x,y) /* nothing */ 250 #endif 251 252 static int auich_match(struct device *, struct cfdata *, void *); 253 static void auich_attach(struct device *, struct device *, void *); 254 static int auich_detach(struct device *, int); 255 static int auich_activate(struct device *, enum devact); 256 static int auich_intr(void *); 257 258 CFATTACH_DECL(auich, sizeof(struct auich_softc), 259 auich_match, auich_attach, auich_detach, auich_activate); 260 261 static int auich_open(void *, int); 262 static void auich_close(void *); 263 static int auich_query_encoding(void *, struct audio_encoding *); 264 static int auich_set_params(void *, int, int, audio_params_t *, 265 audio_params_t *, stream_filter_list_t *, 266 stream_filter_list_t *); 267 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 268 static void auich_halt_pipe(struct auich_softc *, int); 269 static int auich_halt_output(void *); 270 static int auich_halt_input(void *); 271 static int auich_getdev(void *, struct audio_device *); 272 static int auich_set_port(void *, mixer_ctrl_t *); 273 static int auich_get_port(void *, mixer_ctrl_t *); 274 static int auich_query_devinfo(void *, mixer_devinfo_t *); 275 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 276 static void auich_freem(void *, void *, struct malloc_type *); 277 static size_t auich_round_buffersize(void *, int, size_t); 278 static paddr_t auich_mappage(void *, void *, off_t, int); 279 static int auich_get_props(void *); 280 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 281 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 282 static int auich_trigger_output(void *, void *, void *, int, 283 void (*)(void *), void *, const audio_params_t *); 284 static int auich_trigger_input(void *, void *, void *, int, 285 void (*)(void *), void *, const audio_params_t *); 286 static int auich_powerstate(void *, int); 287 288 static int auich_alloc_cdata(struct auich_softc *); 289 290 static int auich_allocmem(struct auich_softc *, size_t, size_t, 291 struct auich_dma *); 292 static int auich_freemem(struct auich_softc *, struct auich_dma *); 293 294 static void auich_powerhook(int, void *); 295 static int auich_set_rate(struct auich_softc *, int, u_long); 296 static int auich_sysctl_verify(SYSCTLFN_ARGS); 297 static void auich_finish_attach(struct device *); 298 static void auich_calibrate(struct auich_softc *); 299 static void auich_clear_cas(struct auich_softc *); 300 301 static int auich_attach_codec(void *, struct ac97_codec_if *); 302 static int auich_read_codec(void *, uint8_t, uint16_t *); 303 static int auich_write_codec(void *, uint8_t, uint16_t); 304 static int auich_reset_codec(void *); 305 static enum ac97_host_flags auich_flags_codec(void *); 306 static void auich_spdif_event(void *, boolean_t); 307 308 static const struct audio_hw_if auich_hw_if = { 309 auich_open, 310 auich_close, 311 NULL, /* drain */ 312 auich_query_encoding, 313 auich_set_params, 314 auich_round_blocksize, 315 NULL, /* commit_setting */ 316 NULL, /* init_output */ 317 NULL, /* init_input */ 318 NULL, /* start_output */ 319 NULL, /* start_input */ 320 auich_halt_output, 321 auich_halt_input, 322 NULL, /* speaker_ctl */ 323 auich_getdev, 324 NULL, /* getfd */ 325 auich_set_port, 326 auich_get_port, 327 auich_query_devinfo, 328 auich_allocm, 329 auich_freem, 330 auich_round_buffersize, 331 auich_mappage, 332 auich_get_props, 333 auich_trigger_output, 334 auich_trigger_input, 335 NULL, /* dev_ioctl */ 336 auich_powerstate, 337 }; 338 339 #define AUICH_FORMATS_1CH 0 340 #define AUICH_FORMATS_4CH 1 341 #define AUICH_FORMATS_6CH 2 342 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 343 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 344 2, AUFMT_STEREO, 0, {8000, 48000}}, 345 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 346 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 347 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 348 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 349 }; 350 351 #define AUICH_SPDIF_NFORMATS 1 352 static const struct audio_format auich_spdif_formats[AUICH_SPDIF_NFORMATS] = { 353 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 354 2, AUFMT_STEREO, 1, {48000}}, 355 }; 356 357 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 358 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 359 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 360 }; 361 362 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 363 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 364 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 365 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 366 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 367 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 368 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 369 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 370 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 371 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 372 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 373 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 374 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 375 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 376 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 377 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 378 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 379 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 380 #define PCIID_NFORCE430 PCI_ID_CODE0(NVIDIA, NFORCE430_AC) 381 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 382 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 383 384 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 385 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 386 387 struct auich_devtype { 388 pcireg_t id; 389 const char *name; 390 const char *shortname; /* must be less than 11 characters */ 391 }; 392 393 static const struct auich_devtype auich_audio_devices[] = { 394 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 395 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 396 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 397 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 398 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 399 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 400 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 401 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 402 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 403 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 404 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 405 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 406 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 407 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 408 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 409 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 410 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 411 { PCIID_NFORCE430, "nForce430 (MCP51) AC-97 Audio", "nForce430" }, 412 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 413 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 414 { 0, NULL, NULL }, 415 }; 416 417 static const struct auich_devtype auich_modem_devices[] = { 418 #ifdef AUICH_ATTACH_MODEM 419 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 420 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 421 #endif 422 { 0, NULL, NULL }, 423 }; 424 425 static const struct auich_devtype * 426 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 427 { 428 const struct auich_devtype *d; 429 430 for (d = auich_devices; d->name != NULL; d++) { 431 if (pa->pa_id == d->id) 432 return d; 433 } 434 435 return NULL; 436 } 437 438 static int 439 auich_match(struct device *parent __unused, struct cfdata *match __unused, 440 void *aux) 441 { 442 struct pci_attach_args *pa; 443 444 pa = aux; 445 if (auich_lookup(pa, auich_audio_devices) != NULL) 446 return 1; 447 if (auich_lookup(pa, auich_modem_devices) != NULL) 448 return 1; 449 450 return 0; 451 } 452 453 static void 454 auich_attach(struct device *parent __unused, struct device *self, void *aux) 455 { 456 struct auich_softc *sc; 457 struct pci_attach_args *pa; 458 pcireg_t v, subdev; 459 const char *intrstr; 460 const struct auich_devtype *d; 461 const struct sysctlnode *node, *node_ac97clock; 462 int err, node_mib, i; 463 464 sc = (struct auich_softc *)self; 465 pa = aux; 466 467 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 468 sc->sc_modem_offset = 0x10; 469 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 470 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 471 sc->sc_modem_offset = 0; 472 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 473 } else 474 panic("auich_attach: impossible"); 475 476 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 477 aprint_naive(": Audio controller\n"); 478 else 479 aprint_naive(": Modem controller\n"); 480 481 sc->sc_pc = pa->pa_pc; 482 sc->sc_pt = pa->pa_tag; 483 484 aprint_normal(": %s\n", d->name); 485 486 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 487 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 488 || d->id == PCIID_ICH4MODEM) { 489 /* 490 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 491 */ 492 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 493 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 494 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 495 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 496 v | ICH_CFG_IOSE); 497 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 498 0, &sc->iot, &sc->mix_ioh, NULL, 499 &sc->mix_size)) { 500 aprint_error("%s: can't map codec i/o space\n", 501 sc->sc_dev.dv_xname); 502 return; 503 } 504 } 505 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 506 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 507 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 508 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 509 v | ICH_CFG_IOSE); 510 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 511 0, &sc->iot, &sc->aud_ioh, NULL, 512 &sc->aud_size)) { 513 aprint_error("%s: can't map device i/o space\n", 514 sc->sc_dev.dv_xname); 515 return; 516 } 517 } 518 } else { 519 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 520 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 521 aprint_error("%s: can't map codec i/o space\n", 522 sc->sc_dev.dv_xname); 523 return; 524 } 525 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 526 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 527 aprint_error("%s: can't map device i/o space\n", 528 sc->sc_dev.dv_xname); 529 return; 530 } 531 } 532 sc->dmat = pa->pa_dmat; 533 534 /* enable bus mastering */ 535 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 536 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 537 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 538 539 /* Map and establish the interrupt. */ 540 if (pci_intr_map(pa, &sc->intrh)) { 541 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 542 return; 543 } 544 intrstr = pci_intr_string(pa->pa_pc, sc->intrh); 545 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO, 546 auich_intr, sc); 547 if (sc->sc_ih == NULL) { 548 aprint_error("%s: can't establish interrupt", 549 sc->sc_dev.dv_xname); 550 if (intrstr != NULL) 551 aprint_normal(" at %s", intrstr); 552 aprint_normal("\n"); 553 return; 554 } 555 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 556 557 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 558 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 559 "0x%02x", PCI_REVISION(pa->pa_class)); 560 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 561 562 /* SiS 7012 needs special handling */ 563 if (d->id == PCIID_SIS7012) { 564 sc->sc_sts_reg = ICH_PICB; 565 sc->sc_sample_shift = 0; 566 /* Un-mute output. From Linux. */ 567 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 568 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 569 ICH_SIS_CTL_UNMUTE); 570 } else { 571 sc->sc_sts_reg = ICH_STS; 572 sc->sc_sample_shift = 1; 573 } 574 575 /* Workaround for a 440MX B-stepping erratum */ 576 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 577 if (d->id == PCIID_440MX) { 578 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 579 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 580 } 581 582 /* Set up DMA lists. */ 583 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 584 auich_alloc_cdata(sc); 585 586 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 587 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 588 589 /* Modem codecs are always the secondary codec on ICH */ 590 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 591 592 sc->host_if.arg = sc; 593 sc->host_if.attach = auich_attach_codec; 594 sc->host_if.read = auich_read_codec; 595 sc->host_if.write = auich_write_codec; 596 sc->host_if.reset = auich_reset_codec; 597 sc->host_if.flags = auich_flags_codec; 598 sc->host_if.spdif_event = auich_spdif_event; 599 600 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 601 switch (subdev) { 602 case 0x202f161f: /* Gateway 7326GZ */ 603 case 0x203a161f: /* Gateway 4028GZ */ 604 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 605 case 0x8144104d: /* Sony VAIO PCG-TR* */ 606 case 0x8197104d: /* Sony S1XP */ 607 case 0x81c0104d: /* Sony VAIO type T */ 608 case 0x81c5104d: /* Sony VAIO VGN-B1XP */ 609 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP; 610 break; 611 default: 612 sc->sc_codecflags = 0; 613 break; 614 } 615 616 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 617 return; 618 sc->codec_if->vtbl->unlock(sc->codec_if); 619 620 /* setup audio_format */ 621 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 622 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 623 if (!AC97_IS_4CH(sc->codec_if)) 624 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 625 if (!AC97_IS_6CH(sc->codec_if)) 626 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 627 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 628 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 629 sc->sc_audio_formats[i].frequency_type = 1; 630 sc->sc_audio_formats[i].frequency[0] = 48000; 631 } 632 } 633 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 634 &sc->sc_encodings)) 635 return; 636 if (0 != auconv_create_encodings(auich_spdif_formats, AUICH_SPDIF_NFORMATS, 637 &sc->sc_spdif_encodings)) 638 return; 639 } else { 640 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 641 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 642 &sc->sc_encodings)) 643 return; 644 } 645 646 647 /* Watch for power change */ 648 sc->sc_suspend = PWR_RESUME; 649 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 650 auich_powerhook, sc); 651 652 config_interrupts(self, auich_finish_attach); 653 654 /* sysctl setup */ 655 if (AC97_IS_FIXED_RATE(sc->codec_if) && 656 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 657 return; 658 659 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 660 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 661 CTL_HW, CTL_EOL); 662 if (err != 0) 663 goto sysctl_err; 664 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 665 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 666 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 667 if (err != 0) 668 goto sysctl_err; 669 node_mib = node->sysctl_num; 670 671 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 672 /* passing the sc address instead of &sc->sc_ac97_clock */ 673 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 674 CTLFLAG_READWRITE, 675 CTLTYPE_INT, "ac97rate", 676 SYSCTL_DESCR("AC'97 codec link rate"), 677 auich_sysctl_verify, 0, sc, 0, 678 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 679 if (err != 0) 680 goto sysctl_err; 681 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 682 } 683 684 return; 685 686 sysctl_err: 687 printf("%s: failed to add sysctl nodes. (%d)\n", 688 sc->sc_dev.dv_xname, err); 689 return; /* failure of sysctl is not fatal. */ 690 } 691 692 static int 693 auich_activate(struct device *self, enum devact act) 694 { 695 struct auich_softc *sc; 696 int ret; 697 698 sc = (struct auich_softc *)self; 699 ret = 0; 700 switch (act) { 701 case DVACT_ACTIVATE: 702 return EOPNOTSUPP; 703 case DVACT_DEACTIVATE: 704 if (sc->sc_audiodev != NULL) 705 ret = config_deactivate(sc->sc_audiodev); 706 return ret; 707 } 708 return EOPNOTSUPP; 709 } 710 711 static int 712 auich_detach(struct device *self, int flags) 713 { 714 struct auich_softc *sc; 715 716 sc = (struct auich_softc *)self; 717 718 /* audio */ 719 if (sc->sc_audiodev != NULL) 720 config_detach(sc->sc_audiodev, flags); 721 722 /* sysctl */ 723 sysctl_teardown(&sc->sc_log); 724 725 /* audio_encoding_set */ 726 auconv_delete_encodings(sc->sc_encodings); 727 auconv_delete_encodings(sc->sc_spdif_encodings); 728 729 /* ac97 */ 730 if (sc->codec_if != NULL) 731 sc->codec_if->vtbl->detach(sc->codec_if); 732 733 /* PCI */ 734 if (sc->sc_ih != NULL) 735 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 736 if (sc->mix_size != 0) 737 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 738 if (sc->aud_size != 0) 739 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 740 return 0; 741 } 742 743 static int 744 auich_sysctl_verify(SYSCTLFN_ARGS) 745 { 746 int error, tmp; 747 struct sysctlnode node; 748 struct auich_softc *sc; 749 750 node = *rnode; 751 sc = rnode->sysctl_data; 752 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 753 tmp = sc->sc_ac97_clock; 754 node.sysctl_data = &tmp; 755 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 756 if (error || newp == NULL) 757 return error; 758 759 if (tmp < 48000 || tmp > 96000) 760 return EINVAL; 761 sc->sc_ac97_clock = tmp; 762 } 763 764 return 0; 765 } 766 767 static void 768 auich_finish_attach(struct device *self) 769 { 770 struct auich_softc *sc; 771 772 sc = (void *)self; 773 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 774 auich_calibrate(sc); 775 776 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 777 778 #if notyet 779 auich_powerhook(PWR_SUSPEND, sc); 780 #endif 781 782 return; 783 } 784 785 #define ICH_CODECIO_INTERVAL 10 786 static int 787 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 788 { 789 struct auich_softc *sc; 790 int i; 791 uint32_t status; 792 793 sc = v; 794 /* wait for an access semaphore */ 795 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 796 bus_space_read_1(sc->iot, sc->aud_ioh, 797 ICH_CAS + sc->sc_modem_offset) & 1; 798 DELAY(ICH_CODECIO_INTERVAL)); 799 800 if (i > 0) { 801 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 802 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 803 DPRINTF(ICH_DEBUG_CODECIO, 804 ("auich_read_codec(%x, %x)\n", reg, *val)); 805 status = bus_space_read_4(sc->iot, sc->aud_ioh, 806 ICH_GSTS + sc->sc_modem_offset); 807 if (status & ICH_RCS) { 808 bus_space_write_4(sc->iot, sc->aud_ioh, 809 ICH_GSTS + sc->sc_modem_offset, 810 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 811 *val = 0xffff; 812 DPRINTF(ICH_DEBUG_CODECIO, 813 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 814 if (reg == AC97_REG_GPIO_STATUS) 815 auich_clear_cas(sc); 816 return -1; 817 } 818 if (reg == AC97_REG_GPIO_STATUS) 819 auich_clear_cas(sc); 820 return 0; 821 } else { 822 aprint_normal("%s: read_codec timeout\n", sc->sc_dev.dv_xname); 823 if (reg == AC97_REG_GPIO_STATUS) 824 auich_clear_cas(sc); 825 return -1; 826 } 827 } 828 829 static int 830 auich_write_codec(void *v, uint8_t reg, uint16_t val) 831 { 832 struct auich_softc *sc; 833 int i; 834 835 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 836 sc = v; 837 /* wait for an access semaphore */ 838 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 839 bus_space_read_1(sc->iot, sc->aud_ioh, 840 ICH_CAS + sc->sc_modem_offset) & 1; 841 DELAY(ICH_CODECIO_INTERVAL)); 842 843 if (i > 0) { 844 bus_space_write_2(sc->iot, sc->mix_ioh, 845 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 846 return 0; 847 } else { 848 aprint_normal("%s: write_codec timeout\n", sc->sc_dev.dv_xname); 849 return -1; 850 } 851 } 852 853 static int 854 auich_attach_codec(void *v, struct ac97_codec_if *cif) 855 { 856 struct auich_softc *sc; 857 858 sc = v; 859 sc->codec_if = cif; 860 861 return 0; 862 } 863 864 static int 865 auich_reset_codec(void *v) 866 { 867 struct auich_softc *sc; 868 int i; 869 uint32_t control, status; 870 871 sc = v; 872 control = bus_space_read_4(sc->iot, sc->aud_ioh, 873 ICH_GCTRL + sc->sc_modem_offset); 874 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 875 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 876 } else { 877 control &= ~ICH_ACLSO; 878 control |= ICH_GIE; 879 } 880 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 881 bus_space_write_4(sc->iot, sc->aud_ioh, 882 ICH_GCTRL + sc->sc_modem_offset, control); 883 884 for (i = 500000; i >= 0; i--) { 885 status = bus_space_read_4(sc->iot, sc->aud_ioh, 886 ICH_GSTS + sc->sc_modem_offset); 887 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 888 break; 889 DELAY(1); 890 } 891 if (i <= 0) { 892 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 893 return ETIMEDOUT; 894 } 895 #ifdef AUICH_DEBUG 896 if (status & ICH_SCR) 897 printf("%s: The 2nd codec is ready.\n", 898 sc->sc_dev.dv_xname); 899 if (status & ICH_S2CR) 900 printf("%s: The 3rd codec is ready.\n", 901 sc->sc_dev.dv_xname); 902 #endif 903 return 0; 904 } 905 906 static enum ac97_host_flags 907 auich_flags_codec(void *v) 908 { 909 struct auich_softc *sc = v; 910 return sc->sc_codecflags; 911 } 912 913 static void 914 auich_spdif_event(void *addr, boolean_t flag) 915 { 916 struct auich_softc *sc; 917 918 sc = addr; 919 sc->sc_spdif = flag; 920 } 921 922 static int 923 auich_open(void *addr, int flags __unused) 924 { 925 struct auich_softc *sc; 926 927 sc = (struct auich_softc *)addr; 928 sc->codec_if->vtbl->lock(sc->codec_if); 929 return 0; 930 } 931 932 static void 933 auich_close(void *addr) 934 { 935 struct auich_softc *sc; 936 937 sc = (struct auich_softc *)addr; 938 sc->codec_if->vtbl->unlock(sc->codec_if); 939 } 940 941 static int 942 auich_query_encoding(void *v, struct audio_encoding *aep) 943 { 944 struct auich_softc *sc; 945 946 sc = (struct auich_softc *)v; 947 return auconv_query_encoding( 948 sc->sc_spdif ? sc->sc_spdif_encodings : sc->sc_encodings, aep); 949 } 950 951 static int 952 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 953 { 954 int ret; 955 u_int ratetmp; 956 957 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 958 ratetmp = srate; 959 if (mode == AUMODE_RECORD) 960 return sc->codec_if->vtbl->set_rate(sc->codec_if, 961 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 962 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 963 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 964 if (ret) 965 return ret; 966 ratetmp = srate; 967 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 968 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 969 if (ret) 970 return ret; 971 ratetmp = srate; 972 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 973 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 974 return ret; 975 } 976 977 static int 978 auich_set_params(void *v, int setmode, int usemode __unused, 979 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 980 stream_filter_list_t *rfil) 981 { 982 struct auich_softc *sc; 983 audio_params_t *p; 984 stream_filter_list_t *fil; 985 int mode, index; 986 uint32_t control; 987 988 sc = v; 989 for (mode = AUMODE_RECORD; mode != -1; 990 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 991 if ((setmode & mode) == 0) 992 continue; 993 994 p = mode == AUMODE_PLAY ? play : rec; 995 fil = mode == AUMODE_PLAY ? pfil : rfil; 996 if (p == NULL) 997 continue; 998 999 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1000 if (p->sample_rate < 8000 || 1001 p->sample_rate > 48000) 1002 return EINVAL; 1003 1004 if (sc->sc_spdif) 1005 index = auconv_set_converter(sc->sc_audio_formats, 1006 AUICH_AUDIO_NFORMATS, mode, p, TRUE, fil); 1007 else 1008 index = auconv_set_converter(auich_spdif_formats, 1009 AUICH_SPDIF_NFORMATS, mode, p, TRUE, fil); 1010 } else { 1011 if (p->sample_rate != 8000 && p->sample_rate != 16000) 1012 return EINVAL; 1013 index = auconv_set_converter(sc->sc_modem_formats, 1014 AUICH_MODEM_NFORMATS, mode, p, TRUE, fil); 1015 } 1016 if (index < 0) 1017 return EINVAL; 1018 if (fil->req_size > 0) 1019 p = &fil->filters[0].param; 1020 /* p represents HW encoding */ 1021 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1022 if (sc->sc_audio_formats[index].frequency_type != 1 1023 && auich_set_rate(sc, mode, p->sample_rate)) 1024 return EINVAL; 1025 } else { 1026 if (sc->sc_modem_formats[index].frequency_type != 1 1027 && auich_set_rate(sc, mode, p->sample_rate)) 1028 return EINVAL; 1029 auich_write_codec(sc, AC97_REG_LINE1_RATE, 1030 p->sample_rate); 1031 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 1032 } 1033 if (mode == AUMODE_PLAY && 1034 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1035 control = bus_space_read_4(sc->iot, sc->aud_ioh, 1036 ICH_GCTRL + sc->sc_modem_offset); 1037 control &= ~ICH_PCM246_MASK; 1038 if (p->channels == 4) { 1039 control |= ICH_PCM4; 1040 } else if (p->channels == 6) { 1041 control |= ICH_PCM6; 1042 } 1043 bus_space_write_4(sc->iot, sc->aud_ioh, 1044 ICH_GCTRL + sc->sc_modem_offset, control); 1045 } 1046 } 1047 1048 return 0; 1049 } 1050 1051 static int 1052 auich_round_blocksize(void *v __unused, int blk, int mode __unused, 1053 const audio_params_t *param __unused) 1054 { 1055 1056 return blk & ~0x3f; /* keep good alignment */ 1057 } 1058 1059 static void 1060 auich_halt_pipe(struct auich_softc *sc, int pipe) 1061 { 1062 int i; 1063 uint32_t status; 1064 1065 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 1066 for (i = 0; i < 100; i++) { 1067 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 1068 if (status & ICH_DCH) 1069 break; 1070 DELAY(1); 1071 } 1072 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 1073 1074 #if AUICH_DEBUG 1075 if (i > 0) 1076 printf("auich_halt_pipe: halt took %d cycles\n", i); 1077 #endif 1078 } 1079 1080 static int 1081 auich_halt_output(void *v) 1082 { 1083 struct auich_softc *sc; 1084 1085 sc = v; 1086 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 1087 1088 auich_halt_pipe(sc, ICH_PCMO); 1089 sc->pcmo.intr = NULL; 1090 1091 return 0; 1092 } 1093 1094 static int 1095 auich_halt_input(void *v) 1096 { 1097 struct auich_softc *sc; 1098 1099 sc = v; 1100 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", sc->sc_dev.dv_xname)); 1101 1102 auich_halt_pipe(sc, ICH_PCMI); 1103 sc->pcmi.intr = NULL; 1104 1105 return 0; 1106 } 1107 1108 static int 1109 auich_getdev(void *v, struct audio_device *adp) 1110 { 1111 struct auich_softc *sc; 1112 1113 sc = v; 1114 *adp = sc->sc_audev; 1115 return 0; 1116 } 1117 1118 static int 1119 auich_set_port(void *v, mixer_ctrl_t *cp) 1120 { 1121 struct auich_softc *sc; 1122 1123 sc = v; 1124 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1125 } 1126 1127 static int 1128 auich_get_port(void *v, mixer_ctrl_t *cp) 1129 { 1130 struct auich_softc *sc; 1131 1132 sc = v; 1133 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1134 } 1135 1136 static int 1137 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1138 { 1139 struct auich_softc *sc; 1140 1141 sc = v; 1142 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1143 } 1144 1145 static void * 1146 auich_allocm(void *v, int direction __unused, size_t size, 1147 struct malloc_type *pool, int flags) 1148 { 1149 struct auich_softc *sc; 1150 struct auich_dma *p; 1151 int error; 1152 1153 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1154 return NULL; 1155 1156 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1157 if (p == NULL) 1158 return NULL; 1159 1160 sc = v; 1161 error = auich_allocmem(sc, size, 0, p); 1162 if (error) { 1163 free(p, pool); 1164 return NULL; 1165 } 1166 1167 p->next = sc->sc_dmas; 1168 sc->sc_dmas = p; 1169 1170 return KERNADDR(p); 1171 } 1172 1173 static void 1174 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1175 { 1176 struct auich_softc *sc; 1177 struct auich_dma *p, **pp; 1178 1179 sc = v; 1180 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1181 if (KERNADDR(p) == ptr) { 1182 auich_freemem(sc, p); 1183 *pp = p->next; 1184 free(p, pool); 1185 return; 1186 } 1187 } 1188 } 1189 1190 static size_t 1191 auich_round_buffersize(void *v __unused, int direction __unused, size_t size) 1192 { 1193 1194 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1195 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1196 1197 return size; 1198 } 1199 1200 static paddr_t 1201 auich_mappage(void *v, void *mem, off_t off, int prot) 1202 { 1203 struct auich_softc *sc; 1204 struct auich_dma *p; 1205 1206 if (off < 0) 1207 return -1; 1208 sc = v; 1209 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1210 continue; 1211 if (!p) 1212 return -1; 1213 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1214 off, prot, BUS_DMA_WAITOK); 1215 } 1216 1217 static int 1218 auich_get_props(void *v) 1219 { 1220 struct auich_softc *sc; 1221 int props; 1222 1223 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1224 sc = v; 1225 /* 1226 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1227 * rate because of aurateconv. Applications can't know what rate the 1228 * device can process in the case of mmap(). 1229 */ 1230 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1231 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1232 props |= AUDIO_PROP_MMAP; 1233 return props; 1234 } 1235 1236 static int 1237 auich_intr(void *v) 1238 { 1239 struct auich_softc *sc; 1240 int ret, gsts; 1241 #ifdef DIAGNOSTIC 1242 int csts; 1243 #endif 1244 1245 sc = v; 1246 ret = 0; 1247 #ifdef DIAGNOSTIC 1248 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1249 if (csts & PCI_STATUS_MASTER_ABORT) { 1250 printf("auich_intr: PCI master abort\n"); 1251 } 1252 #endif 1253 1254 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1255 ICH_GSTS + sc->sc_modem_offset); 1256 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1257 1258 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1259 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1260 int sts; 1261 1262 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1263 ICH_PCMO + sc->sc_sts_reg); 1264 DPRINTF(ICH_DEBUG_INTR, 1265 ("auich_intr: osts=0x%x\n", sts)); 1266 1267 if (sts & ICH_FIFOE) 1268 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1269 1270 if (sts & ICH_BCIS) 1271 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1272 1273 /* int ack */ 1274 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1275 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1276 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1277 bus_space_write_4(sc->iot, sc->aud_ioh, 1278 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1279 else 1280 bus_space_write_4(sc->iot, sc->aud_ioh, 1281 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1282 ret++; 1283 } 1284 1285 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1286 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1287 int sts; 1288 1289 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1290 ICH_PCMI + sc->sc_sts_reg); 1291 DPRINTF(ICH_DEBUG_INTR, 1292 ("auich_intr: ists=0x%x\n", sts)); 1293 1294 if (sts & ICH_FIFOE) 1295 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1296 1297 if (sts & ICH_BCIS) 1298 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1299 1300 /* int ack */ 1301 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1302 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1303 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1304 bus_space_write_4(sc->iot, sc->aud_ioh, 1305 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1306 else 1307 bus_space_write_4(sc->iot, sc->aud_ioh, 1308 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1309 ret++; 1310 } 1311 1312 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1313 int sts; 1314 1315 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1316 ICH_MICI + sc->sc_sts_reg); 1317 DPRINTF(ICH_DEBUG_INTR, 1318 ("auich_intr: ists=0x%x\n", sts)); 1319 1320 if (sts & ICH_FIFOE) 1321 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1322 1323 if (sts & ICH_BCIS) 1324 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1325 1326 /* int ack */ 1327 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1328 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1329 bus_space_write_4(sc->iot, sc->aud_ioh, 1330 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1331 ret++; 1332 } 1333 1334 #ifdef AUICH_MODEM_DEBUG 1335 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1336 printf("%s: gsts=0x%x\n", sc->sc_dev.dv_xname, gsts); 1337 /* int ack */ 1338 bus_space_write_4(sc->iot, sc->aud_ioh, 1339 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1340 ret++; 1341 } 1342 #endif 1343 1344 return ret; 1345 } 1346 1347 static void 1348 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1349 { 1350 int blksize, qptr; 1351 struct auich_dmalist *q; 1352 1353 blksize = ring->blksize; 1354 1355 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1356 q = &ring->dmalist[qptr]; 1357 q->base = ring->p; 1358 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1359 1360 ring->p += blksize; 1361 if (ring->p >= ring->end) 1362 ring->p = ring->start; 1363 } 1364 ring->qptr = 0; 1365 1366 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1367 (qptr - 1) & ICH_LVI_MASK); 1368 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1369 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1370 } 1371 1372 static void 1373 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1374 { 1375 int blksize, qptr, nqptr; 1376 struct auich_dmalist *q; 1377 1378 blksize = ring->blksize; 1379 qptr = ring->qptr; 1380 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1381 1382 while (qptr != nqptr) { 1383 q = &ring->dmalist[qptr]; 1384 q->base = ring->p; 1385 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1386 1387 DPRINTF(ICH_DEBUG_INTR, 1388 ("auich_intr: %p, %p = %x @ 0x%x\n", 1389 &ring->dmalist[qptr], q, q->len, q->base)); 1390 1391 ring->p += blksize; 1392 if (ring->p >= ring->end) 1393 ring->p = ring->start; 1394 1395 qptr = (qptr + 1) & ICH_LVI_MASK; 1396 if (ring->intr) 1397 ring->intr(ring->arg); 1398 } 1399 ring->qptr = qptr; 1400 1401 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1402 (qptr - 1) & ICH_LVI_MASK); 1403 } 1404 1405 static int 1406 auich_trigger_output(void *v, void *start, void *end, int blksize, 1407 void (*intr)(void *), void *arg, const audio_params_t *param __unused) 1408 { 1409 struct auich_softc *sc; 1410 struct auich_dma *p; 1411 size_t size; 1412 1413 DPRINTF(ICH_DEBUG_DMA, 1414 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1415 start, end, blksize, intr, arg, param)); 1416 sc = v; 1417 1418 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1419 continue; 1420 if (!p) { 1421 printf("auich_trigger_output: bad addr %p\n", start); 1422 return EINVAL; 1423 } 1424 1425 size = (size_t)((caddr_t)end - (caddr_t)start); 1426 1427 sc->pcmo.intr = intr; 1428 sc->pcmo.arg = arg; 1429 sc->pcmo.start = DMAADDR(p); 1430 sc->pcmo.p = sc->pcmo.start; 1431 sc->pcmo.end = sc->pcmo.start + size; 1432 sc->pcmo.blksize = blksize; 1433 1434 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1435 sc->sc_cddma + ICH_PCMO_OFF(0)); 1436 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1437 1438 return 0; 1439 } 1440 1441 static int 1442 auich_trigger_input(void *v, void *start, void *end, int blksize, 1443 void (*intr)(void *), void *arg, const audio_params_t *param __unused) 1444 { 1445 struct auich_softc *sc; 1446 struct auich_dma *p; 1447 size_t size; 1448 1449 DPRINTF(ICH_DEBUG_DMA, 1450 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1451 start, end, blksize, intr, arg, param)); 1452 sc = v; 1453 1454 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1455 continue; 1456 if (!p) { 1457 printf("auich_trigger_input: bad addr %p\n", start); 1458 return EINVAL; 1459 } 1460 1461 size = (size_t)((caddr_t)end - (caddr_t)start); 1462 1463 sc->pcmi.intr = intr; 1464 sc->pcmi.arg = arg; 1465 sc->pcmi.start = DMAADDR(p); 1466 sc->pcmi.p = sc->pcmi.start; 1467 sc->pcmi.end = sc->pcmi.start + size; 1468 sc->pcmi.blksize = blksize; 1469 1470 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1471 sc->sc_cddma + ICH_PCMI_OFF(0)); 1472 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1473 1474 return 0; 1475 } 1476 1477 static int 1478 auich_powerstate(void *v __unused, int state __unused) 1479 { 1480 #if notyet 1481 struct auich_softc *sc; 1482 int rv; 1483 1484 sc = (struct auich_softc *)v; 1485 rv = 0; 1486 1487 switch (state) { 1488 case AUDIOPOWER_OFF: 1489 auich_powerhook(PWR_SUSPEND, sc); 1490 break; 1491 case AUDIOPOWER_ON: 1492 auich_powerhook(PWR_RESUME, sc); 1493 break; 1494 default: 1495 aprint_error("%s: unknown power state %d\n", 1496 sc->sc_dev.dv_xname, state); 1497 rv = 1; 1498 break; 1499 } 1500 1501 return rv; 1502 #else 1503 return 0; 1504 #endif 1505 } 1506 1507 static int 1508 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1509 struct auich_dma *p) 1510 { 1511 int error; 1512 1513 p->size = size; 1514 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1515 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1516 &p->nsegs, BUS_DMA_NOWAIT); 1517 if (error) 1518 return error; 1519 1520 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1521 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1522 if (error) 1523 goto free; 1524 1525 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1526 0, BUS_DMA_NOWAIT, &p->map); 1527 if (error) 1528 goto unmap; 1529 1530 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1531 BUS_DMA_NOWAIT); 1532 if (error) 1533 goto destroy; 1534 return 0; 1535 1536 destroy: 1537 bus_dmamap_destroy(sc->dmat, p->map); 1538 unmap: 1539 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1540 free: 1541 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1542 return error; 1543 } 1544 1545 static int 1546 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1547 { 1548 1549 bus_dmamap_unload(sc->dmat, p->map); 1550 bus_dmamap_destroy(sc->dmat, p->map); 1551 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1552 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1553 return 0; 1554 } 1555 1556 static int 1557 auich_alloc_cdata(struct auich_softc *sc) 1558 { 1559 bus_dma_segment_t seg; 1560 int error, rseg; 1561 1562 /* 1563 * Allocate the control data structure, and create and load the 1564 * DMA map for it. 1565 */ 1566 if ((error = bus_dmamem_alloc(sc->dmat, 1567 sizeof(struct auich_cdata), 1568 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1569 printf("%s: unable to allocate control data, error = %d\n", 1570 sc->sc_dev.dv_xname, error); 1571 goto fail_0; 1572 } 1573 1574 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1575 sizeof(struct auich_cdata), 1576 (caddr_t *) &sc->sc_cdata, 1577 sc->sc_dmamap_flags)) != 0) { 1578 printf("%s: unable to map control data, error = %d\n", 1579 sc->sc_dev.dv_xname, error); 1580 goto fail_1; 1581 } 1582 1583 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1584 sizeof(struct auich_cdata), 0, 0, 1585 &sc->sc_cddmamap)) != 0) { 1586 printf("%s: unable to create control data DMA map, " 1587 "error = %d\n", sc->sc_dev.dv_xname, error); 1588 goto fail_2; 1589 } 1590 1591 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1592 sc->sc_cdata, sizeof(struct auich_cdata), 1593 NULL, 0)) != 0) { 1594 printf("%s: unable tp load control data DMA map, " 1595 "error = %d\n", sc->sc_dev.dv_xname, error); 1596 goto fail_3; 1597 } 1598 1599 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1600 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1601 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1602 1603 return 0; 1604 1605 fail_3: 1606 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1607 fail_2: 1608 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1609 sizeof(struct auich_cdata)); 1610 fail_1: 1611 bus_dmamem_free(sc->dmat, &seg, rseg); 1612 fail_0: 1613 return error; 1614 } 1615 1616 static void 1617 auich_powerhook(int why, void *addr) 1618 { 1619 struct auich_softc *sc; 1620 1621 sc = (struct auich_softc *)addr; 1622 switch (why) { 1623 case PWR_SUSPEND: 1624 case PWR_STANDBY: 1625 /* Power down */ 1626 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1627 1628 /* if we're already asleep, don't try to sleep again */ 1629 if (sc->sc_suspend == PWR_SUSPEND || 1630 sc->sc_suspend == PWR_STANDBY) 1631 break; 1632 sc->sc_suspend = why; 1633 1634 DELAY(1000); 1635 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1636 1637 if (sc->sc_ih != NULL) 1638 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1639 1640 break; 1641 1642 case PWR_RESUME: 1643 /* Wake up */ 1644 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1645 if (sc->sc_suspend == PWR_RESUME) { 1646 printf("%s: resume without suspend.\n", 1647 sc->sc_dev.dv_xname); 1648 sc->sc_suspend = why; 1649 return; 1650 } 1651 1652 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 1653 auich_intr, sc); 1654 if (sc->sc_ih == NULL) { 1655 aprint_error("%s: can't establish interrupt", 1656 sc->sc_dev.dv_xname); 1657 /* XXX jmcneill what should we do here? */ 1658 return; 1659 } 1660 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1661 sc->sc_suspend = why; 1662 auich_reset_codec(sc); 1663 DELAY(1000); 1664 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1665 break; 1666 1667 case PWR_SOFTSUSPEND: 1668 case PWR_SOFTSTANDBY: 1669 case PWR_SOFTRESUME: 1670 break; 1671 } 1672 } 1673 1674 /* 1675 * Calibrate card (some boards are overclocked and need scaling) 1676 */ 1677 static void 1678 auich_calibrate(struct auich_softc *sc) 1679 { 1680 struct timeval t1, t2; 1681 uint8_t ociv, nciv; 1682 uint64_t wait_us; 1683 uint32_t actual_48k_rate, bytes, ac97rate; 1684 void *temp_buffer; 1685 struct auich_dma *p; 1686 u_int rate; 1687 1688 /* 1689 * Grab audio from input for fixed interval and compare how 1690 * much we actually get with what we expect. Interval needs 1691 * to be sufficiently short that no interrupts are 1692 * generated. 1693 */ 1694 1695 /* Force the codec to a known state first. */ 1696 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1697 rate = sc->sc_ac97_clock = 48000; 1698 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1699 &rate); 1700 1701 /* Setup a buffer */ 1702 bytes = 64000; 1703 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1704 1705 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1706 continue; 1707 if (p == NULL) { 1708 printf("auich_calibrate: bad address %p\n", temp_buffer); 1709 return; 1710 } 1711 sc->pcmi.dmalist[0].base = DMAADDR(p); 1712 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1713 1714 /* 1715 * our data format is stereo, 16 bit so each sample is 4 bytes. 1716 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1717 * we're going to start recording with interrupts disabled and measure 1718 * the time taken for one block to complete. we know the block size, 1719 * we know the time in microseconds, we calculate the sample rate: 1720 * 1721 * actual_rate [bps] = bytes / (time [s] * 4) 1722 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1723 * actual_rate [Hz] = (bytes * 250000) / time [us] 1724 */ 1725 1726 /* prepare */ 1727 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1728 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1729 sc->sc_cddma + ICH_PCMI_OFF(0)); 1730 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1731 (0 - 1) & ICH_LVI_MASK); 1732 1733 /* start */ 1734 microtime(&t1); 1735 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1736 1737 /* wait */ 1738 nciv = ociv; 1739 do { 1740 microtime(&t2); 1741 if (t2.tv_sec - t1.tv_sec > 1) 1742 break; 1743 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1744 ICH_PCMI + ICH_CIV); 1745 } while (nciv == ociv); 1746 microtime(&t2); 1747 1748 /* stop */ 1749 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1750 1751 /* reset */ 1752 DELAY(100); 1753 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1754 1755 /* turn time delta into us */ 1756 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1757 1758 auich_freem(sc, temp_buffer, M_DEVBUF); 1759 1760 if (nciv == ociv) { 1761 printf("%s: ac97 link rate calibration timed out after %" 1762 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1763 return; 1764 } 1765 1766 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1767 1768 if (actual_48k_rate < 50000) 1769 ac97rate = 48000; 1770 else 1771 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1772 1773 printf("%s: measured ac97 link rate at %d Hz", 1774 sc->sc_dev.dv_xname, actual_48k_rate); 1775 if (ac97rate != actual_48k_rate) 1776 printf(", will use %d Hz", ac97rate); 1777 printf("\n"); 1778 1779 sc->sc_ac97_clock = ac97rate; 1780 } 1781 1782 static void 1783 auich_clear_cas(struct auich_softc *sc) 1784 { 1785 /* Clear the codec access semaphore */ 1786 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1787 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1788 1789 return; 1790 } 1791
Indexes created Fri Sep 26 20:09:58 GMT 2025