auich.c revision 1.118
1 /* $NetBSD: auich.c,v 1.118 2007/09/02 00:48:52 xtraeme Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.118 2007/09/02 00:48:52 xtraeme Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 void *addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 pci_intr_handle_t intrh; 187 188 struct ac97_codec_if *codec_if; 189 struct ac97_host_if host_if; 190 int sc_codecnum; 191 int sc_codectype; 192 enum ac97_host_flags sc_codecflags; 193 bool sc_spdif; 194 195 /* DMA scatter-gather lists. */ 196 bus_dmamap_t sc_cddmamap; 197 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 198 199 struct auich_cdata *sc_cdata; 200 201 struct auich_ring { 202 int qptr; 203 struct auich_dmalist *dmalist; 204 205 uint32_t start, p, end; 206 int blksize; 207 208 void (*intr)(void *); 209 void *arg; 210 } pcmo, pcmi, mici; 211 212 struct auich_dma *sc_dmas; 213 214 /* SiS 7012 hack */ 215 int sc_sample_shift; 216 int sc_sts_reg; 217 /* 440MX workaround */ 218 int sc_dmamap_flags; 219 220 /* Power Management */ 221 void *sc_powerhook; 222 int sc_suspend; 223 int sc_powerstate; 224 struct pci_conf_state sc_pciconf; 225 226 /* sysctl */ 227 struct sysctllog *sc_log; 228 uint32_t sc_ac97_clock; 229 int sc_ac97_clock_mib; 230 231 int sc_modem_offset; 232 233 #define AUICH_AUDIO_NFORMATS 3 234 #define AUICH_MODEM_NFORMATS 1 235 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 236 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 237 struct audio_encoding_set *sc_encodings; 238 struct audio_encoding_set *sc_spdif_encodings; 239 }; 240 241 /* Debug */ 242 #ifdef AUICH_DEBUG 243 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 244 int auich_debug = 0xfffe; 245 #define ICH_DEBUG_CODECIO 0x0001 246 #define ICH_DEBUG_DMA 0x0002 247 #define ICH_DEBUG_INTR 0x0004 248 #else 249 #define DPRINTF(x,y) /* nothing */ 250 #endif 251 252 static int auich_match(struct device *, struct cfdata *, void *); 253 static void auich_attach(struct device *, struct device *, void *); 254 static int auich_detach(struct device *, int); 255 static int auich_activate(struct device *, enum devact); 256 static int auich_intr(void *); 257 258 CFATTACH_DECL(auich, sizeof(struct auich_softc), 259 auich_match, auich_attach, auich_detach, auich_activate); 260 261 static int auich_open(void *, int); 262 static void auich_close(void *); 263 static int auich_query_encoding(void *, struct audio_encoding *); 264 static int auich_set_params(void *, int, int, audio_params_t *, 265 audio_params_t *, stream_filter_list_t *, 266 stream_filter_list_t *); 267 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 268 static void auich_halt_pipe(struct auich_softc *, int); 269 static int auich_halt_output(void *); 270 static int auich_halt_input(void *); 271 static int auich_getdev(void *, struct audio_device *); 272 static int auich_set_port(void *, mixer_ctrl_t *); 273 static int auich_get_port(void *, mixer_ctrl_t *); 274 static int auich_query_devinfo(void *, mixer_devinfo_t *); 275 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 276 static void auich_freem(void *, void *, struct malloc_type *); 277 static size_t auich_round_buffersize(void *, int, size_t); 278 static paddr_t auich_mappage(void *, void *, off_t, int); 279 static int auich_get_props(void *); 280 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 281 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 282 static int auich_trigger_output(void *, void *, void *, int, 283 void (*)(void *), void *, const audio_params_t *); 284 static int auich_trigger_input(void *, void *, void *, int, 285 void (*)(void *), void *, const audio_params_t *); 286 static int auich_powerstate(void *, int); 287 288 static int auich_alloc_cdata(struct auich_softc *); 289 290 static int auich_allocmem(struct auich_softc *, size_t, size_t, 291 struct auich_dma *); 292 static int auich_freemem(struct auich_softc *, struct auich_dma *); 293 294 static void auich_powerhook(int, void *); 295 static int auich_set_rate(struct auich_softc *, int, u_long); 296 static int auich_sysctl_verify(SYSCTLFN_ARGS); 297 static void auich_finish_attach(struct device *); 298 static void auich_calibrate(struct auich_softc *); 299 static void auich_clear_cas(struct auich_softc *); 300 301 static int auich_attach_codec(void *, struct ac97_codec_if *); 302 static int auich_read_codec(void *, uint8_t, uint16_t *); 303 static int auich_write_codec(void *, uint8_t, uint16_t); 304 static int auich_reset_codec(void *); 305 static enum ac97_host_flags auich_flags_codec(void *); 306 static void auich_spdif_event(void *, bool); 307 308 static const struct audio_hw_if auich_hw_if = { 309 auich_open, 310 auich_close, 311 NULL, /* drain */ 312 auich_query_encoding, 313 auich_set_params, 314 auich_round_blocksize, 315 NULL, /* commit_setting */ 316 NULL, /* init_output */ 317 NULL, /* init_input */ 318 NULL, /* start_output */ 319 NULL, /* start_input */ 320 auich_halt_output, 321 auich_halt_input, 322 NULL, /* speaker_ctl */ 323 auich_getdev, 324 NULL, /* getfd */ 325 auich_set_port, 326 auich_get_port, 327 auich_query_devinfo, 328 auich_allocm, 329 auich_freem, 330 auich_round_buffersize, 331 auich_mappage, 332 auich_get_props, 333 auich_trigger_output, 334 auich_trigger_input, 335 NULL, /* dev_ioctl */ 336 auich_powerstate, 337 }; 338 339 #define AUICH_FORMATS_1CH 0 340 #define AUICH_FORMATS_4CH 1 341 #define AUICH_FORMATS_6CH 2 342 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 343 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 344 2, AUFMT_STEREO, 0, {8000, 48000}}, 345 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 346 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 347 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 348 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 349 }; 350 351 #define AUICH_SPDIF_NFORMATS 1 352 static const struct audio_format auich_spdif_formats[AUICH_SPDIF_NFORMATS] = { 353 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 354 2, AUFMT_STEREO, 1, {48000}}, 355 }; 356 357 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 358 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 359 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 360 }; 361 362 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 363 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 364 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 365 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 366 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 367 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 368 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 369 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 370 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 371 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 372 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 373 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 374 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 375 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 376 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 377 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 378 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 379 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 380 #define PCIID_NFORCE430 PCI_ID_CODE0(NVIDIA, NFORCE430_AC) 381 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 382 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 383 384 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 385 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 386 #define PCIID_ICH6MODEM PCI_ID_CODE0(INTEL, 82801FB_ACM) 387 388 struct auich_devtype { 389 pcireg_t id; 390 const char *name; 391 const char *shortname; /* must be less than 11 characters */ 392 }; 393 394 static const struct auich_devtype auich_audio_devices[] = { 395 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 396 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 397 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 398 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 399 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 400 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 401 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 402 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 403 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 404 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 405 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 406 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 407 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 408 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 409 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 410 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 411 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 412 { PCIID_NFORCE430, "nForce430 (MCP51) AC-97 Audio", "nForce430" }, 413 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 414 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 415 { 0, NULL, NULL }, 416 }; 417 418 static const struct auich_devtype auich_modem_devices[] = { 419 #ifdef AUICH_ATTACH_MODEM 420 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 421 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 422 { PCIID_ICH6MODEM, "i82801FB (ICH6) AC-97 Modem", "ICH6MODEM" }, 423 #endif 424 { 0, NULL, NULL }, 425 }; 426 427 static const struct auich_devtype * 428 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 429 { 430 const struct auich_devtype *d; 431 432 for (d = auich_devices; d->name != NULL; d++) { 433 if (pa->pa_id == d->id) 434 return d; 435 } 436 437 return NULL; 438 } 439 440 static int 441 auich_match(struct device *parent, struct cfdata *match, 442 void *aux) 443 { 444 struct pci_attach_args *pa; 445 446 pa = aux; 447 if (auich_lookup(pa, auich_audio_devices) != NULL) 448 return 1; 449 if (auich_lookup(pa, auich_modem_devices) != NULL) 450 return 1; 451 452 return 0; 453 } 454 455 static void 456 auich_attach(struct device *parent, struct device *self, void *aux) 457 { 458 struct auich_softc *sc; 459 struct pci_attach_args *pa; 460 pcireg_t v, subdev; 461 const char *intrstr; 462 const struct auich_devtype *d; 463 const struct sysctlnode *node, *node_ac97clock; 464 int err, node_mib, i; 465 466 sc = (struct auich_softc *)self; 467 pa = aux; 468 469 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 470 sc->sc_modem_offset = 0x10; 471 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 472 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 473 sc->sc_modem_offset = 0; 474 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 475 } else 476 panic("auich_attach: impossible"); 477 478 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 479 aprint_naive(": Audio controller\n"); 480 else 481 aprint_naive(": Modem controller\n"); 482 483 sc->sc_pc = pa->pa_pc; 484 sc->sc_pt = pa->pa_tag; 485 486 aprint_normal(": %s\n", d->name); 487 488 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 489 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 490 || d->id == PCIID_ICH4MODEM) { 491 /* 492 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 493 */ 494 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 495 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 496 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 497 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 498 v | ICH_CFG_IOSE); 499 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 500 0, &sc->iot, &sc->mix_ioh, NULL, 501 &sc->mix_size)) { 502 aprint_error("%s: can't map codec i/o space\n", 503 sc->sc_dev.dv_xname); 504 return; 505 } 506 } 507 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 508 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 509 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 510 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 511 v | ICH_CFG_IOSE); 512 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 513 0, &sc->iot, &sc->aud_ioh, NULL, 514 &sc->aud_size)) { 515 aprint_error("%s: can't map device i/o space\n", 516 sc->sc_dev.dv_xname); 517 return; 518 } 519 } 520 } else { 521 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 522 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 523 aprint_error("%s: can't map codec i/o space\n", 524 sc->sc_dev.dv_xname); 525 return; 526 } 527 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 528 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 529 aprint_error("%s: can't map device i/o space\n", 530 sc->sc_dev.dv_xname); 531 return; 532 } 533 } 534 sc->dmat = pa->pa_dmat; 535 536 /* enable bus mastering */ 537 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 538 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 539 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 540 541 /* Map and establish the interrupt. */ 542 if (pci_intr_map(pa, &sc->intrh)) { 543 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 544 return; 545 } 546 intrstr = pci_intr_string(pa->pa_pc, sc->intrh); 547 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO, 548 auich_intr, sc); 549 if (sc->sc_ih == NULL) { 550 aprint_error("%s: can't establish interrupt", 551 sc->sc_dev.dv_xname); 552 if (intrstr != NULL) 553 aprint_normal(" at %s", intrstr); 554 aprint_normal("\n"); 555 return; 556 } 557 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 558 559 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 560 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 561 "0x%02x", PCI_REVISION(pa->pa_class)); 562 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 563 564 /* SiS 7012 needs special handling */ 565 if (d->id == PCIID_SIS7012) { 566 sc->sc_sts_reg = ICH_PICB; 567 sc->sc_sample_shift = 0; 568 /* Un-mute output. From Linux. */ 569 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 570 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 571 ICH_SIS_CTL_UNMUTE); 572 } else { 573 sc->sc_sts_reg = ICH_STS; 574 sc->sc_sample_shift = 1; 575 } 576 577 /* Workaround for a 440MX B-stepping erratum */ 578 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 579 if (d->id == PCIID_440MX) { 580 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 581 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 582 } 583 584 /* Set up DMA lists. */ 585 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 586 auich_alloc_cdata(sc); 587 588 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 589 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 590 591 /* Modem codecs are always the secondary codec on ICH */ 592 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 593 594 sc->host_if.arg = sc; 595 sc->host_if.attach = auich_attach_codec; 596 sc->host_if.read = auich_read_codec; 597 sc->host_if.write = auich_write_codec; 598 sc->host_if.reset = auich_reset_codec; 599 sc->host_if.flags = auich_flags_codec; 600 sc->host_if.spdif_event = auich_spdif_event; 601 602 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 603 switch (subdev) { 604 case 0x202f161f: /* Gateway 7326GZ */ 605 case 0x203a161f: /* Gateway 4028GZ */ 606 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 607 case 0x8144104d: /* Sony VAIO PCG-TR* */ 608 case 0x8197104d: /* Sony S1XP */ 609 case 0x81c0104d: /* Sony VAIO type T */ 610 case 0x81c5104d: /* Sony VAIO VGN-B1XP */ 611 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP; 612 break; 613 default: 614 sc->sc_codecflags = 0; 615 break; 616 } 617 618 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 619 return; 620 sc->codec_if->vtbl->unlock(sc->codec_if); 621 622 /* setup audio_format */ 623 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 624 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 625 if (!AC97_IS_4CH(sc->codec_if)) 626 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 627 if (!AC97_IS_6CH(sc->codec_if)) 628 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 629 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 630 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 631 sc->sc_audio_formats[i].frequency_type = 1; 632 sc->sc_audio_formats[i].frequency[0] = 48000; 633 } 634 } 635 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 636 &sc->sc_encodings)) 637 return; 638 if (0 != auconv_create_encodings(auich_spdif_formats, AUICH_SPDIF_NFORMATS, 639 &sc->sc_spdif_encodings)) 640 return; 641 } else { 642 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 643 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 644 &sc->sc_encodings)) 645 return; 646 } 647 648 649 /* Watch for power change */ 650 sc->sc_suspend = PWR_RESUME; 651 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 652 auich_powerhook, sc); 653 654 config_interrupts(self, auich_finish_attach); 655 656 /* sysctl setup */ 657 if (AC97_IS_FIXED_RATE(sc->codec_if) && 658 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 659 return; 660 661 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 662 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 663 CTL_HW, CTL_EOL); 664 if (err != 0) 665 goto sysctl_err; 666 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 667 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 668 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 669 if (err != 0) 670 goto sysctl_err; 671 node_mib = node->sysctl_num; 672 673 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 674 /* passing the sc address instead of &sc->sc_ac97_clock */ 675 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 676 CTLFLAG_READWRITE, 677 CTLTYPE_INT, "ac97rate", 678 SYSCTL_DESCR("AC'97 codec link rate"), 679 auich_sysctl_verify, 0, sc, 0, 680 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 681 if (err != 0) 682 goto sysctl_err; 683 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 684 } 685 686 return; 687 688 sysctl_err: 689 printf("%s: failed to add sysctl nodes. (%d)\n", 690 sc->sc_dev.dv_xname, err); 691 return; /* failure of sysctl is not fatal. */ 692 } 693 694 static int 695 auich_activate(struct device *self, enum devact act) 696 { 697 struct auich_softc *sc; 698 int ret; 699 700 sc = (struct auich_softc *)self; 701 ret = 0; 702 switch (act) { 703 case DVACT_ACTIVATE: 704 return EOPNOTSUPP; 705 case DVACT_DEACTIVATE: 706 if (sc->sc_audiodev != NULL) 707 ret = config_deactivate(sc->sc_audiodev); 708 return ret; 709 } 710 return EOPNOTSUPP; 711 } 712 713 static int 714 auich_detach(struct device *self, int flags) 715 { 716 struct auich_softc *sc; 717 718 sc = (struct auich_softc *)self; 719 720 /* audio */ 721 if (sc->sc_audiodev != NULL) 722 config_detach(sc->sc_audiodev, flags); 723 724 /* sysctl */ 725 sysctl_teardown(&sc->sc_log); 726 727 /* audio_encoding_set */ 728 auconv_delete_encodings(sc->sc_encodings); 729 auconv_delete_encodings(sc->sc_spdif_encodings); 730 731 /* ac97 */ 732 if (sc->codec_if != NULL) 733 sc->codec_if->vtbl->detach(sc->codec_if); 734 735 /* PCI */ 736 if (sc->sc_ih != NULL) 737 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 738 if (sc->mix_size != 0) 739 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 740 if (sc->aud_size != 0) 741 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 742 return 0; 743 } 744 745 static int 746 auich_sysctl_verify(SYSCTLFN_ARGS) 747 { 748 int error, tmp; 749 struct sysctlnode node; 750 struct auich_softc *sc; 751 752 node = *rnode; 753 sc = rnode->sysctl_data; 754 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 755 tmp = sc->sc_ac97_clock; 756 node.sysctl_data = &tmp; 757 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 758 if (error || newp == NULL) 759 return error; 760 761 if (tmp < 48000 || tmp > 96000) 762 return EINVAL; 763 sc->sc_ac97_clock = tmp; 764 } 765 766 return 0; 767 } 768 769 static void 770 auich_finish_attach(struct device *self) 771 { 772 struct auich_softc *sc; 773 774 sc = (void *)self; 775 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 776 auich_calibrate(sc); 777 778 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 779 780 #if notyet 781 auich_powerhook(PWR_SUSPEND, sc); 782 #endif 783 784 return; 785 } 786 787 #define ICH_CODECIO_INTERVAL 10 788 static int 789 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 790 { 791 struct auich_softc *sc; 792 int i; 793 uint32_t status; 794 795 sc = v; 796 /* wait for an access semaphore */ 797 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 798 bus_space_read_1(sc->iot, sc->aud_ioh, 799 ICH_CAS + sc->sc_modem_offset) & 1; 800 DELAY(ICH_CODECIO_INTERVAL)); 801 802 if (i > 0) { 803 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 804 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 805 DPRINTF(ICH_DEBUG_CODECIO, 806 ("auich_read_codec(%x, %x)\n", reg, *val)); 807 status = bus_space_read_4(sc->iot, sc->aud_ioh, 808 ICH_GSTS + sc->sc_modem_offset); 809 if (status & ICH_RCS) { 810 bus_space_write_4(sc->iot, sc->aud_ioh, 811 ICH_GSTS + sc->sc_modem_offset, 812 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 813 *val = 0xffff; 814 DPRINTF(ICH_DEBUG_CODECIO, 815 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 816 if (reg == AC97_REG_GPIO_STATUS) 817 auich_clear_cas(sc); 818 return -1; 819 } 820 if (reg == AC97_REG_GPIO_STATUS) 821 auich_clear_cas(sc); 822 return 0; 823 } else { 824 aprint_normal("%s: read_codec timeout\n", sc->sc_dev.dv_xname); 825 if (reg == AC97_REG_GPIO_STATUS) 826 auich_clear_cas(sc); 827 return -1; 828 } 829 } 830 831 static int 832 auich_write_codec(void *v, uint8_t reg, uint16_t val) 833 { 834 struct auich_softc *sc; 835 int i; 836 837 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 838 sc = v; 839 /* wait for an access semaphore */ 840 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 841 bus_space_read_1(sc->iot, sc->aud_ioh, 842 ICH_CAS + sc->sc_modem_offset) & 1; 843 DELAY(ICH_CODECIO_INTERVAL)); 844 845 if (i > 0) { 846 bus_space_write_2(sc->iot, sc->mix_ioh, 847 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 848 return 0; 849 } else { 850 aprint_normal("%s: write_codec timeout\n", sc->sc_dev.dv_xname); 851 return -1; 852 } 853 } 854 855 static int 856 auich_attach_codec(void *v, struct ac97_codec_if *cif) 857 { 858 struct auich_softc *sc; 859 860 sc = v; 861 sc->codec_if = cif; 862 863 return 0; 864 } 865 866 static int 867 auich_reset_codec(void *v) 868 { 869 struct auich_softc *sc; 870 int i; 871 uint32_t control, status; 872 873 sc = v; 874 control = bus_space_read_4(sc->iot, sc->aud_ioh, 875 ICH_GCTRL + sc->sc_modem_offset); 876 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 877 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 878 } else { 879 control &= ~ICH_ACLSO; 880 control |= ICH_GIE; 881 } 882 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 883 bus_space_write_4(sc->iot, sc->aud_ioh, 884 ICH_GCTRL + sc->sc_modem_offset, control); 885 886 for (i = 500000; i >= 0; i--) { 887 status = bus_space_read_4(sc->iot, sc->aud_ioh, 888 ICH_GSTS + sc->sc_modem_offset); 889 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 890 break; 891 DELAY(1); 892 } 893 if (i <= 0) { 894 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 895 return ETIMEDOUT; 896 } 897 #ifdef AUICH_DEBUG 898 if (status & ICH_SCR) 899 printf("%s: The 2nd codec is ready.\n", 900 sc->sc_dev.dv_xname); 901 if (status & ICH_S2CR) 902 printf("%s: The 3rd codec is ready.\n", 903 sc->sc_dev.dv_xname); 904 #endif 905 return 0; 906 } 907 908 static enum ac97_host_flags 909 auich_flags_codec(void *v) 910 { 911 struct auich_softc *sc = v; 912 return sc->sc_codecflags; 913 } 914 915 static void 916 auich_spdif_event(void *addr, bool flag) 917 { 918 struct auich_softc *sc; 919 920 sc = addr; 921 sc->sc_spdif = flag; 922 } 923 924 static int 925 auich_open(void *addr, int flags) 926 { 927 struct auich_softc *sc; 928 929 sc = (struct auich_softc *)addr; 930 sc->codec_if->vtbl->lock(sc->codec_if); 931 return 0; 932 } 933 934 static void 935 auich_close(void *addr) 936 { 937 struct auich_softc *sc; 938 939 sc = (struct auich_softc *)addr; 940 sc->codec_if->vtbl->unlock(sc->codec_if); 941 } 942 943 static int 944 auich_query_encoding(void *v, struct audio_encoding *aep) 945 { 946 struct auich_softc *sc; 947 948 sc = (struct auich_softc *)v; 949 return auconv_query_encoding( 950 sc->sc_spdif ? sc->sc_spdif_encodings : sc->sc_encodings, aep); 951 } 952 953 static int 954 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 955 { 956 int ret; 957 u_int ratetmp; 958 959 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 960 ratetmp = srate; 961 if (mode == AUMODE_RECORD) 962 return sc->codec_if->vtbl->set_rate(sc->codec_if, 963 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 964 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 965 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 966 if (ret) 967 return ret; 968 ratetmp = srate; 969 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 970 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 971 if (ret) 972 return ret; 973 ratetmp = srate; 974 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 975 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 976 return ret; 977 } 978 979 static int 980 auich_set_params(void *v, int setmode, int usemode, 981 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 982 stream_filter_list_t *rfil) 983 { 984 struct auich_softc *sc; 985 audio_params_t *p; 986 stream_filter_list_t *fil; 987 int mode, index; 988 uint32_t control; 989 990 sc = v; 991 for (mode = AUMODE_RECORD; mode != -1; 992 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 993 if ((setmode & mode) == 0) 994 continue; 995 996 p = mode == AUMODE_PLAY ? play : rec; 997 fil = mode == AUMODE_PLAY ? pfil : rfil; 998 if (p == NULL) 999 continue; 1000 1001 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1002 if (p->sample_rate < 8000 || 1003 p->sample_rate > 48000) 1004 return EINVAL; 1005 1006 if (sc->sc_spdif) 1007 index = auconv_set_converter(sc->sc_audio_formats, 1008 AUICH_AUDIO_NFORMATS, mode, p, TRUE, fil); 1009 else 1010 index = auconv_set_converter(auich_spdif_formats, 1011 AUICH_SPDIF_NFORMATS, mode, p, TRUE, fil); 1012 } else { 1013 if (p->sample_rate != 8000 && p->sample_rate != 16000) 1014 return EINVAL; 1015 index = auconv_set_converter(sc->sc_modem_formats, 1016 AUICH_MODEM_NFORMATS, mode, p, TRUE, fil); 1017 } 1018 if (index < 0) 1019 return EINVAL; 1020 if (fil->req_size > 0) 1021 p = &fil->filters[0].param; 1022 /* p represents HW encoding */ 1023 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1024 if (sc->sc_audio_formats[index].frequency_type != 1 1025 && auich_set_rate(sc, mode, p->sample_rate)) 1026 return EINVAL; 1027 } else { 1028 if (sc->sc_modem_formats[index].frequency_type != 1 1029 && auich_set_rate(sc, mode, p->sample_rate)) 1030 return EINVAL; 1031 auich_write_codec(sc, AC97_REG_LINE1_RATE, 1032 p->sample_rate); 1033 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 1034 } 1035 if (mode == AUMODE_PLAY && 1036 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1037 control = bus_space_read_4(sc->iot, sc->aud_ioh, 1038 ICH_GCTRL + sc->sc_modem_offset); 1039 control &= ~ICH_PCM246_MASK; 1040 if (p->channels == 4) { 1041 control |= ICH_PCM4; 1042 } else if (p->channels == 6) { 1043 control |= ICH_PCM6; 1044 } 1045 bus_space_write_4(sc->iot, sc->aud_ioh, 1046 ICH_GCTRL + sc->sc_modem_offset, control); 1047 } 1048 } 1049 1050 return 0; 1051 } 1052 1053 static int 1054 auich_round_blocksize(void *v, int blk, int mode, 1055 const audio_params_t *param) 1056 { 1057 1058 return blk & ~0x3f; /* keep good alignment */ 1059 } 1060 1061 static void 1062 auich_halt_pipe(struct auich_softc *sc, int pipe) 1063 { 1064 int i; 1065 uint32_t status; 1066 1067 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 1068 for (i = 0; i < 100; i++) { 1069 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 1070 if (status & ICH_DCH) 1071 break; 1072 DELAY(1); 1073 } 1074 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 1075 1076 #if AUICH_DEBUG 1077 if (i > 0) 1078 printf("auich_halt_pipe: halt took %d cycles\n", i); 1079 #endif 1080 } 1081 1082 static int 1083 auich_halt_output(void *v) 1084 { 1085 struct auich_softc *sc; 1086 1087 sc = v; 1088 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 1089 1090 auich_halt_pipe(sc, ICH_PCMO); 1091 sc->pcmo.intr = NULL; 1092 1093 return 0; 1094 } 1095 1096 static int 1097 auich_halt_input(void *v) 1098 { 1099 struct auich_softc *sc; 1100 1101 sc = v; 1102 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", sc->sc_dev.dv_xname)); 1103 1104 auich_halt_pipe(sc, ICH_PCMI); 1105 sc->pcmi.intr = NULL; 1106 1107 return 0; 1108 } 1109 1110 static int 1111 auich_getdev(void *v, struct audio_device *adp) 1112 { 1113 struct auich_softc *sc; 1114 1115 sc = v; 1116 *adp = sc->sc_audev; 1117 return 0; 1118 } 1119 1120 static int 1121 auich_set_port(void *v, mixer_ctrl_t *cp) 1122 { 1123 struct auich_softc *sc; 1124 1125 sc = v; 1126 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1127 } 1128 1129 static int 1130 auich_get_port(void *v, mixer_ctrl_t *cp) 1131 { 1132 struct auich_softc *sc; 1133 1134 sc = v; 1135 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1136 } 1137 1138 static int 1139 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1140 { 1141 struct auich_softc *sc; 1142 1143 sc = v; 1144 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1145 } 1146 1147 static void * 1148 auich_allocm(void *v, int direction, size_t size, 1149 struct malloc_type *pool, int flags) 1150 { 1151 struct auich_softc *sc; 1152 struct auich_dma *p; 1153 int error; 1154 1155 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1156 return NULL; 1157 1158 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1159 if (p == NULL) 1160 return NULL; 1161 1162 sc = v; 1163 error = auich_allocmem(sc, size, 0, p); 1164 if (error) { 1165 free(p, pool); 1166 return NULL; 1167 } 1168 1169 p->next = sc->sc_dmas; 1170 sc->sc_dmas = p; 1171 1172 return KERNADDR(p); 1173 } 1174 1175 static void 1176 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1177 { 1178 struct auich_softc *sc; 1179 struct auich_dma *p, **pp; 1180 1181 sc = v; 1182 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1183 if (KERNADDR(p) == ptr) { 1184 auich_freemem(sc, p); 1185 *pp = p->next; 1186 free(p, pool); 1187 return; 1188 } 1189 } 1190 } 1191 1192 static size_t 1193 auich_round_buffersize(void *v, int direction, size_t size) 1194 { 1195 1196 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1197 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1198 1199 return size; 1200 } 1201 1202 static paddr_t 1203 auich_mappage(void *v, void *mem, off_t off, int prot) 1204 { 1205 struct auich_softc *sc; 1206 struct auich_dma *p; 1207 1208 if (off < 0) 1209 return -1; 1210 sc = v; 1211 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1212 continue; 1213 if (!p) 1214 return -1; 1215 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1216 off, prot, BUS_DMA_WAITOK); 1217 } 1218 1219 static int 1220 auich_get_props(void *v) 1221 { 1222 struct auich_softc *sc; 1223 int props; 1224 1225 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1226 sc = v; 1227 /* 1228 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1229 * rate because of aurateconv. Applications can't know what rate the 1230 * device can process in the case of mmap(). 1231 */ 1232 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1233 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1234 props |= AUDIO_PROP_MMAP; 1235 return props; 1236 } 1237 1238 static int 1239 auich_intr(void *v) 1240 { 1241 struct auich_softc *sc; 1242 int ret, gsts; 1243 #ifdef DIAGNOSTIC 1244 int csts; 1245 #endif 1246 1247 sc = v; 1248 ret = 0; 1249 #ifdef DIAGNOSTIC 1250 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1251 if (csts & PCI_STATUS_MASTER_ABORT) { 1252 printf("auich_intr: PCI master abort\n"); 1253 } 1254 #endif 1255 1256 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1257 ICH_GSTS + sc->sc_modem_offset); 1258 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1259 1260 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1261 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1262 int sts; 1263 1264 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1265 ICH_PCMO + sc->sc_sts_reg); 1266 DPRINTF(ICH_DEBUG_INTR, 1267 ("auich_intr: osts=0x%x\n", sts)); 1268 1269 if (sts & ICH_FIFOE) 1270 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1271 1272 if (sts & ICH_BCIS) 1273 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1274 1275 /* int ack */ 1276 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1277 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1278 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1279 bus_space_write_4(sc->iot, sc->aud_ioh, 1280 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1281 else 1282 bus_space_write_4(sc->iot, sc->aud_ioh, 1283 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1284 ret++; 1285 } 1286 1287 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1288 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1289 int sts; 1290 1291 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1292 ICH_PCMI + sc->sc_sts_reg); 1293 DPRINTF(ICH_DEBUG_INTR, 1294 ("auich_intr: ists=0x%x\n", sts)); 1295 1296 if (sts & ICH_FIFOE) 1297 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1298 1299 if (sts & ICH_BCIS) 1300 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1301 1302 /* int ack */ 1303 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1304 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1305 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1306 bus_space_write_4(sc->iot, sc->aud_ioh, 1307 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1308 else 1309 bus_space_write_4(sc->iot, sc->aud_ioh, 1310 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1311 ret++; 1312 } 1313 1314 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1315 int sts; 1316 1317 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1318 ICH_MICI + sc->sc_sts_reg); 1319 DPRINTF(ICH_DEBUG_INTR, 1320 ("auich_intr: ists=0x%x\n", sts)); 1321 1322 if (sts & ICH_FIFOE) 1323 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1324 1325 if (sts & ICH_BCIS) 1326 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1327 1328 /* int ack */ 1329 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1330 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1331 bus_space_write_4(sc->iot, sc->aud_ioh, 1332 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1333 ret++; 1334 } 1335 1336 #ifdef AUICH_MODEM_DEBUG 1337 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1338 printf("%s: gsts=0x%x\n", sc->sc_dev.dv_xname, gsts); 1339 /* int ack */ 1340 bus_space_write_4(sc->iot, sc->aud_ioh, 1341 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1342 ret++; 1343 } 1344 #endif 1345 1346 return ret; 1347 } 1348 1349 static void 1350 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1351 { 1352 int blksize, qptr; 1353 struct auich_dmalist *q; 1354 1355 blksize = ring->blksize; 1356 1357 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1358 q = &ring->dmalist[qptr]; 1359 q->base = ring->p; 1360 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1361 1362 ring->p += blksize; 1363 if (ring->p >= ring->end) 1364 ring->p = ring->start; 1365 } 1366 ring->qptr = 0; 1367 1368 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1369 (qptr - 1) & ICH_LVI_MASK); 1370 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1371 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1372 } 1373 1374 static void 1375 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1376 { 1377 int blksize, qptr, nqptr; 1378 struct auich_dmalist *q; 1379 1380 blksize = ring->blksize; 1381 qptr = ring->qptr; 1382 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1383 1384 while (qptr != nqptr) { 1385 q = &ring->dmalist[qptr]; 1386 q->base = ring->p; 1387 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1388 1389 DPRINTF(ICH_DEBUG_INTR, 1390 ("auich_intr: %p, %p = %x @ 0x%x\n", 1391 &ring->dmalist[qptr], q, q->len, q->base)); 1392 1393 ring->p += blksize; 1394 if (ring->p >= ring->end) 1395 ring->p = ring->start; 1396 1397 qptr = (qptr + 1) & ICH_LVI_MASK; 1398 if (ring->intr) 1399 ring->intr(ring->arg); 1400 } 1401 ring->qptr = qptr; 1402 1403 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1404 (qptr - 1) & ICH_LVI_MASK); 1405 } 1406 1407 static int 1408 auich_trigger_output(void *v, void *start, void *end, int blksize, 1409 void (*intr)(void *), void *arg, const audio_params_t *param) 1410 { 1411 struct auich_softc *sc; 1412 struct auich_dma *p; 1413 size_t size; 1414 1415 DPRINTF(ICH_DEBUG_DMA, 1416 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1417 start, end, blksize, intr, arg, param)); 1418 sc = v; 1419 1420 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1421 continue; 1422 if (!p) { 1423 printf("auich_trigger_output: bad addr %p\n", start); 1424 return EINVAL; 1425 } 1426 1427 size = (size_t)((char *)end - (char *)start); 1428 1429 sc->pcmo.intr = intr; 1430 sc->pcmo.arg = arg; 1431 sc->pcmo.start = DMAADDR(p); 1432 sc->pcmo.p = sc->pcmo.start; 1433 sc->pcmo.end = sc->pcmo.start + size; 1434 sc->pcmo.blksize = blksize; 1435 1436 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1437 sc->sc_cddma + ICH_PCMO_OFF(0)); 1438 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1439 1440 return 0; 1441 } 1442 1443 static int 1444 auich_trigger_input(void *v, void *start, void *end, int blksize, 1445 void (*intr)(void *), void *arg, const audio_params_t *param) 1446 { 1447 struct auich_softc *sc; 1448 struct auich_dma *p; 1449 size_t size; 1450 1451 DPRINTF(ICH_DEBUG_DMA, 1452 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1453 start, end, blksize, intr, arg, param)); 1454 sc = v; 1455 1456 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1457 continue; 1458 if (!p) { 1459 printf("auich_trigger_input: bad addr %p\n", start); 1460 return EINVAL; 1461 } 1462 1463 size = (size_t)((char *)end - (char *)start); 1464 1465 sc->pcmi.intr = intr; 1466 sc->pcmi.arg = arg; 1467 sc->pcmi.start = DMAADDR(p); 1468 sc->pcmi.p = sc->pcmi.start; 1469 sc->pcmi.end = sc->pcmi.start + size; 1470 sc->pcmi.blksize = blksize; 1471 1472 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1473 sc->sc_cddma + ICH_PCMI_OFF(0)); 1474 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1475 1476 return 0; 1477 } 1478 1479 static int 1480 auich_powerstate(void *v, int state) 1481 { 1482 #if notyet 1483 struct auich_softc *sc; 1484 int rv; 1485 1486 sc = (struct auich_softc *)v; 1487 rv = 0; 1488 1489 switch (state) { 1490 case AUDIOPOWER_OFF: 1491 auich_powerhook(PWR_SUSPEND, sc); 1492 break; 1493 case AUDIOPOWER_ON: 1494 auich_powerhook(PWR_RESUME, sc); 1495 break; 1496 default: 1497 aprint_error("%s: unknown power state %d\n", 1498 sc->sc_dev.dv_xname, state); 1499 rv = 1; 1500 break; 1501 } 1502 1503 return rv; 1504 #else 1505 return 0; 1506 #endif 1507 } 1508 1509 static int 1510 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1511 struct auich_dma *p) 1512 { 1513 int error; 1514 1515 p->size = size; 1516 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1517 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1518 &p->nsegs, BUS_DMA_NOWAIT); 1519 if (error) 1520 return error; 1521 1522 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1523 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1524 if (error) 1525 goto free; 1526 1527 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1528 0, BUS_DMA_NOWAIT, &p->map); 1529 if (error) 1530 goto unmap; 1531 1532 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1533 BUS_DMA_NOWAIT); 1534 if (error) 1535 goto destroy; 1536 return 0; 1537 1538 destroy: 1539 bus_dmamap_destroy(sc->dmat, p->map); 1540 unmap: 1541 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1542 free: 1543 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1544 return error; 1545 } 1546 1547 static int 1548 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1549 { 1550 1551 bus_dmamap_unload(sc->dmat, p->map); 1552 bus_dmamap_destroy(sc->dmat, p->map); 1553 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1554 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1555 return 0; 1556 } 1557 1558 static int 1559 auich_alloc_cdata(struct auich_softc *sc) 1560 { 1561 bus_dma_segment_t seg; 1562 int error, rseg; 1563 1564 /* 1565 * Allocate the control data structure, and create and load the 1566 * DMA map for it. 1567 */ 1568 if ((error = bus_dmamem_alloc(sc->dmat, 1569 sizeof(struct auich_cdata), 1570 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1571 printf("%s: unable to allocate control data, error = %d\n", 1572 sc->sc_dev.dv_xname, error); 1573 goto fail_0; 1574 } 1575 1576 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1577 sizeof(struct auich_cdata), 1578 (void **) &sc->sc_cdata, 1579 sc->sc_dmamap_flags)) != 0) { 1580 printf("%s: unable to map control data, error = %d\n", 1581 sc->sc_dev.dv_xname, error); 1582 goto fail_1; 1583 } 1584 1585 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1586 sizeof(struct auich_cdata), 0, 0, 1587 &sc->sc_cddmamap)) != 0) { 1588 printf("%s: unable to create control data DMA map, " 1589 "error = %d\n", sc->sc_dev.dv_xname, error); 1590 goto fail_2; 1591 } 1592 1593 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1594 sc->sc_cdata, sizeof(struct auich_cdata), 1595 NULL, 0)) != 0) { 1596 printf("%s: unable tp load control data DMA map, " 1597 "error = %d\n", sc->sc_dev.dv_xname, error); 1598 goto fail_3; 1599 } 1600 1601 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1602 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1603 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1604 1605 return 0; 1606 1607 fail_3: 1608 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1609 fail_2: 1610 bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata, 1611 sizeof(struct auich_cdata)); 1612 fail_1: 1613 bus_dmamem_free(sc->dmat, &seg, rseg); 1614 fail_0: 1615 return error; 1616 } 1617 1618 static void 1619 auich_powerhook(int why, void *addr) 1620 { 1621 struct auich_softc *sc; 1622 1623 sc = (struct auich_softc *)addr; 1624 switch (why) { 1625 case PWR_SUSPEND: 1626 case PWR_STANDBY: 1627 /* Power down */ 1628 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1629 1630 /* if we're already asleep, don't try to sleep again */ 1631 if (sc->sc_suspend == PWR_SUSPEND || 1632 sc->sc_suspend == PWR_STANDBY) 1633 break; 1634 sc->sc_suspend = why; 1635 1636 DELAY(1000); 1637 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1638 1639 if (sc->sc_ih != NULL) 1640 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1641 1642 break; 1643 1644 case PWR_RESUME: 1645 /* Wake up */ 1646 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1647 if (sc->sc_suspend == PWR_RESUME) { 1648 printf("%s: resume without suspend.\n", 1649 sc->sc_dev.dv_xname); 1650 sc->sc_suspend = why; 1651 return; 1652 } 1653 1654 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 1655 auich_intr, sc); 1656 if (sc->sc_ih == NULL) { 1657 aprint_error("%s: can't establish interrupt", 1658 sc->sc_dev.dv_xname); 1659 /* XXX jmcneill what should we do here? */ 1660 return; 1661 } 1662 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1663 sc->sc_suspend = why; 1664 auich_reset_codec(sc); 1665 DELAY(1000); 1666 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1667 break; 1668 1669 case PWR_SOFTSUSPEND: 1670 case PWR_SOFTSTANDBY: 1671 case PWR_SOFTRESUME: 1672 break; 1673 } 1674 } 1675 1676 /* 1677 * Calibrate card (some boards are overclocked and need scaling) 1678 */ 1679 static void 1680 auich_calibrate(struct auich_softc *sc) 1681 { 1682 struct timeval t1, t2; 1683 uint8_t ociv, nciv; 1684 uint64_t wait_us; 1685 uint32_t actual_48k_rate, bytes, ac97rate; 1686 void *temp_buffer; 1687 struct auich_dma *p; 1688 u_int rate; 1689 1690 /* 1691 * Grab audio from input for fixed interval and compare how 1692 * much we actually get with what we expect. Interval needs 1693 * to be sufficiently short that no interrupts are 1694 * generated. 1695 */ 1696 1697 /* Force the codec to a known state first. */ 1698 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1699 rate = sc->sc_ac97_clock = 48000; 1700 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1701 &rate); 1702 1703 /* Setup a buffer */ 1704 bytes = 64000; 1705 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1706 1707 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1708 continue; 1709 if (p == NULL) { 1710 printf("auich_calibrate: bad address %p\n", temp_buffer); 1711 return; 1712 } 1713 sc->pcmi.dmalist[0].base = DMAADDR(p); 1714 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1715 1716 /* 1717 * our data format is stereo, 16 bit so each sample is 4 bytes. 1718 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1719 * we're going to start recording with interrupts disabled and measure 1720 * the time taken for one block to complete. we know the block size, 1721 * we know the time in microseconds, we calculate the sample rate: 1722 * 1723 * actual_rate [bps] = bytes / (time [s] * 4) 1724 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1725 * actual_rate [Hz] = (bytes * 250000) / time [us] 1726 */ 1727 1728 /* prepare */ 1729 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1730 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1731 sc->sc_cddma + ICH_PCMI_OFF(0)); 1732 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1733 (0 - 1) & ICH_LVI_MASK); 1734 1735 /* start */ 1736 microtime(&t1); 1737 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1738 1739 /* wait */ 1740 nciv = ociv; 1741 do { 1742 microtime(&t2); 1743 if (t2.tv_sec - t1.tv_sec > 1) 1744 break; 1745 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1746 ICH_PCMI + ICH_CIV); 1747 } while (nciv == ociv); 1748 microtime(&t2); 1749 1750 /* stop */ 1751 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1752 1753 /* reset */ 1754 DELAY(100); 1755 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1756 1757 /* turn time delta into us */ 1758 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1759 1760 auich_freem(sc, temp_buffer, M_DEVBUF); 1761 1762 if (nciv == ociv) { 1763 printf("%s: ac97 link rate calibration timed out after %" 1764 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1765 return; 1766 } 1767 1768 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1769 1770 if (actual_48k_rate < 50000) 1771 ac97rate = 48000; 1772 else 1773 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1774 1775 printf("%s: measured ac97 link rate at %d Hz", 1776 sc->sc_dev.dv_xname, actual_48k_rate); 1777 if (ac97rate != actual_48k_rate) 1778 printf(", will use %d Hz", ac97rate); 1779 printf("\n"); 1780 1781 sc->sc_ac97_clock = ac97rate; 1782 } 1783 1784 static void 1785 auich_clear_cas(struct auich_softc *sc) 1786 { 1787 /* Clear the codec access semaphore */ 1788 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1789 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1790 1791 return; 1792 } 1793
Indexes created Thu Oct 23 18:09:57 GMT 2025