auich.c revision 1.120
1 /* $NetBSD: auich.c,v 1.120 2007/12/09 20:28:05 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.120 2007/12/09 20:28:05 jmcneill Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <sys/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 void *addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 pci_intr_handle_t intrh; 187 188 struct ac97_codec_if *codec_if; 189 struct ac97_host_if host_if; 190 int sc_codecnum; 191 int sc_codectype; 192 enum ac97_host_flags sc_codecflags; 193 bool sc_spdif; 194 195 /* DMA scatter-gather lists. */ 196 bus_dmamap_t sc_cddmamap; 197 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 198 199 struct auich_cdata *sc_cdata; 200 201 struct auich_ring { 202 int qptr; 203 struct auich_dmalist *dmalist; 204 205 uint32_t start, p, end; 206 int blksize; 207 208 void (*intr)(void *); 209 void *arg; 210 } pcmo, pcmi, mici; 211 212 struct auich_dma *sc_dmas; 213 214 /* SiS 7012 hack */ 215 int sc_sample_shift; 216 int sc_sts_reg; 217 /* 440MX workaround */ 218 int sc_dmamap_flags; 219 220 /* sysctl */ 221 struct sysctllog *sc_log; 222 uint32_t sc_ac97_clock; 223 int sc_ac97_clock_mib; 224 225 int sc_modem_offset; 226 227 #define AUICH_AUDIO_NFORMATS 3 228 #define AUICH_MODEM_NFORMATS 1 229 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 230 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 231 struct audio_encoding_set *sc_encodings; 232 struct audio_encoding_set *sc_spdif_encodings; 233 }; 234 235 /* Debug */ 236 #ifdef AUICH_DEBUG 237 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 238 int auich_debug = 0xfffe; 239 #define ICH_DEBUG_CODECIO 0x0001 240 #define ICH_DEBUG_DMA 0x0002 241 #define ICH_DEBUG_INTR 0x0004 242 #else 243 #define DPRINTF(x,y) /* nothing */ 244 #endif 245 246 static int auich_match(struct device *, struct cfdata *, void *); 247 static void auich_attach(struct device *, struct device *, void *); 248 static int auich_detach(struct device *, int); 249 static int auich_activate(struct device *, enum devact); 250 static int auich_intr(void *); 251 252 CFATTACH_DECL(auich, sizeof(struct auich_softc), 253 auich_match, auich_attach, auich_detach, auich_activate); 254 255 static int auich_open(void *, int); 256 static void auich_close(void *); 257 static int auich_query_encoding(void *, struct audio_encoding *); 258 static int auich_set_params(void *, int, int, audio_params_t *, 259 audio_params_t *, stream_filter_list_t *, 260 stream_filter_list_t *); 261 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 262 static void auich_halt_pipe(struct auich_softc *, int); 263 static int auich_halt_output(void *); 264 static int auich_halt_input(void *); 265 static int auich_getdev(void *, struct audio_device *); 266 static int auich_set_port(void *, mixer_ctrl_t *); 267 static int auich_get_port(void *, mixer_ctrl_t *); 268 static int auich_query_devinfo(void *, mixer_devinfo_t *); 269 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 270 static void auich_freem(void *, void *, struct malloc_type *); 271 static size_t auich_round_buffersize(void *, int, size_t); 272 static paddr_t auich_mappage(void *, void *, off_t, int); 273 static int auich_get_props(void *); 274 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 275 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 276 static int auich_trigger_output(void *, void *, void *, int, 277 void (*)(void *), void *, const audio_params_t *); 278 static int auich_trigger_input(void *, void *, void *, int, 279 void (*)(void *), void *, const audio_params_t *); 280 static int auich_powerstate(void *, int); 281 282 static int auich_alloc_cdata(struct auich_softc *); 283 284 static int auich_allocmem(struct auich_softc *, size_t, size_t, 285 struct auich_dma *); 286 static int auich_freemem(struct auich_softc *, struct auich_dma *); 287 288 static bool auich_resume(device_t); 289 static int auich_set_rate(struct auich_softc *, int, u_long); 290 static int auich_sysctl_verify(SYSCTLFN_ARGS); 291 static void auich_finish_attach(struct device *); 292 static void auich_calibrate(struct auich_softc *); 293 static void auich_clear_cas(struct auich_softc *); 294 295 static int auich_attach_codec(void *, struct ac97_codec_if *); 296 static int auich_read_codec(void *, uint8_t, uint16_t *); 297 static int auich_write_codec(void *, uint8_t, uint16_t); 298 static int auich_reset_codec(void *); 299 static enum ac97_host_flags auich_flags_codec(void *); 300 static void auich_spdif_event(void *, bool); 301 302 static const struct audio_hw_if auich_hw_if = { 303 auich_open, 304 auich_close, 305 NULL, /* drain */ 306 auich_query_encoding, 307 auich_set_params, 308 auich_round_blocksize, 309 NULL, /* commit_setting */ 310 NULL, /* init_output */ 311 NULL, /* init_input */ 312 NULL, /* start_output */ 313 NULL, /* start_input */ 314 auich_halt_output, 315 auich_halt_input, 316 NULL, /* speaker_ctl */ 317 auich_getdev, 318 NULL, /* getfd */ 319 auich_set_port, 320 auich_get_port, 321 auich_query_devinfo, 322 auich_allocm, 323 auich_freem, 324 auich_round_buffersize, 325 auich_mappage, 326 auich_get_props, 327 auich_trigger_output, 328 auich_trigger_input, 329 NULL, /* dev_ioctl */ 330 auich_powerstate, 331 }; 332 333 #define AUICH_FORMATS_1CH 0 334 #define AUICH_FORMATS_4CH 1 335 #define AUICH_FORMATS_6CH 2 336 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 337 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 338 2, AUFMT_STEREO, 0, {8000, 48000}}, 339 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 340 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 341 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 342 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 343 }; 344 345 #define AUICH_SPDIF_NFORMATS 1 346 static const struct audio_format auich_spdif_formats[AUICH_SPDIF_NFORMATS] = { 347 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 348 2, AUFMT_STEREO, 1, {48000}}, 349 }; 350 351 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 352 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 353 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 354 }; 355 356 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 357 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 358 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 359 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 360 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 361 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 362 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 363 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 364 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 365 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 366 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 367 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 368 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 369 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 370 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 371 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 372 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 373 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 374 #define PCIID_NFORCE430 PCI_ID_CODE0(NVIDIA, NFORCE430_AC) 375 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 376 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 377 378 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 379 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 380 #define PCIID_ICH6MODEM PCI_ID_CODE0(INTEL, 82801FB_ACM) 381 382 struct auich_devtype { 383 pcireg_t id; 384 const char *name; 385 const char *shortname; /* must be less than 11 characters */ 386 }; 387 388 static const struct auich_devtype auich_audio_devices[] = { 389 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 390 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 391 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 392 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 393 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 394 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 395 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 396 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 397 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 398 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 399 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 400 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 401 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 402 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 403 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 404 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 405 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 406 { PCIID_NFORCE430, "nForce430 (MCP51) AC-97 Audio", "nForce430" }, 407 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 408 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 409 { 0, NULL, NULL }, 410 }; 411 412 static const struct auich_devtype auich_modem_devices[] = { 413 #ifdef AUICH_ATTACH_MODEM 414 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 415 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 416 { PCIID_ICH6MODEM, "i82801FB (ICH6) AC-97 Modem", "ICH6MODEM" }, 417 #endif 418 { 0, NULL, NULL }, 419 }; 420 421 static const struct auich_devtype * 422 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 423 { 424 const struct auich_devtype *d; 425 426 for (d = auich_devices; d->name != NULL; d++) { 427 if (pa->pa_id == d->id) 428 return d; 429 } 430 431 return NULL; 432 } 433 434 static int 435 auich_match(struct device *parent, struct cfdata *match, 436 void *aux) 437 { 438 struct pci_attach_args *pa; 439 440 pa = aux; 441 if (auich_lookup(pa, auich_audio_devices) != NULL) 442 return 1; 443 if (auich_lookup(pa, auich_modem_devices) != NULL) 444 return 1; 445 446 return 0; 447 } 448 449 static void 450 auich_attach(struct device *parent, struct device *self, void *aux) 451 { 452 struct auich_softc *sc; 453 struct pci_attach_args *pa; 454 pcireg_t v, subdev; 455 const char *intrstr; 456 const struct auich_devtype *d; 457 const struct sysctlnode *node, *node_ac97clock; 458 int err, node_mib, i; 459 460 sc = (struct auich_softc *)self; 461 pa = aux; 462 463 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 464 sc->sc_modem_offset = 0x10; 465 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 466 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 467 sc->sc_modem_offset = 0; 468 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 469 } else 470 panic("auich_attach: impossible"); 471 472 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 473 aprint_naive(": Audio controller\n"); 474 else 475 aprint_naive(": Modem controller\n"); 476 477 sc->sc_pc = pa->pa_pc; 478 sc->sc_pt = pa->pa_tag; 479 480 aprint_normal(": %s\n", d->name); 481 482 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 483 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 484 || d->id == PCIID_ICH4MODEM) { 485 /* 486 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 487 */ 488 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 489 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 490 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 491 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 492 v | ICH_CFG_IOSE); 493 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 494 0, &sc->iot, &sc->mix_ioh, NULL, 495 &sc->mix_size)) { 496 aprint_error("%s: can't map codec i/o space\n", 497 sc->sc_dev.dv_xname); 498 return; 499 } 500 } 501 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 502 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 503 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 504 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 505 v | ICH_CFG_IOSE); 506 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 507 0, &sc->iot, &sc->aud_ioh, NULL, 508 &sc->aud_size)) { 509 aprint_error("%s: can't map device i/o space\n", 510 sc->sc_dev.dv_xname); 511 return; 512 } 513 } 514 } else { 515 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 516 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 517 aprint_error("%s: can't map codec i/o space\n", 518 sc->sc_dev.dv_xname); 519 return; 520 } 521 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 522 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 523 aprint_error("%s: can't map device i/o space\n", 524 sc->sc_dev.dv_xname); 525 return; 526 } 527 } 528 sc->dmat = pa->pa_dmat; 529 530 /* enable bus mastering */ 531 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 532 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 533 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 534 535 /* Map and establish the interrupt. */ 536 if (pci_intr_map(pa, &sc->intrh)) { 537 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 538 return; 539 } 540 intrstr = pci_intr_string(pa->pa_pc, sc->intrh); 541 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO, 542 auich_intr, sc); 543 if (sc->sc_ih == NULL) { 544 aprint_error("%s: can't establish interrupt", 545 sc->sc_dev.dv_xname); 546 if (intrstr != NULL) 547 aprint_normal(" at %s", intrstr); 548 aprint_normal("\n"); 549 return; 550 } 551 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 552 553 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 554 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 555 "0x%02x", PCI_REVISION(pa->pa_class)); 556 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 557 558 /* SiS 7012 needs special handling */ 559 if (d->id == PCIID_SIS7012) { 560 sc->sc_sts_reg = ICH_PICB; 561 sc->sc_sample_shift = 0; 562 /* Un-mute output. From Linux. */ 563 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 564 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 565 ICH_SIS_CTL_UNMUTE); 566 } else { 567 sc->sc_sts_reg = ICH_STS; 568 sc->sc_sample_shift = 1; 569 } 570 571 /* Workaround for a 440MX B-stepping erratum */ 572 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 573 if (d->id == PCIID_440MX) { 574 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 575 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 576 } 577 578 /* Set up DMA lists. */ 579 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 580 auich_alloc_cdata(sc); 581 582 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 583 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 584 585 /* Modem codecs are always the secondary codec on ICH */ 586 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 587 588 sc->host_if.arg = sc; 589 sc->host_if.attach = auich_attach_codec; 590 sc->host_if.read = auich_read_codec; 591 sc->host_if.write = auich_write_codec; 592 sc->host_if.reset = auich_reset_codec; 593 sc->host_if.flags = auich_flags_codec; 594 sc->host_if.spdif_event = auich_spdif_event; 595 596 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 597 switch (subdev) { 598 case 0x202f161f: /* Gateway 7326GZ */ 599 case 0x203a161f: /* Gateway 4028GZ */ 600 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 601 case 0x8144104d: /* Sony VAIO PCG-TR* */ 602 case 0x8197104d: /* Sony S1XP */ 603 case 0x81c0104d: /* Sony VAIO type T */ 604 case 0x81c5104d: /* Sony VAIO VGN-B1XP */ 605 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP; 606 break; 607 default: 608 sc->sc_codecflags = 0; 609 break; 610 } 611 612 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 613 return; 614 sc->codec_if->vtbl->unlock(sc->codec_if); 615 616 /* setup audio_format */ 617 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 618 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 619 if (!AC97_IS_4CH(sc->codec_if)) 620 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 621 if (!AC97_IS_6CH(sc->codec_if)) 622 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 623 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 624 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 625 sc->sc_audio_formats[i].frequency_type = 1; 626 sc->sc_audio_formats[i].frequency[0] = 48000; 627 } 628 } 629 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 630 &sc->sc_encodings)) 631 return; 632 if (0 != auconv_create_encodings(auich_spdif_formats, AUICH_SPDIF_NFORMATS, 633 &sc->sc_spdif_encodings)) 634 return; 635 } else { 636 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 637 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 638 &sc->sc_encodings)) 639 return; 640 } 641 642 /* Watch for power change */ 643 if (!pmf_device_register(self, NULL, auich_resume)) 644 aprint_error_dev(self, "couldn't establish power handler\n"); 645 646 config_interrupts(self, auich_finish_attach); 647 648 /* sysctl setup */ 649 if (AC97_IS_FIXED_RATE(sc->codec_if) && 650 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 651 return; 652 653 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 654 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 655 CTL_HW, CTL_EOL); 656 if (err != 0) 657 goto sysctl_err; 658 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 659 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 660 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 661 if (err != 0) 662 goto sysctl_err; 663 node_mib = node->sysctl_num; 664 665 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 666 /* passing the sc address instead of &sc->sc_ac97_clock */ 667 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 668 CTLFLAG_READWRITE, 669 CTLTYPE_INT, "ac97rate", 670 SYSCTL_DESCR("AC'97 codec link rate"), 671 auich_sysctl_verify, 0, sc, 0, 672 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 673 if (err != 0) 674 goto sysctl_err; 675 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 676 } 677 678 return; 679 680 sysctl_err: 681 printf("%s: failed to add sysctl nodes. (%d)\n", 682 sc->sc_dev.dv_xname, err); 683 return; /* failure of sysctl is not fatal. */ 684 } 685 686 static int 687 auich_activate(struct device *self, enum devact act) 688 { 689 struct auich_softc *sc; 690 int ret; 691 692 sc = (struct auich_softc *)self; 693 ret = 0; 694 switch (act) { 695 case DVACT_ACTIVATE: 696 return EOPNOTSUPP; 697 case DVACT_DEACTIVATE: 698 if (sc->sc_audiodev != NULL) 699 ret = config_deactivate(sc->sc_audiodev); 700 return ret; 701 } 702 return EOPNOTSUPP; 703 } 704 705 static int 706 auich_detach(struct device *self, int flags) 707 { 708 struct auich_softc *sc; 709 710 sc = (struct auich_softc *)self; 711 712 /* audio */ 713 if (sc->sc_audiodev != NULL) 714 config_detach(sc->sc_audiodev, flags); 715 716 /* sysctl */ 717 sysctl_teardown(&sc->sc_log); 718 719 /* audio_encoding_set */ 720 auconv_delete_encodings(sc->sc_encodings); 721 auconv_delete_encodings(sc->sc_spdif_encodings); 722 723 /* ac97 */ 724 if (sc->codec_if != NULL) 725 sc->codec_if->vtbl->detach(sc->codec_if); 726 727 /* PCI */ 728 if (sc->sc_ih != NULL) 729 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 730 if (sc->mix_size != 0) 731 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 732 if (sc->aud_size != 0) 733 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 734 return 0; 735 } 736 737 static int 738 auich_sysctl_verify(SYSCTLFN_ARGS) 739 { 740 int error, tmp; 741 struct sysctlnode node; 742 struct auich_softc *sc; 743 744 node = *rnode; 745 sc = rnode->sysctl_data; 746 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 747 tmp = sc->sc_ac97_clock; 748 node.sysctl_data = &tmp; 749 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 750 if (error || newp == NULL) 751 return error; 752 753 if (tmp < 48000 || tmp > 96000) 754 return EINVAL; 755 sc->sc_ac97_clock = tmp; 756 } 757 758 return 0; 759 } 760 761 static void 762 auich_finish_attach(struct device *self) 763 { 764 struct auich_softc *sc; 765 766 sc = (void *)self; 767 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 768 auich_calibrate(sc); 769 770 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 771 772 return; 773 } 774 775 #define ICH_CODECIO_INTERVAL 10 776 static int 777 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 778 { 779 struct auich_softc *sc; 780 int i; 781 uint32_t status; 782 783 sc = v; 784 /* wait for an access semaphore */ 785 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 786 bus_space_read_1(sc->iot, sc->aud_ioh, 787 ICH_CAS + sc->sc_modem_offset) & 1; 788 DELAY(ICH_CODECIO_INTERVAL)); 789 790 if (i > 0) { 791 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 792 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 793 DPRINTF(ICH_DEBUG_CODECIO, 794 ("auich_read_codec(%x, %x)\n", reg, *val)); 795 status = bus_space_read_4(sc->iot, sc->aud_ioh, 796 ICH_GSTS + sc->sc_modem_offset); 797 if (status & ICH_RCS) { 798 bus_space_write_4(sc->iot, sc->aud_ioh, 799 ICH_GSTS + sc->sc_modem_offset, 800 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 801 *val = 0xffff; 802 DPRINTF(ICH_DEBUG_CODECIO, 803 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 804 if (reg == AC97_REG_GPIO_STATUS) 805 auich_clear_cas(sc); 806 return -1; 807 } 808 if (reg == AC97_REG_GPIO_STATUS) 809 auich_clear_cas(sc); 810 return 0; 811 } else { 812 aprint_normal("%s: read_codec timeout\n", sc->sc_dev.dv_xname); 813 if (reg == AC97_REG_GPIO_STATUS) 814 auich_clear_cas(sc); 815 return -1; 816 } 817 } 818 819 static int 820 auich_write_codec(void *v, uint8_t reg, uint16_t val) 821 { 822 struct auich_softc *sc; 823 int i; 824 825 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 826 sc = v; 827 /* wait for an access semaphore */ 828 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 829 bus_space_read_1(sc->iot, sc->aud_ioh, 830 ICH_CAS + sc->sc_modem_offset) & 1; 831 DELAY(ICH_CODECIO_INTERVAL)); 832 833 if (i > 0) { 834 bus_space_write_2(sc->iot, sc->mix_ioh, 835 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 836 return 0; 837 } else { 838 aprint_normal("%s: write_codec timeout\n", sc->sc_dev.dv_xname); 839 return -1; 840 } 841 } 842 843 static int 844 auich_attach_codec(void *v, struct ac97_codec_if *cif) 845 { 846 struct auich_softc *sc; 847 848 sc = v; 849 sc->codec_if = cif; 850 851 return 0; 852 } 853 854 static int 855 auich_reset_codec(void *v) 856 { 857 struct auich_softc *sc; 858 int i; 859 uint32_t control, status; 860 861 sc = v; 862 control = bus_space_read_4(sc->iot, sc->aud_ioh, 863 ICH_GCTRL + sc->sc_modem_offset); 864 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 865 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 866 } else { 867 control &= ~ICH_ACLSO; 868 control |= ICH_GIE; 869 } 870 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 871 bus_space_write_4(sc->iot, sc->aud_ioh, 872 ICH_GCTRL + sc->sc_modem_offset, control); 873 874 for (i = 500000; i >= 0; i--) { 875 status = bus_space_read_4(sc->iot, sc->aud_ioh, 876 ICH_GSTS + sc->sc_modem_offset); 877 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 878 break; 879 DELAY(1); 880 } 881 if (i <= 0) { 882 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 883 return ETIMEDOUT; 884 } 885 #ifdef AUICH_DEBUG 886 if (status & ICH_SCR) 887 printf("%s: The 2nd codec is ready.\n", 888 sc->sc_dev.dv_xname); 889 if (status & ICH_S2CR) 890 printf("%s: The 3rd codec is ready.\n", 891 sc->sc_dev.dv_xname); 892 #endif 893 return 0; 894 } 895 896 static enum ac97_host_flags 897 auich_flags_codec(void *v) 898 { 899 struct auich_softc *sc = v; 900 return sc->sc_codecflags; 901 } 902 903 static void 904 auich_spdif_event(void *addr, bool flag) 905 { 906 struct auich_softc *sc; 907 908 sc = addr; 909 sc->sc_spdif = flag; 910 } 911 912 static int 913 auich_open(void *addr, int flags) 914 { 915 struct auich_softc *sc; 916 917 sc = (struct auich_softc *)addr; 918 sc->codec_if->vtbl->lock(sc->codec_if); 919 return 0; 920 } 921 922 static void 923 auich_close(void *addr) 924 { 925 struct auich_softc *sc; 926 927 sc = (struct auich_softc *)addr; 928 sc->codec_if->vtbl->unlock(sc->codec_if); 929 } 930 931 static int 932 auich_query_encoding(void *v, struct audio_encoding *aep) 933 { 934 struct auich_softc *sc; 935 936 sc = (struct auich_softc *)v; 937 return auconv_query_encoding( 938 sc->sc_spdif ? sc->sc_spdif_encodings : sc->sc_encodings, aep); 939 } 940 941 static int 942 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 943 { 944 int ret; 945 u_int ratetmp; 946 947 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 948 ratetmp = srate; 949 if (mode == AUMODE_RECORD) 950 return sc->codec_if->vtbl->set_rate(sc->codec_if, 951 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 952 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 953 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 954 if (ret) 955 return ret; 956 ratetmp = srate; 957 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 958 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 959 if (ret) 960 return ret; 961 ratetmp = srate; 962 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 963 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 964 return ret; 965 } 966 967 static int 968 auich_set_params(void *v, int setmode, int usemode, 969 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 970 stream_filter_list_t *rfil) 971 { 972 struct auich_softc *sc; 973 audio_params_t *p; 974 stream_filter_list_t *fil; 975 int mode, index; 976 uint32_t control; 977 978 sc = v; 979 for (mode = AUMODE_RECORD; mode != -1; 980 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 981 if ((setmode & mode) == 0) 982 continue; 983 984 p = mode == AUMODE_PLAY ? play : rec; 985 fil = mode == AUMODE_PLAY ? pfil : rfil; 986 if (p == NULL) 987 continue; 988 989 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 990 if (p->sample_rate < 8000 || 991 p->sample_rate > 48000) 992 return EINVAL; 993 994 if (sc->sc_spdif) 995 index = auconv_set_converter(sc->sc_audio_formats, 996 AUICH_AUDIO_NFORMATS, mode, p, TRUE, fil); 997 else 998 index = auconv_set_converter(auich_spdif_formats, 999 AUICH_SPDIF_NFORMATS, mode, p, TRUE, fil); 1000 } else { 1001 if (p->sample_rate != 8000 && p->sample_rate != 16000) 1002 return EINVAL; 1003 index = auconv_set_converter(sc->sc_modem_formats, 1004 AUICH_MODEM_NFORMATS, mode, p, TRUE, fil); 1005 } 1006 if (index < 0) 1007 return EINVAL; 1008 if (fil->req_size > 0) 1009 p = &fil->filters[0].param; 1010 /* p represents HW encoding */ 1011 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1012 if (sc->sc_audio_formats[index].frequency_type != 1 1013 && auich_set_rate(sc, mode, p->sample_rate)) 1014 return EINVAL; 1015 } else { 1016 if (sc->sc_modem_formats[index].frequency_type != 1 1017 && auich_set_rate(sc, mode, p->sample_rate)) 1018 return EINVAL; 1019 auich_write_codec(sc, AC97_REG_LINE1_RATE, 1020 p->sample_rate); 1021 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 1022 } 1023 if (mode == AUMODE_PLAY && 1024 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1025 control = bus_space_read_4(sc->iot, sc->aud_ioh, 1026 ICH_GCTRL + sc->sc_modem_offset); 1027 control &= ~ICH_PCM246_MASK; 1028 if (p->channels == 4) { 1029 control |= ICH_PCM4; 1030 } else if (p->channels == 6) { 1031 control |= ICH_PCM6; 1032 } 1033 bus_space_write_4(sc->iot, sc->aud_ioh, 1034 ICH_GCTRL + sc->sc_modem_offset, control); 1035 } 1036 } 1037 1038 return 0; 1039 } 1040 1041 static int 1042 auich_round_blocksize(void *v, int blk, int mode, 1043 const audio_params_t *param) 1044 { 1045 1046 return blk & ~0x3f; /* keep good alignment */ 1047 } 1048 1049 static void 1050 auich_halt_pipe(struct auich_softc *sc, int pipe) 1051 { 1052 int i; 1053 uint32_t status; 1054 1055 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 1056 for (i = 0; i < 100; i++) { 1057 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 1058 if (status & ICH_DCH) 1059 break; 1060 DELAY(1); 1061 } 1062 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 1063 1064 #if AUICH_DEBUG 1065 if (i > 0) 1066 printf("auich_halt_pipe: halt took %d cycles\n", i); 1067 #endif 1068 } 1069 1070 static int 1071 auich_halt_output(void *v) 1072 { 1073 struct auich_softc *sc; 1074 1075 sc = v; 1076 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 1077 1078 auich_halt_pipe(sc, ICH_PCMO); 1079 sc->pcmo.intr = NULL; 1080 1081 return 0; 1082 } 1083 1084 static int 1085 auich_halt_input(void *v) 1086 { 1087 struct auich_softc *sc; 1088 1089 sc = v; 1090 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", sc->sc_dev.dv_xname)); 1091 1092 auich_halt_pipe(sc, ICH_PCMI); 1093 sc->pcmi.intr = NULL; 1094 1095 return 0; 1096 } 1097 1098 static int 1099 auich_getdev(void *v, struct audio_device *adp) 1100 { 1101 struct auich_softc *sc; 1102 1103 sc = v; 1104 *adp = sc->sc_audev; 1105 return 0; 1106 } 1107 1108 static int 1109 auich_set_port(void *v, mixer_ctrl_t *cp) 1110 { 1111 struct auich_softc *sc; 1112 1113 sc = v; 1114 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1115 } 1116 1117 static int 1118 auich_get_port(void *v, mixer_ctrl_t *cp) 1119 { 1120 struct auich_softc *sc; 1121 1122 sc = v; 1123 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1124 } 1125 1126 static int 1127 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1128 { 1129 struct auich_softc *sc; 1130 1131 sc = v; 1132 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1133 } 1134 1135 static void * 1136 auich_allocm(void *v, int direction, size_t size, 1137 struct malloc_type *pool, int flags) 1138 { 1139 struct auich_softc *sc; 1140 struct auich_dma *p; 1141 int error; 1142 1143 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1144 return NULL; 1145 1146 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1147 if (p == NULL) 1148 return NULL; 1149 1150 sc = v; 1151 error = auich_allocmem(sc, size, 0, p); 1152 if (error) { 1153 free(p, pool); 1154 return NULL; 1155 } 1156 1157 p->next = sc->sc_dmas; 1158 sc->sc_dmas = p; 1159 1160 return KERNADDR(p); 1161 } 1162 1163 static void 1164 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1165 { 1166 struct auich_softc *sc; 1167 struct auich_dma *p, **pp; 1168 1169 sc = v; 1170 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1171 if (KERNADDR(p) == ptr) { 1172 auich_freemem(sc, p); 1173 *pp = p->next; 1174 free(p, pool); 1175 return; 1176 } 1177 } 1178 } 1179 1180 static size_t 1181 auich_round_buffersize(void *v, int direction, size_t size) 1182 { 1183 1184 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1185 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1186 1187 return size; 1188 } 1189 1190 static paddr_t 1191 auich_mappage(void *v, void *mem, off_t off, int prot) 1192 { 1193 struct auich_softc *sc; 1194 struct auich_dma *p; 1195 1196 if (off < 0) 1197 return -1; 1198 sc = v; 1199 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1200 continue; 1201 if (!p) 1202 return -1; 1203 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1204 off, prot, BUS_DMA_WAITOK); 1205 } 1206 1207 static int 1208 auich_get_props(void *v) 1209 { 1210 struct auich_softc *sc; 1211 int props; 1212 1213 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1214 sc = v; 1215 /* 1216 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1217 * rate because of aurateconv. Applications can't know what rate the 1218 * device can process in the case of mmap(). 1219 */ 1220 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1221 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1222 props |= AUDIO_PROP_MMAP; 1223 return props; 1224 } 1225 1226 static int 1227 auich_intr(void *v) 1228 { 1229 struct auich_softc *sc; 1230 int ret, gsts; 1231 #ifdef DIAGNOSTIC 1232 int csts; 1233 #endif 1234 1235 sc = v; 1236 1237 if (!device_has_power(&sc->sc_dev)) 1238 return (0); 1239 1240 ret = 0; 1241 #ifdef DIAGNOSTIC 1242 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1243 if (csts & PCI_STATUS_MASTER_ABORT) { 1244 printf("auich_intr: PCI master abort\n"); 1245 } 1246 #endif 1247 1248 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1249 ICH_GSTS + sc->sc_modem_offset); 1250 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1251 1252 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1253 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1254 int sts; 1255 1256 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1257 ICH_PCMO + sc->sc_sts_reg); 1258 DPRINTF(ICH_DEBUG_INTR, 1259 ("auich_intr: osts=0x%x\n", sts)); 1260 1261 if (sts & ICH_FIFOE) 1262 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1263 1264 if (sts & ICH_BCIS) 1265 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1266 1267 /* int ack */ 1268 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1269 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1270 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1271 bus_space_write_4(sc->iot, sc->aud_ioh, 1272 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1273 else 1274 bus_space_write_4(sc->iot, sc->aud_ioh, 1275 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1276 ret++; 1277 } 1278 1279 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1280 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1281 int sts; 1282 1283 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1284 ICH_PCMI + sc->sc_sts_reg); 1285 DPRINTF(ICH_DEBUG_INTR, 1286 ("auich_intr: ists=0x%x\n", sts)); 1287 1288 if (sts & ICH_FIFOE) 1289 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1290 1291 if (sts & ICH_BCIS) 1292 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1293 1294 /* int ack */ 1295 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1296 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1297 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1298 bus_space_write_4(sc->iot, sc->aud_ioh, 1299 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1300 else 1301 bus_space_write_4(sc->iot, sc->aud_ioh, 1302 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1303 ret++; 1304 } 1305 1306 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1307 int sts; 1308 1309 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1310 ICH_MICI + sc->sc_sts_reg); 1311 DPRINTF(ICH_DEBUG_INTR, 1312 ("auich_intr: ists=0x%x\n", sts)); 1313 1314 if (sts & ICH_FIFOE) 1315 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1316 1317 if (sts & ICH_BCIS) 1318 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1319 1320 /* int ack */ 1321 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1322 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1323 bus_space_write_4(sc->iot, sc->aud_ioh, 1324 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1325 ret++; 1326 } 1327 1328 #ifdef AUICH_MODEM_DEBUG 1329 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1330 printf("%s: gsts=0x%x\n", sc->sc_dev.dv_xname, gsts); 1331 /* int ack */ 1332 bus_space_write_4(sc->iot, sc->aud_ioh, 1333 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1334 ret++; 1335 } 1336 #endif 1337 1338 return ret; 1339 } 1340 1341 static void 1342 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1343 { 1344 int blksize, qptr; 1345 struct auich_dmalist *q; 1346 1347 blksize = ring->blksize; 1348 1349 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1350 q = &ring->dmalist[qptr]; 1351 q->base = ring->p; 1352 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1353 1354 ring->p += blksize; 1355 if (ring->p >= ring->end) 1356 ring->p = ring->start; 1357 } 1358 ring->qptr = 0; 1359 1360 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1361 (qptr - 1) & ICH_LVI_MASK); 1362 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1363 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1364 } 1365 1366 static void 1367 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1368 { 1369 int blksize, qptr, nqptr; 1370 struct auich_dmalist *q; 1371 1372 blksize = ring->blksize; 1373 qptr = ring->qptr; 1374 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1375 1376 while (qptr != nqptr) { 1377 q = &ring->dmalist[qptr]; 1378 q->base = ring->p; 1379 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1380 1381 DPRINTF(ICH_DEBUG_INTR, 1382 ("auich_intr: %p, %p = %x @ 0x%x\n", 1383 &ring->dmalist[qptr], q, q->len, q->base)); 1384 1385 ring->p += blksize; 1386 if (ring->p >= ring->end) 1387 ring->p = ring->start; 1388 1389 qptr = (qptr + 1) & ICH_LVI_MASK; 1390 if (ring->intr) 1391 ring->intr(ring->arg); 1392 } 1393 ring->qptr = qptr; 1394 1395 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1396 (qptr - 1) & ICH_LVI_MASK); 1397 } 1398 1399 static int 1400 auich_trigger_output(void *v, void *start, void *end, int blksize, 1401 void (*intr)(void *), void *arg, const audio_params_t *param) 1402 { 1403 struct auich_softc *sc; 1404 struct auich_dma *p; 1405 size_t size; 1406 1407 DPRINTF(ICH_DEBUG_DMA, 1408 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1409 start, end, blksize, intr, arg, param)); 1410 sc = v; 1411 1412 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1413 continue; 1414 if (!p) { 1415 printf("auich_trigger_output: bad addr %p\n", start); 1416 return EINVAL; 1417 } 1418 1419 size = (size_t)((char *)end - (char *)start); 1420 1421 sc->pcmo.intr = intr; 1422 sc->pcmo.arg = arg; 1423 sc->pcmo.start = DMAADDR(p); 1424 sc->pcmo.p = sc->pcmo.start; 1425 sc->pcmo.end = sc->pcmo.start + size; 1426 sc->pcmo.blksize = blksize; 1427 1428 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1429 sc->sc_cddma + ICH_PCMO_OFF(0)); 1430 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1431 1432 return 0; 1433 } 1434 1435 static int 1436 auich_trigger_input(void *v, void *start, void *end, int blksize, 1437 void (*intr)(void *), void *arg, const audio_params_t *param) 1438 { 1439 struct auich_softc *sc; 1440 struct auich_dma *p; 1441 size_t size; 1442 1443 DPRINTF(ICH_DEBUG_DMA, 1444 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1445 start, end, blksize, intr, arg, param)); 1446 sc = v; 1447 1448 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1449 continue; 1450 if (!p) { 1451 printf("auich_trigger_input: bad addr %p\n", start); 1452 return EINVAL; 1453 } 1454 1455 size = (size_t)((char *)end - (char *)start); 1456 1457 sc->pcmi.intr = intr; 1458 sc->pcmi.arg = arg; 1459 sc->pcmi.start = DMAADDR(p); 1460 sc->pcmi.p = sc->pcmi.start; 1461 sc->pcmi.end = sc->pcmi.start + size; 1462 sc->pcmi.blksize = blksize; 1463 1464 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1465 sc->sc_cddma + ICH_PCMI_OFF(0)); 1466 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1467 1468 return 0; 1469 } 1470 1471 static int 1472 auich_powerstate(void *v, int state) 1473 { 1474 return 0; 1475 } 1476 1477 static int 1478 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1479 struct auich_dma *p) 1480 { 1481 int error; 1482 1483 p->size = size; 1484 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1485 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1486 &p->nsegs, BUS_DMA_NOWAIT); 1487 if (error) 1488 return error; 1489 1490 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1491 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1492 if (error) 1493 goto free; 1494 1495 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1496 0, BUS_DMA_NOWAIT, &p->map); 1497 if (error) 1498 goto unmap; 1499 1500 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1501 BUS_DMA_NOWAIT); 1502 if (error) 1503 goto destroy; 1504 return 0; 1505 1506 destroy: 1507 bus_dmamap_destroy(sc->dmat, p->map); 1508 unmap: 1509 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1510 free: 1511 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1512 return error; 1513 } 1514 1515 static int 1516 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1517 { 1518 1519 bus_dmamap_unload(sc->dmat, p->map); 1520 bus_dmamap_destroy(sc->dmat, p->map); 1521 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1522 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1523 return 0; 1524 } 1525 1526 static int 1527 auich_alloc_cdata(struct auich_softc *sc) 1528 { 1529 bus_dma_segment_t seg; 1530 int error, rseg; 1531 1532 /* 1533 * Allocate the control data structure, and create and load the 1534 * DMA map for it. 1535 */ 1536 if ((error = bus_dmamem_alloc(sc->dmat, 1537 sizeof(struct auich_cdata), 1538 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1539 printf("%s: unable to allocate control data, error = %d\n", 1540 sc->sc_dev.dv_xname, error); 1541 goto fail_0; 1542 } 1543 1544 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1545 sizeof(struct auich_cdata), 1546 (void **) &sc->sc_cdata, 1547 sc->sc_dmamap_flags)) != 0) { 1548 printf("%s: unable to map control data, error = %d\n", 1549 sc->sc_dev.dv_xname, error); 1550 goto fail_1; 1551 } 1552 1553 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1554 sizeof(struct auich_cdata), 0, 0, 1555 &sc->sc_cddmamap)) != 0) { 1556 printf("%s: unable to create control data DMA map, " 1557 "error = %d\n", sc->sc_dev.dv_xname, error); 1558 goto fail_2; 1559 } 1560 1561 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1562 sc->sc_cdata, sizeof(struct auich_cdata), 1563 NULL, 0)) != 0) { 1564 printf("%s: unable tp load control data DMA map, " 1565 "error = %d\n", sc->sc_dev.dv_xname, error); 1566 goto fail_3; 1567 } 1568 1569 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1570 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1571 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1572 1573 return 0; 1574 1575 fail_3: 1576 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1577 fail_2: 1578 bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata, 1579 sizeof(struct auich_cdata)); 1580 fail_1: 1581 bus_dmamem_free(sc->dmat, &seg, rseg); 1582 fail_0: 1583 return error; 1584 } 1585 1586 static bool 1587 auich_resume(device_t dv) 1588 { 1589 struct auich_softc *sc = device_private(dv); 1590 1591 auich_reset_codec(sc); 1592 DELAY(1000); 1593 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1594 return true; 1595 } 1596 1597 /* 1598 * Calibrate card (some boards are overclocked and need scaling) 1599 */ 1600 static void 1601 auich_calibrate(struct auich_softc *sc) 1602 { 1603 struct timeval t1, t2; 1604 uint8_t ociv, nciv; 1605 uint64_t wait_us; 1606 uint32_t actual_48k_rate, bytes, ac97rate; 1607 void *temp_buffer; 1608 struct auich_dma *p; 1609 u_int rate; 1610 1611 /* 1612 * Grab audio from input for fixed interval and compare how 1613 * much we actually get with what we expect. Interval needs 1614 * to be sufficiently short that no interrupts are 1615 * generated. 1616 */ 1617 1618 /* Force the codec to a known state first. */ 1619 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1620 rate = sc->sc_ac97_clock = 48000; 1621 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1622 &rate); 1623 1624 /* Setup a buffer */ 1625 bytes = 64000; 1626 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1627 1628 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1629 continue; 1630 if (p == NULL) { 1631 printf("auich_calibrate: bad address %p\n", temp_buffer); 1632 return; 1633 } 1634 sc->pcmi.dmalist[0].base = DMAADDR(p); 1635 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1636 1637 /* 1638 * our data format is stereo, 16 bit so each sample is 4 bytes. 1639 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1640 * we're going to start recording with interrupts disabled and measure 1641 * the time taken for one block to complete. we know the block size, 1642 * we know the time in microseconds, we calculate the sample rate: 1643 * 1644 * actual_rate [bps] = bytes / (time [s] * 4) 1645 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1646 * actual_rate [Hz] = (bytes * 250000) / time [us] 1647 */ 1648 1649 /* prepare */ 1650 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1651 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1652 sc->sc_cddma + ICH_PCMI_OFF(0)); 1653 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1654 (0 - 1) & ICH_LVI_MASK); 1655 1656 /* start */ 1657 microtime(&t1); 1658 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1659 1660 /* wait */ 1661 nciv = ociv; 1662 do { 1663 microtime(&t2); 1664 if (t2.tv_sec - t1.tv_sec > 1) 1665 break; 1666 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1667 ICH_PCMI + ICH_CIV); 1668 } while (nciv == ociv); 1669 microtime(&t2); 1670 1671 /* stop */ 1672 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1673 1674 /* reset */ 1675 DELAY(100); 1676 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1677 1678 /* turn time delta into us */ 1679 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1680 1681 auich_freem(sc, temp_buffer, M_DEVBUF); 1682 1683 if (nciv == ociv) { 1684 printf("%s: ac97 link rate calibration timed out after %" 1685 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1686 return; 1687 } 1688 1689 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1690 1691 if (actual_48k_rate < 50000) 1692 ac97rate = 48000; 1693 else 1694 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1695 1696 printf("%s: measured ac97 link rate at %d Hz", 1697 sc->sc_dev.dv_xname, actual_48k_rate); 1698 if (ac97rate != actual_48k_rate) 1699 printf(", will use %d Hz", ac97rate); 1700 printf("\n"); 1701 1702 sc->sc_ac97_clock = ac97rate; 1703 } 1704 1705 static void 1706 auich_clear_cas(struct auich_softc *sc) 1707 { 1708 /* Clear the codec access semaphore */ 1709 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1710 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1711 1712 return; 1713 } 1714
Indexes created Wed Oct 22 13:09:56 GMT 2025