auich.c revision 1.121
1 /* $NetBSD: auich.c,v 1.121 2007/12/13 15:11:31 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.121 2007/12/13 15:11:31 jmcneill Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <sys/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 void *addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 pci_intr_handle_t intrh; 187 188 struct ac97_codec_if *codec_if; 189 struct ac97_host_if host_if; 190 int sc_codecnum; 191 int sc_codectype; 192 enum ac97_host_flags sc_codecflags; 193 bool sc_spdif; 194 195 /* DMA scatter-gather lists. */ 196 bus_dmamap_t sc_cddmamap; 197 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 198 199 struct auich_cdata *sc_cdata; 200 201 struct auich_ring { 202 int qptr; 203 struct auich_dmalist *dmalist; 204 205 uint32_t start, p, end; 206 int blksize; 207 208 void (*intr)(void *); 209 void *arg; 210 } pcmo, pcmi, mici; 211 212 struct auich_dma *sc_dmas; 213 214 /* SiS 7012 hack */ 215 int sc_sample_shift; 216 int sc_sts_reg; 217 /* 440MX workaround */ 218 int sc_dmamap_flags; 219 /* Native mode? */ 220 int sc_native_mode; 221 222 /* sysctl */ 223 struct sysctllog *sc_log; 224 uint32_t sc_ac97_clock; 225 int sc_ac97_clock_mib; 226 227 int sc_modem_offset; 228 229 #define AUICH_AUDIO_NFORMATS 3 230 #define AUICH_MODEM_NFORMATS 1 231 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 232 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 233 struct audio_encoding_set *sc_encodings; 234 struct audio_encoding_set *sc_spdif_encodings; 235 }; 236 237 /* Debug */ 238 #ifdef AUICH_DEBUG 239 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 240 int auich_debug = 0xfffe; 241 #define ICH_DEBUG_CODECIO 0x0001 242 #define ICH_DEBUG_DMA 0x0002 243 #define ICH_DEBUG_INTR 0x0004 244 #else 245 #define DPRINTF(x,y) /* nothing */ 246 #endif 247 248 static int auich_match(struct device *, struct cfdata *, void *); 249 static void auich_attach(struct device *, struct device *, void *); 250 static int auich_detach(struct device *, int); 251 static int auich_activate(struct device *, enum devact); 252 static int auich_intr(void *); 253 254 CFATTACH_DECL(auich, sizeof(struct auich_softc), 255 auich_match, auich_attach, auich_detach, auich_activate); 256 257 static int auich_open(void *, int); 258 static void auich_close(void *); 259 static int auich_query_encoding(void *, struct audio_encoding *); 260 static int auich_set_params(void *, int, int, audio_params_t *, 261 audio_params_t *, stream_filter_list_t *, 262 stream_filter_list_t *); 263 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 264 static void auich_halt_pipe(struct auich_softc *, int); 265 static int auich_halt_output(void *); 266 static int auich_halt_input(void *); 267 static int auich_getdev(void *, struct audio_device *); 268 static int auich_set_port(void *, mixer_ctrl_t *); 269 static int auich_get_port(void *, mixer_ctrl_t *); 270 static int auich_query_devinfo(void *, mixer_devinfo_t *); 271 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 272 static void auich_freem(void *, void *, struct malloc_type *); 273 static size_t auich_round_buffersize(void *, int, size_t); 274 static paddr_t auich_mappage(void *, void *, off_t, int); 275 static int auich_get_props(void *); 276 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 277 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 278 static int auich_trigger_output(void *, void *, void *, int, 279 void (*)(void *), void *, const audio_params_t *); 280 static int auich_trigger_input(void *, void *, void *, int, 281 void (*)(void *), void *, const audio_params_t *); 282 static int auich_powerstate(void *, int); 283 284 static int auich_alloc_cdata(struct auich_softc *); 285 286 static int auich_allocmem(struct auich_softc *, size_t, size_t, 287 struct auich_dma *); 288 static int auich_freemem(struct auich_softc *, struct auich_dma *); 289 290 static bool auich_resume(device_t); 291 static int auich_set_rate(struct auich_softc *, int, u_long); 292 static int auich_sysctl_verify(SYSCTLFN_ARGS); 293 static void auich_finish_attach(struct device *); 294 static void auich_calibrate(struct auich_softc *); 295 static void auich_clear_cas(struct auich_softc *); 296 297 static int auich_attach_codec(void *, struct ac97_codec_if *); 298 static int auich_read_codec(void *, uint8_t, uint16_t *); 299 static int auich_write_codec(void *, uint8_t, uint16_t); 300 static int auich_reset_codec(void *); 301 static enum ac97_host_flags auich_flags_codec(void *); 302 static void auich_spdif_event(void *, bool); 303 304 static const struct audio_hw_if auich_hw_if = { 305 auich_open, 306 auich_close, 307 NULL, /* drain */ 308 auich_query_encoding, 309 auich_set_params, 310 auich_round_blocksize, 311 NULL, /* commit_setting */ 312 NULL, /* init_output */ 313 NULL, /* init_input */ 314 NULL, /* start_output */ 315 NULL, /* start_input */ 316 auich_halt_output, 317 auich_halt_input, 318 NULL, /* speaker_ctl */ 319 auich_getdev, 320 NULL, /* getfd */ 321 auich_set_port, 322 auich_get_port, 323 auich_query_devinfo, 324 auich_allocm, 325 auich_freem, 326 auich_round_buffersize, 327 auich_mappage, 328 auich_get_props, 329 auich_trigger_output, 330 auich_trigger_input, 331 NULL, /* dev_ioctl */ 332 auich_powerstate, 333 }; 334 335 #define AUICH_FORMATS_1CH 0 336 #define AUICH_FORMATS_4CH 1 337 #define AUICH_FORMATS_6CH 2 338 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 339 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 340 2, AUFMT_STEREO, 0, {8000, 48000}}, 341 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 342 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 343 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 344 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 345 }; 346 347 #define AUICH_SPDIF_NFORMATS 1 348 static const struct audio_format auich_spdif_formats[AUICH_SPDIF_NFORMATS] = { 349 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 350 2, AUFMT_STEREO, 1, {48000}}, 351 }; 352 353 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 354 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 355 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 356 }; 357 358 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 359 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 360 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 361 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 362 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 363 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 364 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 365 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 366 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 367 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 368 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 369 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 370 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 371 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 372 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 373 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 374 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 375 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 376 #define PCIID_NFORCE430 PCI_ID_CODE0(NVIDIA, NFORCE430_AC) 377 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 378 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 379 380 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 381 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 382 #define PCIID_ICH6MODEM PCI_ID_CODE0(INTEL, 82801FB_ACM) 383 384 struct auich_devtype { 385 pcireg_t id; 386 const char *name; 387 const char *shortname; /* must be less than 11 characters */ 388 }; 389 390 static const struct auich_devtype auich_audio_devices[] = { 391 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 392 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 393 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 394 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 395 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 396 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 397 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 398 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 399 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 400 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 401 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 402 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 403 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 404 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 405 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 406 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 407 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 408 { PCIID_NFORCE430, "nForce430 (MCP51) AC-97 Audio", "nForce430" }, 409 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 410 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 411 { 0, NULL, NULL }, 412 }; 413 414 static const struct auich_devtype auich_modem_devices[] = { 415 #ifdef AUICH_ATTACH_MODEM 416 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 417 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 418 { PCIID_ICH6MODEM, "i82801FB (ICH6) AC-97 Modem", "ICH6MODEM" }, 419 #endif 420 { 0, NULL, NULL }, 421 }; 422 423 static const struct auich_devtype * 424 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 425 { 426 const struct auich_devtype *d; 427 428 for (d = auich_devices; d->name != NULL; d++) { 429 if (pa->pa_id == d->id) 430 return d; 431 } 432 433 return NULL; 434 } 435 436 static int 437 auich_match(struct device *parent, struct cfdata *match, 438 void *aux) 439 { 440 struct pci_attach_args *pa; 441 442 pa = aux; 443 if (auich_lookup(pa, auich_audio_devices) != NULL) 444 return 1; 445 if (auich_lookup(pa, auich_modem_devices) != NULL) 446 return 1; 447 448 return 0; 449 } 450 451 static void 452 auich_attach(struct device *parent, struct device *self, void *aux) 453 { 454 struct auich_softc *sc; 455 struct pci_attach_args *pa; 456 pcireg_t v, subdev; 457 const char *intrstr; 458 const struct auich_devtype *d; 459 const struct sysctlnode *node, *node_ac97clock; 460 int err, node_mib, i; 461 462 sc = (struct auich_softc *)self; 463 pa = aux; 464 465 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 466 sc->sc_modem_offset = 0x10; 467 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 468 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 469 sc->sc_modem_offset = 0; 470 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 471 } else 472 panic("auich_attach: impossible"); 473 474 sc->sc_devtype = d->id; 475 476 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 477 aprint_naive(": Audio controller\n"); 478 else 479 aprint_naive(": Modem controller\n"); 480 481 sc->sc_pc = pa->pa_pc; 482 sc->sc_pt = pa->pa_tag; 483 484 aprint_normal(": %s\n", d->name); 485 486 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 487 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 488 || d->id == PCIID_ICH4MODEM) { 489 sc->sc_native_mode = 1; 490 /* 491 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 492 */ 493 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 494 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 495 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 496 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 497 v | ICH_CFG_IOSE); 498 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 499 0, &sc->iot, &sc->mix_ioh, NULL, 500 &sc->mix_size)) { 501 aprint_error("%s: can't map codec i/o space\n", 502 sc->sc_dev.dv_xname); 503 return; 504 } 505 } 506 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 507 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 508 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 509 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 510 v | ICH_CFG_IOSE); 511 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 512 0, &sc->iot, &sc->aud_ioh, NULL, 513 &sc->aud_size)) { 514 aprint_error("%s: can't map device i/o space\n", 515 sc->sc_dev.dv_xname); 516 return; 517 } 518 } 519 } else { 520 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 521 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 522 aprint_error("%s: can't map codec i/o space\n", 523 sc->sc_dev.dv_xname); 524 return; 525 } 526 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 527 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 528 aprint_error("%s: can't map device i/o space\n", 529 sc->sc_dev.dv_xname); 530 return; 531 } 532 } 533 sc->dmat = pa->pa_dmat; 534 535 /* enable bus mastering */ 536 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 537 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 538 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 539 540 /* Map and establish the interrupt. */ 541 if (pci_intr_map(pa, &sc->intrh)) { 542 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 543 return; 544 } 545 intrstr = pci_intr_string(pa->pa_pc, sc->intrh); 546 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO, 547 auich_intr, sc); 548 if (sc->sc_ih == NULL) { 549 aprint_error("%s: can't establish interrupt", 550 sc->sc_dev.dv_xname); 551 if (intrstr != NULL) 552 aprint_normal(" at %s", intrstr); 553 aprint_normal("\n"); 554 return; 555 } 556 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 557 558 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 559 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 560 "0x%02x", PCI_REVISION(pa->pa_class)); 561 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 562 563 /* SiS 7012 needs special handling */ 564 if (d->id == PCIID_SIS7012) { 565 sc->sc_sts_reg = ICH_PICB; 566 sc->sc_sample_shift = 0; 567 /* Un-mute output. From Linux. */ 568 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 569 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 570 ICH_SIS_CTL_UNMUTE); 571 } else { 572 sc->sc_sts_reg = ICH_STS; 573 sc->sc_sample_shift = 1; 574 } 575 576 /* Workaround for a 440MX B-stepping erratum */ 577 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 578 if (d->id == PCIID_440MX) { 579 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 580 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 581 } 582 583 /* Set up DMA lists. */ 584 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 585 auich_alloc_cdata(sc); 586 587 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 588 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 589 590 /* Modem codecs are always the secondary codec on ICH */ 591 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 592 593 sc->host_if.arg = sc; 594 sc->host_if.attach = auich_attach_codec; 595 sc->host_if.read = auich_read_codec; 596 sc->host_if.write = auich_write_codec; 597 sc->host_if.reset = auich_reset_codec; 598 sc->host_if.flags = auich_flags_codec; 599 sc->host_if.spdif_event = auich_spdif_event; 600 601 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 602 switch (subdev) { 603 case 0x202f161f: /* Gateway 7326GZ */ 604 case 0x203a161f: /* Gateway 4028GZ */ 605 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 606 case 0x8144104d: /* Sony VAIO PCG-TR* */ 607 case 0x8197104d: /* Sony S1XP */ 608 case 0x81c0104d: /* Sony VAIO type T */ 609 case 0x81c5104d: /* Sony VAIO VGN-B1XP */ 610 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP; 611 break; 612 default: 613 sc->sc_codecflags = 0; 614 break; 615 } 616 617 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 618 return; 619 sc->codec_if->vtbl->unlock(sc->codec_if); 620 621 /* setup audio_format */ 622 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 623 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 624 if (!AC97_IS_4CH(sc->codec_if)) 625 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 626 if (!AC97_IS_6CH(sc->codec_if)) 627 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 628 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 629 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 630 sc->sc_audio_formats[i].frequency_type = 1; 631 sc->sc_audio_formats[i].frequency[0] = 48000; 632 } 633 } 634 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 635 &sc->sc_encodings)) 636 return; 637 if (0 != auconv_create_encodings(auich_spdif_formats, AUICH_SPDIF_NFORMATS, 638 &sc->sc_spdif_encodings)) 639 return; 640 } else { 641 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 642 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 643 &sc->sc_encodings)) 644 return; 645 } 646 647 /* Watch for power change */ 648 if (!pmf_device_register(self, NULL, auich_resume)) 649 aprint_error_dev(self, "couldn't establish power handler\n"); 650 651 config_interrupts(self, auich_finish_attach); 652 653 /* sysctl setup */ 654 if (AC97_IS_FIXED_RATE(sc->codec_if) && 655 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 656 return; 657 658 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 659 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 660 CTL_HW, CTL_EOL); 661 if (err != 0) 662 goto sysctl_err; 663 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 664 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 665 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 666 if (err != 0) 667 goto sysctl_err; 668 node_mib = node->sysctl_num; 669 670 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 671 /* passing the sc address instead of &sc->sc_ac97_clock */ 672 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 673 CTLFLAG_READWRITE, 674 CTLTYPE_INT, "ac97rate", 675 SYSCTL_DESCR("AC'97 codec link rate"), 676 auich_sysctl_verify, 0, sc, 0, 677 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 678 if (err != 0) 679 goto sysctl_err; 680 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 681 } 682 683 return; 684 685 sysctl_err: 686 printf("%s: failed to add sysctl nodes. (%d)\n", 687 sc->sc_dev.dv_xname, err); 688 return; /* failure of sysctl is not fatal. */ 689 } 690 691 static int 692 auich_activate(struct device *self, enum devact act) 693 { 694 struct auich_softc *sc; 695 int ret; 696 697 sc = (struct auich_softc *)self; 698 ret = 0; 699 switch (act) { 700 case DVACT_ACTIVATE: 701 return EOPNOTSUPP; 702 case DVACT_DEACTIVATE: 703 if (sc->sc_audiodev != NULL) 704 ret = config_deactivate(sc->sc_audiodev); 705 return ret; 706 } 707 return EOPNOTSUPP; 708 } 709 710 static int 711 auich_detach(struct device *self, int flags) 712 { 713 struct auich_softc *sc; 714 715 sc = (struct auich_softc *)self; 716 717 /* audio */ 718 if (sc->sc_audiodev != NULL) 719 config_detach(sc->sc_audiodev, flags); 720 721 /* sysctl */ 722 sysctl_teardown(&sc->sc_log); 723 724 /* audio_encoding_set */ 725 auconv_delete_encodings(sc->sc_encodings); 726 auconv_delete_encodings(sc->sc_spdif_encodings); 727 728 /* ac97 */ 729 if (sc->codec_if != NULL) 730 sc->codec_if->vtbl->detach(sc->codec_if); 731 732 /* PCI */ 733 if (sc->sc_ih != NULL) 734 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 735 if (sc->mix_size != 0) 736 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 737 if (sc->aud_size != 0) 738 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 739 return 0; 740 } 741 742 static int 743 auich_sysctl_verify(SYSCTLFN_ARGS) 744 { 745 int error, tmp; 746 struct sysctlnode node; 747 struct auich_softc *sc; 748 749 node = *rnode; 750 sc = rnode->sysctl_data; 751 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 752 tmp = sc->sc_ac97_clock; 753 node.sysctl_data = &tmp; 754 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 755 if (error || newp == NULL) 756 return error; 757 758 if (tmp < 48000 || tmp > 96000) 759 return EINVAL; 760 sc->sc_ac97_clock = tmp; 761 } 762 763 return 0; 764 } 765 766 static void 767 auich_finish_attach(struct device *self) 768 { 769 struct auich_softc *sc; 770 771 sc = (void *)self; 772 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 773 auich_calibrate(sc); 774 775 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 776 777 return; 778 } 779 780 #define ICH_CODECIO_INTERVAL 10 781 static int 782 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 783 { 784 struct auich_softc *sc; 785 int i; 786 uint32_t status; 787 788 sc = v; 789 /* wait for an access semaphore */ 790 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 791 bus_space_read_1(sc->iot, sc->aud_ioh, 792 ICH_CAS + sc->sc_modem_offset) & 1; 793 DELAY(ICH_CODECIO_INTERVAL)); 794 795 if (i > 0) { 796 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 797 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 798 DPRINTF(ICH_DEBUG_CODECIO, 799 ("auich_read_codec(%x, %x)\n", reg, *val)); 800 status = bus_space_read_4(sc->iot, sc->aud_ioh, 801 ICH_GSTS + sc->sc_modem_offset); 802 if (status & ICH_RCS) { 803 bus_space_write_4(sc->iot, sc->aud_ioh, 804 ICH_GSTS + sc->sc_modem_offset, 805 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 806 *val = 0xffff; 807 DPRINTF(ICH_DEBUG_CODECIO, 808 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 809 if (reg == AC97_REG_GPIO_STATUS) 810 auich_clear_cas(sc); 811 return -1; 812 } 813 if (reg == AC97_REG_GPIO_STATUS) 814 auich_clear_cas(sc); 815 return 0; 816 } else { 817 aprint_normal("%s: read_codec timeout\n", sc->sc_dev.dv_xname); 818 if (reg == AC97_REG_GPIO_STATUS) 819 auich_clear_cas(sc); 820 return -1; 821 } 822 } 823 824 static int 825 auich_write_codec(void *v, uint8_t reg, uint16_t val) 826 { 827 struct auich_softc *sc; 828 int i; 829 830 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 831 sc = v; 832 /* wait for an access semaphore */ 833 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 834 bus_space_read_1(sc->iot, sc->aud_ioh, 835 ICH_CAS + sc->sc_modem_offset) & 1; 836 DELAY(ICH_CODECIO_INTERVAL)); 837 838 if (i > 0) { 839 bus_space_write_2(sc->iot, sc->mix_ioh, 840 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 841 return 0; 842 } else { 843 aprint_normal("%s: write_codec timeout\n", sc->sc_dev.dv_xname); 844 return -1; 845 } 846 } 847 848 static int 849 auich_attach_codec(void *v, struct ac97_codec_if *cif) 850 { 851 struct auich_softc *sc; 852 853 sc = v; 854 sc->codec_if = cif; 855 856 return 0; 857 } 858 859 static int 860 auich_reset_codec(void *v) 861 { 862 struct auich_softc *sc; 863 int i; 864 uint32_t control, status; 865 866 sc = v; 867 control = bus_space_read_4(sc->iot, sc->aud_ioh, 868 ICH_GCTRL + sc->sc_modem_offset); 869 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 870 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 871 } else { 872 control &= ~ICH_ACLSO; 873 control |= ICH_GIE; 874 } 875 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 876 bus_space_write_4(sc->iot, sc->aud_ioh, 877 ICH_GCTRL + sc->sc_modem_offset, control); 878 879 for (i = 500000; i >= 0; i--) { 880 status = bus_space_read_4(sc->iot, sc->aud_ioh, 881 ICH_GSTS + sc->sc_modem_offset); 882 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 883 break; 884 DELAY(1); 885 } 886 if (i <= 0) { 887 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 888 return ETIMEDOUT; 889 } 890 #ifdef AUICH_DEBUG 891 if (status & ICH_SCR) 892 printf("%s: The 2nd codec is ready.\n", 893 sc->sc_dev.dv_xname); 894 if (status & ICH_S2CR) 895 printf("%s: The 3rd codec is ready.\n", 896 sc->sc_dev.dv_xname); 897 #endif 898 return 0; 899 } 900 901 static enum ac97_host_flags 902 auich_flags_codec(void *v) 903 { 904 struct auich_softc *sc = v; 905 return sc->sc_codecflags; 906 } 907 908 static void 909 auich_spdif_event(void *addr, bool flag) 910 { 911 struct auich_softc *sc; 912 913 sc = addr; 914 sc->sc_spdif = flag; 915 } 916 917 static int 918 auich_open(void *addr, int flags) 919 { 920 struct auich_softc *sc; 921 922 sc = (struct auich_softc *)addr; 923 sc->codec_if->vtbl->lock(sc->codec_if); 924 return 0; 925 } 926 927 static void 928 auich_close(void *addr) 929 { 930 struct auich_softc *sc; 931 932 sc = (struct auich_softc *)addr; 933 sc->codec_if->vtbl->unlock(sc->codec_if); 934 } 935 936 static int 937 auich_query_encoding(void *v, struct audio_encoding *aep) 938 { 939 struct auich_softc *sc; 940 941 sc = (struct auich_softc *)v; 942 return auconv_query_encoding( 943 sc->sc_spdif ? sc->sc_spdif_encodings : sc->sc_encodings, aep); 944 } 945 946 static int 947 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 948 { 949 int ret; 950 u_int ratetmp; 951 952 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 953 ratetmp = srate; 954 if (mode == AUMODE_RECORD) 955 return sc->codec_if->vtbl->set_rate(sc->codec_if, 956 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 957 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 958 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 959 if (ret) 960 return ret; 961 ratetmp = srate; 962 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 963 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 964 if (ret) 965 return ret; 966 ratetmp = srate; 967 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 968 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 969 return ret; 970 } 971 972 static int 973 auich_set_params(void *v, int setmode, int usemode, 974 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 975 stream_filter_list_t *rfil) 976 { 977 struct auich_softc *sc; 978 audio_params_t *p; 979 stream_filter_list_t *fil; 980 int mode, index; 981 uint32_t control; 982 983 sc = v; 984 for (mode = AUMODE_RECORD; mode != -1; 985 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 986 if ((setmode & mode) == 0) 987 continue; 988 989 p = mode == AUMODE_PLAY ? play : rec; 990 fil = mode == AUMODE_PLAY ? pfil : rfil; 991 if (p == NULL) 992 continue; 993 994 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 995 if (p->sample_rate < 8000 || 996 p->sample_rate > 48000) 997 return EINVAL; 998 999 if (sc->sc_spdif) 1000 index = auconv_set_converter(sc->sc_audio_formats, 1001 AUICH_AUDIO_NFORMATS, mode, p, TRUE, fil); 1002 else 1003 index = auconv_set_converter(auich_spdif_formats, 1004 AUICH_SPDIF_NFORMATS, mode, p, TRUE, fil); 1005 } else { 1006 if (p->sample_rate != 8000 && p->sample_rate != 16000) 1007 return EINVAL; 1008 index = auconv_set_converter(sc->sc_modem_formats, 1009 AUICH_MODEM_NFORMATS, mode, p, TRUE, fil); 1010 } 1011 if (index < 0) 1012 return EINVAL; 1013 if (fil->req_size > 0) 1014 p = &fil->filters[0].param; 1015 /* p represents HW encoding */ 1016 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1017 if (sc->sc_audio_formats[index].frequency_type != 1 1018 && auich_set_rate(sc, mode, p->sample_rate)) 1019 return EINVAL; 1020 } else { 1021 if (sc->sc_modem_formats[index].frequency_type != 1 1022 && auich_set_rate(sc, mode, p->sample_rate)) 1023 return EINVAL; 1024 auich_write_codec(sc, AC97_REG_LINE1_RATE, 1025 p->sample_rate); 1026 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 1027 } 1028 if (mode == AUMODE_PLAY && 1029 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1030 control = bus_space_read_4(sc->iot, sc->aud_ioh, 1031 ICH_GCTRL + sc->sc_modem_offset); 1032 control &= ~ICH_PCM246_MASK; 1033 if (p->channels == 4) { 1034 control |= ICH_PCM4; 1035 } else if (p->channels == 6) { 1036 control |= ICH_PCM6; 1037 } 1038 bus_space_write_4(sc->iot, sc->aud_ioh, 1039 ICH_GCTRL + sc->sc_modem_offset, control); 1040 } 1041 } 1042 1043 return 0; 1044 } 1045 1046 static int 1047 auich_round_blocksize(void *v, int blk, int mode, 1048 const audio_params_t *param) 1049 { 1050 1051 return blk & ~0x3f; /* keep good alignment */ 1052 } 1053 1054 static void 1055 auich_halt_pipe(struct auich_softc *sc, int pipe) 1056 { 1057 int i; 1058 uint32_t status; 1059 1060 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 1061 for (i = 0; i < 100; i++) { 1062 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 1063 if (status & ICH_DCH) 1064 break; 1065 DELAY(1); 1066 } 1067 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 1068 1069 #if AUICH_DEBUG 1070 if (i > 0) 1071 printf("auich_halt_pipe: halt took %d cycles\n", i); 1072 #endif 1073 } 1074 1075 static int 1076 auich_halt_output(void *v) 1077 { 1078 struct auich_softc *sc; 1079 1080 sc = v; 1081 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 1082 1083 auich_halt_pipe(sc, ICH_PCMO); 1084 sc->pcmo.intr = NULL; 1085 1086 return 0; 1087 } 1088 1089 static int 1090 auich_halt_input(void *v) 1091 { 1092 struct auich_softc *sc; 1093 1094 sc = v; 1095 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", sc->sc_dev.dv_xname)); 1096 1097 auich_halt_pipe(sc, ICH_PCMI); 1098 sc->pcmi.intr = NULL; 1099 1100 return 0; 1101 } 1102 1103 static int 1104 auich_getdev(void *v, struct audio_device *adp) 1105 { 1106 struct auich_softc *sc; 1107 1108 sc = v; 1109 *adp = sc->sc_audev; 1110 return 0; 1111 } 1112 1113 static int 1114 auich_set_port(void *v, mixer_ctrl_t *cp) 1115 { 1116 struct auich_softc *sc; 1117 1118 sc = v; 1119 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1120 } 1121 1122 static int 1123 auich_get_port(void *v, mixer_ctrl_t *cp) 1124 { 1125 struct auich_softc *sc; 1126 1127 sc = v; 1128 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1129 } 1130 1131 static int 1132 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1133 { 1134 struct auich_softc *sc; 1135 1136 sc = v; 1137 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1138 } 1139 1140 static void * 1141 auich_allocm(void *v, int direction, size_t size, 1142 struct malloc_type *pool, int flags) 1143 { 1144 struct auich_softc *sc; 1145 struct auich_dma *p; 1146 int error; 1147 1148 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1149 return NULL; 1150 1151 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1152 if (p == NULL) 1153 return NULL; 1154 1155 sc = v; 1156 error = auich_allocmem(sc, size, 0, p); 1157 if (error) { 1158 free(p, pool); 1159 return NULL; 1160 } 1161 1162 p->next = sc->sc_dmas; 1163 sc->sc_dmas = p; 1164 1165 return KERNADDR(p); 1166 } 1167 1168 static void 1169 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1170 { 1171 struct auich_softc *sc; 1172 struct auich_dma *p, **pp; 1173 1174 sc = v; 1175 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1176 if (KERNADDR(p) == ptr) { 1177 auich_freemem(sc, p); 1178 *pp = p->next; 1179 free(p, pool); 1180 return; 1181 } 1182 } 1183 } 1184 1185 static size_t 1186 auich_round_buffersize(void *v, int direction, size_t size) 1187 { 1188 1189 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1190 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1191 1192 return size; 1193 } 1194 1195 static paddr_t 1196 auich_mappage(void *v, void *mem, off_t off, int prot) 1197 { 1198 struct auich_softc *sc; 1199 struct auich_dma *p; 1200 1201 if (off < 0) 1202 return -1; 1203 sc = v; 1204 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1205 continue; 1206 if (!p) 1207 return -1; 1208 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1209 off, prot, BUS_DMA_WAITOK); 1210 } 1211 1212 static int 1213 auich_get_props(void *v) 1214 { 1215 struct auich_softc *sc; 1216 int props; 1217 1218 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1219 sc = v; 1220 /* 1221 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1222 * rate because of aurateconv. Applications can't know what rate the 1223 * device can process in the case of mmap(). 1224 */ 1225 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1226 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1227 props |= AUDIO_PROP_MMAP; 1228 return props; 1229 } 1230 1231 static int 1232 auich_intr(void *v) 1233 { 1234 struct auich_softc *sc; 1235 int ret, gsts; 1236 #ifdef DIAGNOSTIC 1237 int csts; 1238 #endif 1239 1240 sc = v; 1241 1242 if (!device_has_power(&sc->sc_dev)) 1243 return (0); 1244 1245 ret = 0; 1246 #ifdef DIAGNOSTIC 1247 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1248 if (csts & PCI_STATUS_MASTER_ABORT) { 1249 printf("auich_intr: PCI master abort\n"); 1250 } 1251 #endif 1252 1253 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1254 ICH_GSTS + sc->sc_modem_offset); 1255 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1256 1257 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1258 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1259 int sts; 1260 1261 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1262 ICH_PCMO + sc->sc_sts_reg); 1263 DPRINTF(ICH_DEBUG_INTR, 1264 ("auich_intr: osts=0x%x\n", sts)); 1265 1266 if (sts & ICH_FIFOE) 1267 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1268 1269 if (sts & ICH_BCIS) 1270 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1271 1272 /* int ack */ 1273 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1274 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1275 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1276 bus_space_write_4(sc->iot, sc->aud_ioh, 1277 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1278 else 1279 bus_space_write_4(sc->iot, sc->aud_ioh, 1280 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1281 ret++; 1282 } 1283 1284 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1285 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1286 int sts; 1287 1288 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1289 ICH_PCMI + sc->sc_sts_reg); 1290 DPRINTF(ICH_DEBUG_INTR, 1291 ("auich_intr: ists=0x%x\n", sts)); 1292 1293 if (sts & ICH_FIFOE) 1294 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1295 1296 if (sts & ICH_BCIS) 1297 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1298 1299 /* int ack */ 1300 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1301 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1302 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1303 bus_space_write_4(sc->iot, sc->aud_ioh, 1304 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1305 else 1306 bus_space_write_4(sc->iot, sc->aud_ioh, 1307 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1308 ret++; 1309 } 1310 1311 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1312 int sts; 1313 1314 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1315 ICH_MICI + sc->sc_sts_reg); 1316 DPRINTF(ICH_DEBUG_INTR, 1317 ("auich_intr: ists=0x%x\n", sts)); 1318 1319 if (sts & ICH_FIFOE) 1320 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1321 1322 if (sts & ICH_BCIS) 1323 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1324 1325 /* int ack */ 1326 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1327 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1328 bus_space_write_4(sc->iot, sc->aud_ioh, 1329 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1330 ret++; 1331 } 1332 1333 #ifdef AUICH_MODEM_DEBUG 1334 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1335 printf("%s: gsts=0x%x\n", sc->sc_dev.dv_xname, gsts); 1336 /* int ack */ 1337 bus_space_write_4(sc->iot, sc->aud_ioh, 1338 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1339 ret++; 1340 } 1341 #endif 1342 1343 return ret; 1344 } 1345 1346 static void 1347 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1348 { 1349 int blksize, qptr; 1350 struct auich_dmalist *q; 1351 1352 blksize = ring->blksize; 1353 1354 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1355 q = &ring->dmalist[qptr]; 1356 q->base = ring->p; 1357 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1358 1359 ring->p += blksize; 1360 if (ring->p >= ring->end) 1361 ring->p = ring->start; 1362 } 1363 ring->qptr = 0; 1364 1365 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1366 (qptr - 1) & ICH_LVI_MASK); 1367 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1368 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1369 } 1370 1371 static void 1372 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1373 { 1374 int blksize, qptr, nqptr; 1375 struct auich_dmalist *q; 1376 1377 blksize = ring->blksize; 1378 qptr = ring->qptr; 1379 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1380 1381 while (qptr != nqptr) { 1382 q = &ring->dmalist[qptr]; 1383 q->base = ring->p; 1384 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1385 1386 DPRINTF(ICH_DEBUG_INTR, 1387 ("auich_intr: %p, %p = %x @ 0x%x\n", 1388 &ring->dmalist[qptr], q, q->len, q->base)); 1389 1390 ring->p += blksize; 1391 if (ring->p >= ring->end) 1392 ring->p = ring->start; 1393 1394 qptr = (qptr + 1) & ICH_LVI_MASK; 1395 if (ring->intr) 1396 ring->intr(ring->arg); 1397 } 1398 ring->qptr = qptr; 1399 1400 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1401 (qptr - 1) & ICH_LVI_MASK); 1402 } 1403 1404 static int 1405 auich_trigger_output(void *v, void *start, void *end, int blksize, 1406 void (*intr)(void *), void *arg, const audio_params_t *param) 1407 { 1408 struct auich_softc *sc; 1409 struct auich_dma *p; 1410 size_t size; 1411 1412 DPRINTF(ICH_DEBUG_DMA, 1413 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1414 start, end, blksize, intr, arg, param)); 1415 sc = v; 1416 1417 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1418 continue; 1419 if (!p) { 1420 printf("auich_trigger_output: bad addr %p\n", start); 1421 return EINVAL; 1422 } 1423 1424 size = (size_t)((char *)end - (char *)start); 1425 1426 sc->pcmo.intr = intr; 1427 sc->pcmo.arg = arg; 1428 sc->pcmo.start = DMAADDR(p); 1429 sc->pcmo.p = sc->pcmo.start; 1430 sc->pcmo.end = sc->pcmo.start + size; 1431 sc->pcmo.blksize = blksize; 1432 1433 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1434 sc->sc_cddma + ICH_PCMO_OFF(0)); 1435 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1436 1437 return 0; 1438 } 1439 1440 static int 1441 auich_trigger_input(void *v, void *start, void *end, int blksize, 1442 void (*intr)(void *), void *arg, const audio_params_t *param) 1443 { 1444 struct auich_softc *sc; 1445 struct auich_dma *p; 1446 size_t size; 1447 1448 DPRINTF(ICH_DEBUG_DMA, 1449 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1450 start, end, blksize, intr, arg, param)); 1451 sc = v; 1452 1453 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1454 continue; 1455 if (!p) { 1456 printf("auich_trigger_input: bad addr %p\n", start); 1457 return EINVAL; 1458 } 1459 1460 size = (size_t)((char *)end - (char *)start); 1461 1462 sc->pcmi.intr = intr; 1463 sc->pcmi.arg = arg; 1464 sc->pcmi.start = DMAADDR(p); 1465 sc->pcmi.p = sc->pcmi.start; 1466 sc->pcmi.end = sc->pcmi.start + size; 1467 sc->pcmi.blksize = blksize; 1468 1469 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1470 sc->sc_cddma + ICH_PCMI_OFF(0)); 1471 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1472 1473 return 0; 1474 } 1475 1476 static int 1477 auich_powerstate(void *v, int state) 1478 { 1479 return 0; 1480 } 1481 1482 static int 1483 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1484 struct auich_dma *p) 1485 { 1486 int error; 1487 1488 p->size = size; 1489 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1490 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1491 &p->nsegs, BUS_DMA_NOWAIT); 1492 if (error) 1493 return error; 1494 1495 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1496 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1497 if (error) 1498 goto free; 1499 1500 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1501 0, BUS_DMA_NOWAIT, &p->map); 1502 if (error) 1503 goto unmap; 1504 1505 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1506 BUS_DMA_NOWAIT); 1507 if (error) 1508 goto destroy; 1509 return 0; 1510 1511 destroy: 1512 bus_dmamap_destroy(sc->dmat, p->map); 1513 unmap: 1514 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1515 free: 1516 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1517 return error; 1518 } 1519 1520 static int 1521 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1522 { 1523 1524 bus_dmamap_unload(sc->dmat, p->map); 1525 bus_dmamap_destroy(sc->dmat, p->map); 1526 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1527 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1528 return 0; 1529 } 1530 1531 static int 1532 auich_alloc_cdata(struct auich_softc *sc) 1533 { 1534 bus_dma_segment_t seg; 1535 int error, rseg; 1536 1537 /* 1538 * Allocate the control data structure, and create and load the 1539 * DMA map for it. 1540 */ 1541 if ((error = bus_dmamem_alloc(sc->dmat, 1542 sizeof(struct auich_cdata), 1543 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1544 printf("%s: unable to allocate control data, error = %d\n", 1545 sc->sc_dev.dv_xname, error); 1546 goto fail_0; 1547 } 1548 1549 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1550 sizeof(struct auich_cdata), 1551 (void **) &sc->sc_cdata, 1552 sc->sc_dmamap_flags)) != 0) { 1553 printf("%s: unable to map control data, error = %d\n", 1554 sc->sc_dev.dv_xname, error); 1555 goto fail_1; 1556 } 1557 1558 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1559 sizeof(struct auich_cdata), 0, 0, 1560 &sc->sc_cddmamap)) != 0) { 1561 printf("%s: unable to create control data DMA map, " 1562 "error = %d\n", sc->sc_dev.dv_xname, error); 1563 goto fail_2; 1564 } 1565 1566 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1567 sc->sc_cdata, sizeof(struct auich_cdata), 1568 NULL, 0)) != 0) { 1569 printf("%s: unable tp load control data DMA map, " 1570 "error = %d\n", sc->sc_dev.dv_xname, error); 1571 goto fail_3; 1572 } 1573 1574 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1575 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1576 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1577 1578 return 0; 1579 1580 fail_3: 1581 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1582 fail_2: 1583 bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata, 1584 sizeof(struct auich_cdata)); 1585 fail_1: 1586 bus_dmamem_free(sc->dmat, &seg, rseg); 1587 fail_0: 1588 return error; 1589 } 1590 1591 static bool 1592 auich_resume(device_t dv) 1593 { 1594 struct auich_softc *sc = device_private(dv); 1595 pcireg_t v; 1596 1597 if (sc->sc_native_mode) { 1598 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 1599 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 1600 v | ICH_CFG_IOSE); 1601 } 1602 1603 auich_reset_codec(sc); 1604 DELAY(1000); 1605 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1606 1607 return true; 1608 } 1609 1610 /* 1611 * Calibrate card (some boards are overclocked and need scaling) 1612 */ 1613 static void 1614 auich_calibrate(struct auich_softc *sc) 1615 { 1616 struct timeval t1, t2; 1617 uint8_t ociv, nciv; 1618 uint64_t wait_us; 1619 uint32_t actual_48k_rate, bytes, ac97rate; 1620 void *temp_buffer; 1621 struct auich_dma *p; 1622 u_int rate; 1623 1624 /* 1625 * Grab audio from input for fixed interval and compare how 1626 * much we actually get with what we expect. Interval needs 1627 * to be sufficiently short that no interrupts are 1628 * generated. 1629 */ 1630 1631 /* Force the codec to a known state first. */ 1632 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1633 rate = sc->sc_ac97_clock = 48000; 1634 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1635 &rate); 1636 1637 /* Setup a buffer */ 1638 bytes = 64000; 1639 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1640 1641 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1642 continue; 1643 if (p == NULL) { 1644 printf("auich_calibrate: bad address %p\n", temp_buffer); 1645 return; 1646 } 1647 sc->pcmi.dmalist[0].base = DMAADDR(p); 1648 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1649 1650 /* 1651 * our data format is stereo, 16 bit so each sample is 4 bytes. 1652 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1653 * we're going to start recording with interrupts disabled and measure 1654 * the time taken for one block to complete. we know the block size, 1655 * we know the time in microseconds, we calculate the sample rate: 1656 * 1657 * actual_rate [bps] = bytes / (time [s] * 4) 1658 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1659 * actual_rate [Hz] = (bytes * 250000) / time [us] 1660 */ 1661 1662 /* prepare */ 1663 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1664 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1665 sc->sc_cddma + ICH_PCMI_OFF(0)); 1666 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1667 (0 - 1) & ICH_LVI_MASK); 1668 1669 /* start */ 1670 microtime(&t1); 1671 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1672 1673 /* wait */ 1674 nciv = ociv; 1675 do { 1676 microtime(&t2); 1677 if (t2.tv_sec - t1.tv_sec > 1) 1678 break; 1679 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1680 ICH_PCMI + ICH_CIV); 1681 } while (nciv == ociv); 1682 microtime(&t2); 1683 1684 /* stop */ 1685 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1686 1687 /* reset */ 1688 DELAY(100); 1689 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1690 1691 /* turn time delta into us */ 1692 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1693 1694 auich_freem(sc, temp_buffer, M_DEVBUF); 1695 1696 if (nciv == ociv) { 1697 printf("%s: ac97 link rate calibration timed out after %" 1698 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1699 return; 1700 } 1701 1702 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1703 1704 if (actual_48k_rate < 50000) 1705 ac97rate = 48000; 1706 else 1707 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1708 1709 printf("%s: measured ac97 link rate at %d Hz", 1710 sc->sc_dev.dv_xname, actual_48k_rate); 1711 if (ac97rate != actual_48k_rate) 1712 printf(", will use %d Hz", ac97rate); 1713 printf("\n"); 1714 1715 sc->sc_ac97_clock = ac97rate; 1716 } 1717 1718 static void 1719 auich_clear_cas(struct auich_softc *sc) 1720 { 1721 /* Clear the codec access semaphore */ 1722 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1723 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1724 1725 return; 1726 } 1727
Indexes created Fri Sep 26 20:09:58 GMT 2025