auich.c revision 1.123
1 /* $NetBSD: auich.c,v 1.123 2008/01/06 12:56:20 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.123 2008/01/06 12:56:20 kent Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <sys/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 void *addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 pci_intr_handle_t intrh; 187 188 struct ac97_codec_if *codec_if; 189 struct ac97_host_if host_if; 190 int sc_codecnum; 191 int sc_codectype; 192 enum ac97_host_flags sc_codecflags; 193 bool sc_spdif; 194 195 /* DMA scatter-gather lists. */ 196 bus_dmamap_t sc_cddmamap; 197 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 198 199 struct auich_cdata *sc_cdata; 200 201 struct auich_ring { 202 int qptr; 203 struct auich_dmalist *dmalist; 204 205 uint32_t start, p, end; 206 int blksize; 207 208 void (*intr)(void *); 209 void *arg; 210 } pcmo, pcmi, mici; 211 212 struct auich_dma *sc_dmas; 213 214 /* SiS 7012 hack */ 215 int sc_sample_shift; 216 int sc_sts_reg; 217 /* 440MX workaround */ 218 int sc_dmamap_flags; 219 /* Native mode? */ 220 int sc_native_mode; 221 222 /* sysctl */ 223 struct sysctllog *sc_log; 224 uint32_t sc_ac97_clock; 225 int sc_ac97_clock_mib; 226 227 int sc_modem_offset; 228 229 #define AUICH_AUDIO_NFORMATS 3 230 #define AUICH_MODEM_NFORMATS 1 231 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 232 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 233 struct audio_encoding_set *sc_encodings; 234 struct audio_encoding_set *sc_spdif_encodings; 235 }; 236 237 /* Debug */ 238 #ifdef AUICH_DEBUG 239 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 240 int auich_debug = 0xfffe; 241 #define ICH_DEBUG_CODECIO 0x0001 242 #define ICH_DEBUG_DMA 0x0002 243 #define ICH_DEBUG_INTR 0x0004 244 #else 245 #define DPRINTF(x,y) /* nothing */ 246 #endif 247 248 static int auich_match(struct device *, struct cfdata *, void *); 249 static void auich_attach(struct device *, struct device *, void *); 250 static int auich_detach(struct device *, int); 251 static int auich_activate(struct device *, enum devact); 252 static int auich_intr(void *); 253 254 CFATTACH_DECL(auich, sizeof(struct auich_softc), 255 auich_match, auich_attach, auich_detach, auich_activate); 256 257 static int auich_open(void *, int); 258 static void auich_close(void *); 259 static int auich_query_encoding(void *, struct audio_encoding *); 260 static int auich_set_params(void *, int, int, audio_params_t *, 261 audio_params_t *, stream_filter_list_t *, 262 stream_filter_list_t *); 263 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 264 static void auich_halt_pipe(struct auich_softc *, int); 265 static int auich_halt_output(void *); 266 static int auich_halt_input(void *); 267 static int auich_getdev(void *, struct audio_device *); 268 static int auich_set_port(void *, mixer_ctrl_t *); 269 static int auich_get_port(void *, mixer_ctrl_t *); 270 static int auich_query_devinfo(void *, mixer_devinfo_t *); 271 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 272 static void auich_freem(void *, void *, struct malloc_type *); 273 static size_t auich_round_buffersize(void *, int, size_t); 274 static paddr_t auich_mappage(void *, void *, off_t, int); 275 static int auich_get_props(void *); 276 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 277 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 278 static int auich_trigger_output(void *, void *, void *, int, 279 void (*)(void *), void *, const audio_params_t *); 280 static int auich_trigger_input(void *, void *, void *, int, 281 void (*)(void *), void *, const audio_params_t *); 282 static int auich_powerstate(void *, int); 283 284 static int auich_alloc_cdata(struct auich_softc *); 285 286 static int auich_allocmem(struct auich_softc *, size_t, size_t, 287 struct auich_dma *); 288 static int auich_freemem(struct auich_softc *, struct auich_dma *); 289 290 static bool auich_resume(device_t); 291 static int auich_set_rate(struct auich_softc *, int, u_long); 292 static int auich_sysctl_verify(SYSCTLFN_ARGS); 293 static void auich_finish_attach(struct device *); 294 static void auich_calibrate(struct auich_softc *); 295 static void auich_clear_cas(struct auich_softc *); 296 297 static int auich_attach_codec(void *, struct ac97_codec_if *); 298 static int auich_read_codec(void *, uint8_t, uint16_t *); 299 static int auich_write_codec(void *, uint8_t, uint16_t); 300 static int auich_reset_codec(void *); 301 static enum ac97_host_flags auich_flags_codec(void *); 302 static void auich_spdif_event(void *, bool); 303 304 static const struct audio_hw_if auich_hw_if = { 305 auich_open, 306 auich_close, 307 NULL, /* drain */ 308 auich_query_encoding, 309 auich_set_params, 310 auich_round_blocksize, 311 NULL, /* commit_setting */ 312 NULL, /* init_output */ 313 NULL, /* init_input */ 314 NULL, /* start_output */ 315 NULL, /* start_input */ 316 auich_halt_output, 317 auich_halt_input, 318 NULL, /* speaker_ctl */ 319 auich_getdev, 320 NULL, /* getfd */ 321 auich_set_port, 322 auich_get_port, 323 auich_query_devinfo, 324 auich_allocm, 325 auich_freem, 326 auich_round_buffersize, 327 auich_mappage, 328 auich_get_props, 329 auich_trigger_output, 330 auich_trigger_input, 331 NULL, /* dev_ioctl */ 332 auich_powerstate, 333 }; 334 335 #define AUICH_FORMATS_1CH 0 336 #define AUICH_FORMATS_4CH 1 337 #define AUICH_FORMATS_6CH 2 338 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 339 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 340 2, AUFMT_STEREO, 0, {8000, 48000}}, 341 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 342 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 343 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 344 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 345 }; 346 347 #define AUICH_SPDIF_NFORMATS 1 348 static const struct audio_format auich_spdif_formats[AUICH_SPDIF_NFORMATS] = { 349 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 350 2, AUFMT_STEREO, 1, {48000}}, 351 }; 352 353 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 354 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 355 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 356 }; 357 358 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 359 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 360 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 361 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 362 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 363 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 364 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 365 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 366 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 367 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 368 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 369 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 370 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 371 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 372 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 373 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 374 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 375 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 376 #define PCIID_NFORCE430 PCI_ID_CODE0(NVIDIA, NFORCE430_AC) 377 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 378 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 379 380 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 381 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 382 #define PCIID_ICH6MODEM PCI_ID_CODE0(INTEL, 82801FB_ACM) 383 384 struct auich_devtype { 385 pcireg_t id; 386 const char *name; 387 const char *shortname; /* must be less than 11 characters */ 388 }; 389 390 static const struct auich_devtype auich_audio_devices[] = { 391 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 392 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 393 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 394 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 395 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 396 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 397 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 398 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 399 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 400 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 401 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 402 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 403 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 404 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 405 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 406 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 407 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 408 { PCIID_NFORCE430, "nForce430 (MCP51) AC-97 Audio", "nForce430" }, 409 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 410 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 411 { 0, NULL, NULL }, 412 }; 413 414 static const struct auich_devtype auich_modem_devices[] = { 415 #ifdef AUICH_ATTACH_MODEM 416 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 417 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 418 { PCIID_ICH6MODEM, "i82801FB (ICH6) AC-97 Modem", "ICH6MODEM" }, 419 #endif 420 { 0, NULL, NULL }, 421 }; 422 423 static const struct auich_devtype * 424 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 425 { 426 const struct auich_devtype *d; 427 428 for (d = auich_devices; d->name != NULL; d++) { 429 if (pa->pa_id == d->id) 430 return d; 431 } 432 433 return NULL; 434 } 435 436 static int 437 auich_match(struct device *parent, struct cfdata *match, 438 void *aux) 439 { 440 struct pci_attach_args *pa; 441 442 pa = aux; 443 if (auich_lookup(pa, auich_audio_devices) != NULL) 444 return 1; 445 if (auich_lookup(pa, auich_modem_devices) != NULL) 446 return 1; 447 448 return 0; 449 } 450 451 static void 452 auich_attach(struct device *parent, struct device *self, void *aux) 453 { 454 struct auich_softc *sc; 455 struct pci_attach_args *pa; 456 pcireg_t v, subdev; 457 const char *intrstr; 458 const struct auich_devtype *d; 459 const struct sysctlnode *node, *node_ac97clock; 460 int err, node_mib, i; 461 462 sc = (struct auich_softc *)self; 463 pa = aux; 464 465 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 466 sc->sc_modem_offset = 0x10; 467 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 468 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 469 sc->sc_modem_offset = 0; 470 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 471 } else 472 panic("auich_attach: impossible"); 473 474 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 475 aprint_naive(": Audio controller\n"); 476 else 477 aprint_naive(": Modem controller\n"); 478 479 sc->sc_pc = pa->pa_pc; 480 sc->sc_pt = pa->pa_tag; 481 482 aprint_normal(": %s\n", d->name); 483 484 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 485 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 486 || d->id == PCIID_ICH4MODEM) { 487 sc->sc_native_mode = 1; 488 /* 489 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 490 */ 491 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 492 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 493 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 494 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 495 v | ICH_CFG_IOSE); 496 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 497 0, &sc->iot, &sc->mix_ioh, NULL, 498 &sc->mix_size)) { 499 aprint_error("%s: can't map codec i/o space\n", 500 sc->sc_dev.dv_xname); 501 return; 502 } 503 } 504 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 505 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 506 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 507 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 508 v | ICH_CFG_IOSE); 509 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 510 0, &sc->iot, &sc->aud_ioh, NULL, 511 &sc->aud_size)) { 512 aprint_error("%s: can't map device i/o space\n", 513 sc->sc_dev.dv_xname); 514 return; 515 } 516 } 517 } else { 518 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 519 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 520 aprint_error("%s: can't map codec i/o space\n", 521 sc->sc_dev.dv_xname); 522 return; 523 } 524 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 525 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 526 aprint_error("%s: can't map device i/o space\n", 527 sc->sc_dev.dv_xname); 528 return; 529 } 530 } 531 sc->dmat = pa->pa_dmat; 532 533 /* enable bus mastering */ 534 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 535 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 536 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 537 538 /* Map and establish the interrupt. */ 539 if (pci_intr_map(pa, &sc->intrh)) { 540 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 541 return; 542 } 543 intrstr = pci_intr_string(pa->pa_pc, sc->intrh); 544 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO, 545 auich_intr, sc); 546 if (sc->sc_ih == NULL) { 547 aprint_error("%s: can't establish interrupt", 548 sc->sc_dev.dv_xname); 549 if (intrstr != NULL) 550 aprint_normal(" at %s", intrstr); 551 aprint_normal("\n"); 552 return; 553 } 554 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 555 556 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 557 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 558 "0x%02x", PCI_REVISION(pa->pa_class)); 559 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 560 561 /* SiS 7012 needs special handling */ 562 if (d->id == PCIID_SIS7012) { 563 sc->sc_sts_reg = ICH_PICB; 564 sc->sc_sample_shift = 0; 565 /* Un-mute output. From Linux. */ 566 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 567 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 568 ICH_SIS_CTL_UNMUTE); 569 } else { 570 sc->sc_sts_reg = ICH_STS; 571 sc->sc_sample_shift = 1; 572 } 573 574 /* Workaround for a 440MX B-stepping erratum */ 575 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 576 if (d->id == PCIID_440MX) { 577 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 578 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 579 } 580 581 /* Set up DMA lists. */ 582 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 583 auich_alloc_cdata(sc); 584 585 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 586 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 587 588 /* Modem codecs are always the secondary codec on ICH */ 589 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 590 591 sc->host_if.arg = sc; 592 sc->host_if.attach = auich_attach_codec; 593 sc->host_if.read = auich_read_codec; 594 sc->host_if.write = auich_write_codec; 595 sc->host_if.reset = auich_reset_codec; 596 sc->host_if.flags = auich_flags_codec; 597 sc->host_if.spdif_event = auich_spdif_event; 598 599 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 600 switch (subdev) { 601 case 0x202f161f: /* Gateway 7326GZ */ 602 case 0x203a161f: /* Gateway 4028GZ */ 603 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 604 case 0x8144104d: /* Sony VAIO PCG-TR* */ 605 case 0x8197104d: /* Sony S1XP */ 606 case 0x81c0104d: /* Sony VAIO type T */ 607 case 0x81c5104d: /* Sony VAIO VGN-B1XP */ 608 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP; 609 break; 610 default: 611 sc->sc_codecflags = 0; 612 break; 613 } 614 615 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 616 return; 617 sc->codec_if->vtbl->unlock(sc->codec_if); 618 619 /* setup audio_format */ 620 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 621 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 622 if (!AC97_IS_4CH(sc->codec_if)) 623 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 624 if (!AC97_IS_6CH(sc->codec_if)) 625 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 626 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 627 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 628 sc->sc_audio_formats[i].frequency_type = 1; 629 sc->sc_audio_formats[i].frequency[0] = 48000; 630 } 631 } 632 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 633 &sc->sc_encodings)) 634 return; 635 if (0 != auconv_create_encodings(auich_spdif_formats, AUICH_SPDIF_NFORMATS, 636 &sc->sc_spdif_encodings)) 637 return; 638 } else { 639 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 640 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 641 &sc->sc_encodings)) 642 return; 643 } 644 645 /* Watch for power change */ 646 if (!pmf_device_register(self, NULL, auich_resume)) 647 aprint_error_dev(self, "couldn't establish power handler\n"); 648 649 config_interrupts(self, auich_finish_attach); 650 651 /* sysctl setup */ 652 if (AC97_IS_FIXED_RATE(sc->codec_if) && 653 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 654 return; 655 656 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 657 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 658 CTL_HW, CTL_EOL); 659 if (err != 0) 660 goto sysctl_err; 661 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 662 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 663 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 664 if (err != 0) 665 goto sysctl_err; 666 node_mib = node->sysctl_num; 667 668 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 669 /* passing the sc address instead of &sc->sc_ac97_clock */ 670 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 671 CTLFLAG_READWRITE, 672 CTLTYPE_INT, "ac97rate", 673 SYSCTL_DESCR("AC'97 codec link rate"), 674 auich_sysctl_verify, 0, sc, 0, 675 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 676 if (err != 0) 677 goto sysctl_err; 678 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 679 } 680 681 return; 682 683 sysctl_err: 684 printf("%s: failed to add sysctl nodes. (%d)\n", 685 sc->sc_dev.dv_xname, err); 686 return; /* failure of sysctl is not fatal. */ 687 } 688 689 static int 690 auich_activate(struct device *self, enum devact act) 691 { 692 struct auich_softc *sc; 693 int ret; 694 695 sc = (struct auich_softc *)self; 696 ret = 0; 697 switch (act) { 698 case DVACT_ACTIVATE: 699 return EOPNOTSUPP; 700 case DVACT_DEACTIVATE: 701 if (sc->sc_audiodev != NULL) 702 ret = config_deactivate(sc->sc_audiodev); 703 return ret; 704 } 705 return EOPNOTSUPP; 706 } 707 708 static int 709 auich_detach(struct device *self, int flags) 710 { 711 struct auich_softc *sc; 712 713 sc = (struct auich_softc *)self; 714 715 /* audio */ 716 if (sc->sc_audiodev != NULL) 717 config_detach(sc->sc_audiodev, flags); 718 719 /* sysctl */ 720 sysctl_teardown(&sc->sc_log); 721 722 /* audio_encoding_set */ 723 auconv_delete_encodings(sc->sc_encodings); 724 auconv_delete_encodings(sc->sc_spdif_encodings); 725 726 /* ac97 */ 727 if (sc->codec_if != NULL) 728 sc->codec_if->vtbl->detach(sc->codec_if); 729 730 /* PCI */ 731 if (sc->sc_ih != NULL) 732 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 733 if (sc->mix_size != 0) 734 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 735 if (sc->aud_size != 0) 736 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 737 return 0; 738 } 739 740 static int 741 auich_sysctl_verify(SYSCTLFN_ARGS) 742 { 743 int error, tmp; 744 struct sysctlnode node; 745 struct auich_softc *sc; 746 747 node = *rnode; 748 sc = rnode->sysctl_data; 749 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 750 tmp = sc->sc_ac97_clock; 751 node.sysctl_data = &tmp; 752 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 753 if (error || newp == NULL) 754 return error; 755 756 if (tmp < 48000 || tmp > 96000) 757 return EINVAL; 758 sc->sc_ac97_clock = tmp; 759 } 760 761 return 0; 762 } 763 764 static void 765 auich_finish_attach(struct device *self) 766 { 767 struct auich_softc *sc; 768 769 sc = (void *)self; 770 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 771 auich_calibrate(sc); 772 773 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 774 775 return; 776 } 777 778 #define ICH_CODECIO_INTERVAL 10 779 static int 780 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 781 { 782 struct auich_softc *sc; 783 int i; 784 uint32_t status; 785 786 sc = v; 787 /* wait for an access semaphore */ 788 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 789 bus_space_read_1(sc->iot, sc->aud_ioh, 790 ICH_CAS + sc->sc_modem_offset) & 1; 791 DELAY(ICH_CODECIO_INTERVAL)); 792 793 if (i > 0) { 794 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 795 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 796 DPRINTF(ICH_DEBUG_CODECIO, 797 ("auich_read_codec(%x, %x)\n", reg, *val)); 798 status = bus_space_read_4(sc->iot, sc->aud_ioh, 799 ICH_GSTS + sc->sc_modem_offset); 800 if (status & ICH_RCS) { 801 bus_space_write_4(sc->iot, sc->aud_ioh, 802 ICH_GSTS + sc->sc_modem_offset, 803 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 804 *val = 0xffff; 805 DPRINTF(ICH_DEBUG_CODECIO, 806 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 807 if (reg == AC97_REG_GPIO_STATUS) 808 auich_clear_cas(sc); 809 return -1; 810 } 811 if (reg == AC97_REG_GPIO_STATUS) 812 auich_clear_cas(sc); 813 return 0; 814 } else { 815 aprint_normal("%s: read_codec timeout\n", sc->sc_dev.dv_xname); 816 if (reg == AC97_REG_GPIO_STATUS) 817 auich_clear_cas(sc); 818 return -1; 819 } 820 } 821 822 static int 823 auich_write_codec(void *v, uint8_t reg, uint16_t val) 824 { 825 struct auich_softc *sc; 826 int i; 827 828 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 829 sc = v; 830 /* wait for an access semaphore */ 831 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 832 bus_space_read_1(sc->iot, sc->aud_ioh, 833 ICH_CAS + sc->sc_modem_offset) & 1; 834 DELAY(ICH_CODECIO_INTERVAL)); 835 836 if (i > 0) { 837 bus_space_write_2(sc->iot, sc->mix_ioh, 838 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 839 return 0; 840 } else { 841 aprint_normal("%s: write_codec timeout\n", sc->sc_dev.dv_xname); 842 return -1; 843 } 844 } 845 846 static int 847 auich_attach_codec(void *v, struct ac97_codec_if *cif) 848 { 849 struct auich_softc *sc; 850 851 sc = v; 852 sc->codec_if = cif; 853 854 return 0; 855 } 856 857 static int 858 auich_reset_codec(void *v) 859 { 860 struct auich_softc *sc; 861 int i; 862 uint32_t control, status; 863 864 sc = v; 865 control = bus_space_read_4(sc->iot, sc->aud_ioh, 866 ICH_GCTRL + sc->sc_modem_offset); 867 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 868 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 869 } else { 870 control &= ~ICH_ACLSO; 871 control |= ICH_GIE; 872 } 873 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 874 bus_space_write_4(sc->iot, sc->aud_ioh, 875 ICH_GCTRL + sc->sc_modem_offset, control); 876 877 for (i = 500000; i >= 0; i--) { 878 status = bus_space_read_4(sc->iot, sc->aud_ioh, 879 ICH_GSTS + sc->sc_modem_offset); 880 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 881 break; 882 DELAY(1); 883 } 884 if (i <= 0) { 885 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 886 return ETIMEDOUT; 887 } 888 #ifdef AUICH_DEBUG 889 if (status & ICH_SCR) 890 printf("%s: The 2nd codec is ready.\n", 891 sc->sc_dev.dv_xname); 892 if (status & ICH_S2CR) 893 printf("%s: The 3rd codec is ready.\n", 894 sc->sc_dev.dv_xname); 895 #endif 896 return 0; 897 } 898 899 static enum ac97_host_flags 900 auich_flags_codec(void *v) 901 { 902 struct auich_softc *sc = v; 903 return sc->sc_codecflags; 904 } 905 906 static void 907 auich_spdif_event(void *addr, bool flag) 908 { 909 struct auich_softc *sc; 910 911 sc = addr; 912 sc->sc_spdif = flag; 913 } 914 915 static int 916 auich_open(void *addr, int flags) 917 { 918 struct auich_softc *sc; 919 920 sc = (struct auich_softc *)addr; 921 sc->codec_if->vtbl->lock(sc->codec_if); 922 return 0; 923 } 924 925 static void 926 auich_close(void *addr) 927 { 928 struct auich_softc *sc; 929 930 sc = (struct auich_softc *)addr; 931 sc->codec_if->vtbl->unlock(sc->codec_if); 932 } 933 934 static int 935 auich_query_encoding(void *v, struct audio_encoding *aep) 936 { 937 struct auich_softc *sc; 938 939 sc = (struct auich_softc *)v; 940 return auconv_query_encoding( 941 sc->sc_spdif ? sc->sc_spdif_encodings : sc->sc_encodings, aep); 942 } 943 944 static int 945 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 946 { 947 int ret; 948 u_int ratetmp; 949 950 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 951 ratetmp = srate; 952 if (mode == AUMODE_RECORD) 953 return sc->codec_if->vtbl->set_rate(sc->codec_if, 954 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 955 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 956 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 957 if (ret) 958 return ret; 959 ratetmp = srate; 960 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 961 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 962 if (ret) 963 return ret; 964 ratetmp = srate; 965 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 966 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 967 return ret; 968 } 969 970 static int 971 auich_set_params(void *v, int setmode, int usemode, 972 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 973 stream_filter_list_t *rfil) 974 { 975 struct auich_softc *sc; 976 audio_params_t *p; 977 stream_filter_list_t *fil; 978 int mode, index; 979 uint32_t control; 980 981 sc = v; 982 for (mode = AUMODE_RECORD; mode != -1; 983 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 984 if ((setmode & mode) == 0) 985 continue; 986 987 p = mode == AUMODE_PLAY ? play : rec; 988 fil = mode == AUMODE_PLAY ? pfil : rfil; 989 if (p == NULL) 990 continue; 991 992 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 993 if (p->sample_rate < 8000 || 994 p->sample_rate > 48000) 995 return EINVAL; 996 997 if (!sc->sc_spdif) 998 index = auconv_set_converter(sc->sc_audio_formats, 999 AUICH_AUDIO_NFORMATS, mode, p, TRUE, fil); 1000 else 1001 index = auconv_set_converter(auich_spdif_formats, 1002 AUICH_SPDIF_NFORMATS, mode, p, TRUE, fil); 1003 } else { 1004 if (p->sample_rate != 8000 && p->sample_rate != 16000) 1005 return EINVAL; 1006 index = auconv_set_converter(sc->sc_modem_formats, 1007 AUICH_MODEM_NFORMATS, mode, p, TRUE, fil); 1008 } 1009 if (index < 0) 1010 return EINVAL; 1011 if (fil->req_size > 0) 1012 p = &fil->filters[0].param; 1013 /* p represents HW encoding */ 1014 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1015 if (sc->sc_audio_formats[index].frequency_type != 1 1016 && auich_set_rate(sc, mode, p->sample_rate)) 1017 return EINVAL; 1018 } else { 1019 if (sc->sc_modem_formats[index].frequency_type != 1 1020 && auich_set_rate(sc, mode, p->sample_rate)) 1021 return EINVAL; 1022 auich_write_codec(sc, AC97_REG_LINE1_RATE, 1023 p->sample_rate); 1024 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 1025 } 1026 if (mode == AUMODE_PLAY && 1027 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1028 control = bus_space_read_4(sc->iot, sc->aud_ioh, 1029 ICH_GCTRL + sc->sc_modem_offset); 1030 control &= ~ICH_PCM246_MASK; 1031 if (p->channels == 4) { 1032 control |= ICH_PCM4; 1033 } else if (p->channels == 6) { 1034 control |= ICH_PCM6; 1035 } 1036 bus_space_write_4(sc->iot, sc->aud_ioh, 1037 ICH_GCTRL + sc->sc_modem_offset, control); 1038 } 1039 } 1040 1041 return 0; 1042 } 1043 1044 static int 1045 auich_round_blocksize(void *v, int blk, int mode, 1046 const audio_params_t *param) 1047 { 1048 1049 return blk & ~0x3f; /* keep good alignment */ 1050 } 1051 1052 static void 1053 auich_halt_pipe(struct auich_softc *sc, int pipe) 1054 { 1055 int i; 1056 uint32_t status; 1057 1058 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 1059 for (i = 0; i < 100; i++) { 1060 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 1061 if (status & ICH_DCH) 1062 break; 1063 DELAY(1); 1064 } 1065 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 1066 1067 #if AUICH_DEBUG 1068 if (i > 0) 1069 printf("auich_halt_pipe: halt took %d cycles\n", i); 1070 #endif 1071 } 1072 1073 static int 1074 auich_halt_output(void *v) 1075 { 1076 struct auich_softc *sc; 1077 1078 sc = v; 1079 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 1080 1081 auich_halt_pipe(sc, ICH_PCMO); 1082 sc->pcmo.intr = NULL; 1083 1084 return 0; 1085 } 1086 1087 static int 1088 auich_halt_input(void *v) 1089 { 1090 struct auich_softc *sc; 1091 1092 sc = v; 1093 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", sc->sc_dev.dv_xname)); 1094 1095 auich_halt_pipe(sc, ICH_PCMI); 1096 sc->pcmi.intr = NULL; 1097 1098 return 0; 1099 } 1100 1101 static int 1102 auich_getdev(void *v, struct audio_device *adp) 1103 { 1104 struct auich_softc *sc; 1105 1106 sc = v; 1107 *adp = sc->sc_audev; 1108 return 0; 1109 } 1110 1111 static int 1112 auich_set_port(void *v, mixer_ctrl_t *cp) 1113 { 1114 struct auich_softc *sc; 1115 1116 sc = v; 1117 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1118 } 1119 1120 static int 1121 auich_get_port(void *v, mixer_ctrl_t *cp) 1122 { 1123 struct auich_softc *sc; 1124 1125 sc = v; 1126 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1127 } 1128 1129 static int 1130 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1131 { 1132 struct auich_softc *sc; 1133 1134 sc = v; 1135 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1136 } 1137 1138 static void * 1139 auich_allocm(void *v, int direction, size_t size, 1140 struct malloc_type *pool, int flags) 1141 { 1142 struct auich_softc *sc; 1143 struct auich_dma *p; 1144 int error; 1145 1146 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1147 return NULL; 1148 1149 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1150 if (p == NULL) 1151 return NULL; 1152 1153 sc = v; 1154 error = auich_allocmem(sc, size, 0, p); 1155 if (error) { 1156 free(p, pool); 1157 return NULL; 1158 } 1159 1160 p->next = sc->sc_dmas; 1161 sc->sc_dmas = p; 1162 1163 return KERNADDR(p); 1164 } 1165 1166 static void 1167 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1168 { 1169 struct auich_softc *sc; 1170 struct auich_dma *p, **pp; 1171 1172 sc = v; 1173 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1174 if (KERNADDR(p) == ptr) { 1175 auich_freemem(sc, p); 1176 *pp = p->next; 1177 free(p, pool); 1178 return; 1179 } 1180 } 1181 } 1182 1183 static size_t 1184 auich_round_buffersize(void *v, int direction, size_t size) 1185 { 1186 1187 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1188 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1189 1190 return size; 1191 } 1192 1193 static paddr_t 1194 auich_mappage(void *v, void *mem, off_t off, int prot) 1195 { 1196 struct auich_softc *sc; 1197 struct auich_dma *p; 1198 1199 if (off < 0) 1200 return -1; 1201 sc = v; 1202 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1203 continue; 1204 if (!p) 1205 return -1; 1206 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1207 off, prot, BUS_DMA_WAITOK); 1208 } 1209 1210 static int 1211 auich_get_props(void *v) 1212 { 1213 struct auich_softc *sc; 1214 int props; 1215 1216 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1217 sc = v; 1218 /* 1219 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1220 * rate because of aurateconv. Applications can't know what rate the 1221 * device can process in the case of mmap(). 1222 */ 1223 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1224 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1225 props |= AUDIO_PROP_MMAP; 1226 return props; 1227 } 1228 1229 static int 1230 auich_intr(void *v) 1231 { 1232 struct auich_softc *sc; 1233 int ret, gsts; 1234 #ifdef DIAGNOSTIC 1235 int csts; 1236 #endif 1237 1238 sc = v; 1239 1240 if (!device_has_power(&sc->sc_dev)) 1241 return (0); 1242 1243 ret = 0; 1244 #ifdef DIAGNOSTIC 1245 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1246 if (csts & PCI_STATUS_MASTER_ABORT) { 1247 printf("auich_intr: PCI master abort\n"); 1248 } 1249 #endif 1250 1251 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1252 ICH_GSTS + sc->sc_modem_offset); 1253 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1254 1255 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1256 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1257 int sts; 1258 1259 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1260 ICH_PCMO + sc->sc_sts_reg); 1261 DPRINTF(ICH_DEBUG_INTR, 1262 ("auich_intr: osts=0x%x\n", sts)); 1263 1264 if (sts & ICH_FIFOE) 1265 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1266 1267 if (sts & ICH_BCIS) 1268 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1269 1270 /* int ack */ 1271 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1272 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1273 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1274 bus_space_write_4(sc->iot, sc->aud_ioh, 1275 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1276 else 1277 bus_space_write_4(sc->iot, sc->aud_ioh, 1278 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1279 ret++; 1280 } 1281 1282 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1283 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1284 int sts; 1285 1286 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1287 ICH_PCMI + sc->sc_sts_reg); 1288 DPRINTF(ICH_DEBUG_INTR, 1289 ("auich_intr: ists=0x%x\n", sts)); 1290 1291 if (sts & ICH_FIFOE) 1292 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1293 1294 if (sts & ICH_BCIS) 1295 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1296 1297 /* int ack */ 1298 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1299 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1300 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1301 bus_space_write_4(sc->iot, sc->aud_ioh, 1302 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1303 else 1304 bus_space_write_4(sc->iot, sc->aud_ioh, 1305 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1306 ret++; 1307 } 1308 1309 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1310 int sts; 1311 1312 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1313 ICH_MICI + sc->sc_sts_reg); 1314 DPRINTF(ICH_DEBUG_INTR, 1315 ("auich_intr: ists=0x%x\n", sts)); 1316 1317 if (sts & ICH_FIFOE) 1318 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1319 1320 if (sts & ICH_BCIS) 1321 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1322 1323 /* int ack */ 1324 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1325 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1326 bus_space_write_4(sc->iot, sc->aud_ioh, 1327 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1328 ret++; 1329 } 1330 1331 #ifdef AUICH_MODEM_DEBUG 1332 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1333 printf("%s: gsts=0x%x\n", sc->sc_dev.dv_xname, gsts); 1334 /* int ack */ 1335 bus_space_write_4(sc->iot, sc->aud_ioh, 1336 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1337 ret++; 1338 } 1339 #endif 1340 1341 return ret; 1342 } 1343 1344 static void 1345 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1346 { 1347 int blksize, qptr; 1348 struct auich_dmalist *q; 1349 1350 blksize = ring->blksize; 1351 1352 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1353 q = &ring->dmalist[qptr]; 1354 q->base = ring->p; 1355 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1356 1357 ring->p += blksize; 1358 if (ring->p >= ring->end) 1359 ring->p = ring->start; 1360 } 1361 ring->qptr = 0; 1362 1363 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1364 (qptr - 1) & ICH_LVI_MASK); 1365 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1366 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1367 } 1368 1369 static void 1370 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1371 { 1372 int blksize, qptr, nqptr; 1373 struct auich_dmalist *q; 1374 1375 blksize = ring->blksize; 1376 qptr = ring->qptr; 1377 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1378 1379 while (qptr != nqptr) { 1380 q = &ring->dmalist[qptr]; 1381 q->base = ring->p; 1382 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1383 1384 DPRINTF(ICH_DEBUG_INTR, 1385 ("auich_intr: %p, %p = %x @ 0x%x\n", 1386 &ring->dmalist[qptr], q, q->len, q->base)); 1387 1388 ring->p += blksize; 1389 if (ring->p >= ring->end) 1390 ring->p = ring->start; 1391 1392 qptr = (qptr + 1) & ICH_LVI_MASK; 1393 if (ring->intr) 1394 ring->intr(ring->arg); 1395 } 1396 ring->qptr = qptr; 1397 1398 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1399 (qptr - 1) & ICH_LVI_MASK); 1400 } 1401 1402 static int 1403 auich_trigger_output(void *v, void *start, void *end, int blksize, 1404 void (*intr)(void *), void *arg, const audio_params_t *param) 1405 { 1406 struct auich_softc *sc; 1407 struct auich_dma *p; 1408 size_t size; 1409 1410 DPRINTF(ICH_DEBUG_DMA, 1411 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1412 start, end, blksize, intr, arg, param)); 1413 sc = v; 1414 1415 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1416 continue; 1417 if (!p) { 1418 printf("auich_trigger_output: bad addr %p\n", start); 1419 return EINVAL; 1420 } 1421 1422 size = (size_t)((char *)end - (char *)start); 1423 1424 sc->pcmo.intr = intr; 1425 sc->pcmo.arg = arg; 1426 sc->pcmo.start = DMAADDR(p); 1427 sc->pcmo.p = sc->pcmo.start; 1428 sc->pcmo.end = sc->pcmo.start + size; 1429 sc->pcmo.blksize = blksize; 1430 1431 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1432 sc->sc_cddma + ICH_PCMO_OFF(0)); 1433 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1434 1435 return 0; 1436 } 1437 1438 static int 1439 auich_trigger_input(void *v, void *start, void *end, int blksize, 1440 void (*intr)(void *), void *arg, const audio_params_t *param) 1441 { 1442 struct auich_softc *sc; 1443 struct auich_dma *p; 1444 size_t size; 1445 1446 DPRINTF(ICH_DEBUG_DMA, 1447 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1448 start, end, blksize, intr, arg, param)); 1449 sc = v; 1450 1451 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1452 continue; 1453 if (!p) { 1454 printf("auich_trigger_input: bad addr %p\n", start); 1455 return EINVAL; 1456 } 1457 1458 size = (size_t)((char *)end - (char *)start); 1459 1460 sc->pcmi.intr = intr; 1461 sc->pcmi.arg = arg; 1462 sc->pcmi.start = DMAADDR(p); 1463 sc->pcmi.p = sc->pcmi.start; 1464 sc->pcmi.end = sc->pcmi.start + size; 1465 sc->pcmi.blksize = blksize; 1466 1467 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1468 sc->sc_cddma + ICH_PCMI_OFF(0)); 1469 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1470 1471 return 0; 1472 } 1473 1474 static int 1475 auich_powerstate(void *v, int state) 1476 { 1477 return 0; 1478 } 1479 1480 static int 1481 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1482 struct auich_dma *p) 1483 { 1484 int error; 1485 1486 p->size = size; 1487 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1488 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1489 &p->nsegs, BUS_DMA_NOWAIT); 1490 if (error) 1491 return error; 1492 1493 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1494 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1495 if (error) 1496 goto free; 1497 1498 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1499 0, BUS_DMA_NOWAIT, &p->map); 1500 if (error) 1501 goto unmap; 1502 1503 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1504 BUS_DMA_NOWAIT); 1505 if (error) 1506 goto destroy; 1507 return 0; 1508 1509 destroy: 1510 bus_dmamap_destroy(sc->dmat, p->map); 1511 unmap: 1512 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1513 free: 1514 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1515 return error; 1516 } 1517 1518 static int 1519 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1520 { 1521 1522 bus_dmamap_unload(sc->dmat, p->map); 1523 bus_dmamap_destroy(sc->dmat, p->map); 1524 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1525 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1526 return 0; 1527 } 1528 1529 static int 1530 auich_alloc_cdata(struct auich_softc *sc) 1531 { 1532 bus_dma_segment_t seg; 1533 int error, rseg; 1534 1535 /* 1536 * Allocate the control data structure, and create and load the 1537 * DMA map for it. 1538 */ 1539 if ((error = bus_dmamem_alloc(sc->dmat, 1540 sizeof(struct auich_cdata), 1541 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1542 printf("%s: unable to allocate control data, error = %d\n", 1543 sc->sc_dev.dv_xname, error); 1544 goto fail_0; 1545 } 1546 1547 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1548 sizeof(struct auich_cdata), 1549 (void **) &sc->sc_cdata, 1550 sc->sc_dmamap_flags)) != 0) { 1551 printf("%s: unable to map control data, error = %d\n", 1552 sc->sc_dev.dv_xname, error); 1553 goto fail_1; 1554 } 1555 1556 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1557 sizeof(struct auich_cdata), 0, 0, 1558 &sc->sc_cddmamap)) != 0) { 1559 printf("%s: unable to create control data DMA map, " 1560 "error = %d\n", sc->sc_dev.dv_xname, error); 1561 goto fail_2; 1562 } 1563 1564 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1565 sc->sc_cdata, sizeof(struct auich_cdata), 1566 NULL, 0)) != 0) { 1567 printf("%s: unable tp load control data DMA map, " 1568 "error = %d\n", sc->sc_dev.dv_xname, error); 1569 goto fail_3; 1570 } 1571 1572 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1573 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1574 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1575 1576 return 0; 1577 1578 fail_3: 1579 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1580 fail_2: 1581 bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata, 1582 sizeof(struct auich_cdata)); 1583 fail_1: 1584 bus_dmamem_free(sc->dmat, &seg, rseg); 1585 fail_0: 1586 return error; 1587 } 1588 1589 static bool 1590 auich_resume(device_t dv) 1591 { 1592 struct auich_softc *sc = device_private(dv); 1593 pcireg_t v; 1594 1595 if (sc->sc_native_mode) { 1596 v = pci_conf_read(sc->sc_pc, sc->sc_pt, ICH_CFG); 1597 pci_conf_write(sc->sc_pc, sc->sc_pt, ICH_CFG, 1598 v | ICH_CFG_IOSE); 1599 } 1600 1601 auich_reset_codec(sc); 1602 DELAY(1000); 1603 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1604 1605 return true; 1606 } 1607 1608 /* 1609 * Calibrate card (some boards are overclocked and need scaling) 1610 */ 1611 static void 1612 auich_calibrate(struct auich_softc *sc) 1613 { 1614 struct timeval t1, t2; 1615 uint8_t ociv, nciv; 1616 uint64_t wait_us; 1617 uint32_t actual_48k_rate, bytes, ac97rate; 1618 void *temp_buffer; 1619 struct auich_dma *p; 1620 u_int rate; 1621 1622 /* 1623 * Grab audio from input for fixed interval and compare how 1624 * much we actually get with what we expect. Interval needs 1625 * to be sufficiently short that no interrupts are 1626 * generated. 1627 */ 1628 1629 /* Force the codec to a known state first. */ 1630 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1631 rate = sc->sc_ac97_clock = 48000; 1632 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1633 &rate); 1634 1635 /* Setup a buffer */ 1636 bytes = 64000; 1637 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1638 1639 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1640 continue; 1641 if (p == NULL) { 1642 printf("auich_calibrate: bad address %p\n", temp_buffer); 1643 return; 1644 } 1645 sc->pcmi.dmalist[0].base = DMAADDR(p); 1646 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1647 1648 /* 1649 * our data format is stereo, 16 bit so each sample is 4 bytes. 1650 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1651 * we're going to start recording with interrupts disabled and measure 1652 * the time taken for one block to complete. we know the block size, 1653 * we know the time in microseconds, we calculate the sample rate: 1654 * 1655 * actual_rate [bps] = bytes / (time [s] * 4) 1656 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1657 * actual_rate [Hz] = (bytes * 250000) / time [us] 1658 */ 1659 1660 /* prepare */ 1661 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1662 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1663 sc->sc_cddma + ICH_PCMI_OFF(0)); 1664 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1665 (0 - 1) & ICH_LVI_MASK); 1666 1667 /* start */ 1668 microtime(&t1); 1669 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1670 1671 /* wait */ 1672 nciv = ociv; 1673 do { 1674 microtime(&t2); 1675 if (t2.tv_sec - t1.tv_sec > 1) 1676 break; 1677 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1678 ICH_PCMI + ICH_CIV); 1679 } while (nciv == ociv); 1680 microtime(&t2); 1681 1682 /* stop */ 1683 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1684 1685 /* reset */ 1686 DELAY(100); 1687 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1688 1689 /* turn time delta into us */ 1690 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1691 1692 auich_freem(sc, temp_buffer, M_DEVBUF); 1693 1694 if (nciv == ociv) { 1695 printf("%s: ac97 link rate calibration timed out after %" 1696 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1697 return; 1698 } 1699 1700 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1701 1702 if (actual_48k_rate < 50000) 1703 ac97rate = 48000; 1704 else 1705 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1706 1707 printf("%s: measured ac97 link rate at %d Hz", 1708 sc->sc_dev.dv_xname, actual_48k_rate); 1709 if (ac97rate != actual_48k_rate) 1710 printf(", will use %d Hz", ac97rate); 1711 printf("\n"); 1712 1713 sc->sc_ac97_clock = ac97rate; 1714 } 1715 1716 static void 1717 auich_clear_cas(struct auich_softc *sc) 1718 { 1719 /* Clear the codec access semaphore */ 1720 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1721 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1722 1723 return; 1724 } 1725
Indexes created Wed Oct 22 13:09:56 GMT 2025