auich.c revision 1.123.6.2
1 /* $NetBSD: auich.c,v 1.123.6.2 2008/06/02 13:23:37 mjf Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 2000 Michael Shalayeff 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 51 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 52 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 53 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 55 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 56 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 57 * THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 60 */ 61 62 /* 63 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 64 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 77 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 78 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 79 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 80 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 81 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 82 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 83 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 84 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 85 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 86 * SUCH DAMAGE. 87 * 88 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 89 */ 90 91 92 /* #define AUICH_DEBUG */ 93 /* 94 * AC'97 audio found on Intel 810/820/440MX chipsets. 95 * http://developer.intel.com/design/chipsets/datashts/290655.htm 96 * http://developer.intel.com/design/chipsets/manuals/298028.htm 97 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 98 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 99 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 100 * AMD8111: 101 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 102 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 103 * 104 * TODO: 105 * - Add support for the dedicated microphone input. 106 * 107 * NOTE: 108 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 109 * It causes PCI master abort and hangups until cold reboot. 110 * http://www.intel.com/design/chipsets/specupdt/245051.htm 111 */ 112 113 #include <sys/cdefs.h> 114 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.123.6.2 2008/06/02 13:23:37 mjf Exp $"); 115 116 #include <sys/param.h> 117 #include <sys/systm.h> 118 #include <sys/kernel.h> 119 #include <sys/malloc.h> 120 #include <sys/device.h> 121 #include <sys/fcntl.h> 122 #include <sys/proc.h> 123 #include <sys/sysctl.h> 124 125 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 126 127 #include <dev/pci/pcidevs.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/auichreg.h> 130 131 #include <sys/audioio.h> 132 #include <dev/audio_if.h> 133 #include <dev/mulaw.h> 134 #include <dev/auconv.h> 135 136 #include <sys/bus.h> 137 138 #include <dev/ic/ac97reg.h> 139 #include <dev/ic/ac97var.h> 140 141 struct auich_dma { 142 bus_dmamap_t map; 143 void *addr; 144 bus_dma_segment_t segs[1]; 145 int nsegs; 146 size_t size; 147 struct auich_dma *next; 148 }; 149 150 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 151 #define KERNADDR(p) ((void *)((p)->addr)) 152 153 struct auich_cdata { 154 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 155 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 156 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 157 }; 158 159 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 160 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 161 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 162 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 163 164 struct auich_softc { 165 device_t sc_dev; 166 void *sc_ih; 167 168 device_t sc_audiodev; 169 audio_device_t sc_audev; 170 171 pci_chipset_tag_t sc_pc; 172 pcitag_t sc_pt; 173 bus_space_tag_t iot; 174 bus_space_handle_t mix_ioh; 175 bus_size_t mix_size; 176 bus_space_handle_t aud_ioh; 177 bus_size_t aud_size; 178 bus_dma_tag_t dmat; 179 pci_intr_handle_t intrh; 180 181 struct ac97_codec_if *codec_if; 182 struct ac97_host_if host_if; 183 int sc_codecnum; 184 int sc_codectype; 185 enum ac97_host_flags sc_codecflags; 186 bool sc_spdif; 187 188 /* DMA scatter-gather lists. */ 189 bus_dmamap_t sc_cddmamap; 190 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 191 192 struct auich_cdata *sc_cdata; 193 194 struct auich_ring { 195 int qptr; 196 struct auich_dmalist *dmalist; 197 198 uint32_t start, p, end; 199 int blksize; 200 201 void (*intr)(void *); 202 void *arg; 203 } pcmo, pcmi, mici; 204 205 struct auich_dma *sc_dmas; 206 207 /* SiS 7012 hack */ 208 int sc_sample_shift; 209 int sc_sts_reg; 210 /* 440MX workaround */ 211 int sc_dmamap_flags; 212 /* Native mode? */ 213 int sc_native_mode; 214 215 /* sysctl */ 216 struct sysctllog *sc_log; 217 uint32_t sc_ac97_clock; 218 int sc_ac97_clock_mib; 219 220 int sc_modem_offset; 221 222 #define AUICH_AUDIO_NFORMATS 3 223 #define AUICH_MODEM_NFORMATS 1 224 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 225 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 226 struct audio_encoding_set *sc_encodings; 227 struct audio_encoding_set *sc_spdif_encodings; 228 }; 229 230 /* Debug */ 231 #ifdef AUICH_DEBUG 232 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 233 int auich_debug = 0xfffe; 234 #define ICH_DEBUG_CODECIO 0x0001 235 #define ICH_DEBUG_DMA 0x0002 236 #define ICH_DEBUG_INTR 0x0004 237 #else 238 #define DPRINTF(x,y) /* nothing */ 239 #endif 240 241 static int auich_match(device_t, cfdata_t, void *); 242 static void auich_attach(device_t, device_t, void *); 243 static int auich_detach(device_t, int); 244 static int auich_activate(device_t, enum devact); 245 static int auich_intr(void *); 246 247 CFATTACH_DECL_NEW(auich, sizeof(struct auich_softc), 248 auich_match, auich_attach, auich_detach, auich_activate); 249 250 static int auich_open(void *, int); 251 static void auich_close(void *); 252 static int auich_query_encoding(void *, struct audio_encoding *); 253 static int auich_set_params(void *, int, int, audio_params_t *, 254 audio_params_t *, stream_filter_list_t *, 255 stream_filter_list_t *); 256 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 257 static void auich_halt_pipe(struct auich_softc *, int); 258 static int auich_halt_output(void *); 259 static int auich_halt_input(void *); 260 static int auich_getdev(void *, struct audio_device *); 261 static int auich_set_port(void *, mixer_ctrl_t *); 262 static int auich_get_port(void *, mixer_ctrl_t *); 263 static int auich_query_devinfo(void *, mixer_devinfo_t *); 264 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 265 static void auich_freem(void *, void *, struct malloc_type *); 266 static size_t auich_round_buffersize(void *, int, size_t); 267 static paddr_t auich_mappage(void *, void *, off_t, int); 268 static int auich_get_props(void *); 269 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 270 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 271 static int auich_trigger_output(void *, void *, void *, int, 272 void (*)(void *), void *, const audio_params_t *); 273 static int auich_trigger_input(void *, void *, void *, int, 274 void (*)(void *), void *, const audio_params_t *); 275 static int auich_powerstate(void *, int); 276 277 static int auich_alloc_cdata(struct auich_softc *); 278 279 static int auich_allocmem(struct auich_softc *, size_t, size_t, 280 struct auich_dma *); 281 static int auich_freemem(struct auich_softc *, struct auich_dma *); 282 283 static bool auich_resume(device_t PMF_FN_PROTO); 284 static int auich_set_rate(struct auich_softc *, int, u_long); 285 static int auich_sysctl_verify(SYSCTLFN_ARGS); 286 static void auich_finish_attach(device_t); 287 static void auich_calibrate(struct auich_softc *); 288 static void auich_clear_cas(struct auich_softc *); 289 290 static int auich_attach_codec(void *, struct ac97_codec_if *); 291 static int auich_read_codec(void *, uint8_t, uint16_t *); 292 static int auich_write_codec(void *, uint8_t, uint16_t); 293 static int auich_reset_codec(void *); 294 static enum ac97_host_flags auich_flags_codec(void *); 295 static void auich_spdif_event(void *, bool); 296 297 static const struct audio_hw_if auich_hw_if = { 298 auich_open, 299 auich_close, 300 NULL, /* drain */ 301 auich_query_encoding, 302 auich_set_params, 303 auich_round_blocksize, 304 NULL, /* commit_setting */ 305 NULL, /* init_output */ 306 NULL, /* init_input */ 307 NULL, /* start_output */ 308 NULL, /* start_input */ 309 auich_halt_output, 310 auich_halt_input, 311 NULL, /* speaker_ctl */ 312 auich_getdev, 313 NULL, /* getfd */ 314 auich_set_port, 315 auich_get_port, 316 auich_query_devinfo, 317 auich_allocm, 318 auich_freem, 319 auich_round_buffersize, 320 auich_mappage, 321 auich_get_props, 322 auich_trigger_output, 323 auich_trigger_input, 324 NULL, /* dev_ioctl */ 325 auich_powerstate, 326 }; 327 328 #define AUICH_FORMATS_1CH 0 329 #define AUICH_FORMATS_4CH 1 330 #define AUICH_FORMATS_6CH 2 331 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 332 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 333 2, AUFMT_STEREO, 0, {8000, 48000}}, 334 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 335 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 336 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 337 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 338 }; 339 340 #define AUICH_SPDIF_NFORMATS 1 341 static const struct audio_format auich_spdif_formats[AUICH_SPDIF_NFORMATS] = { 342 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 343 2, AUFMT_STEREO, 1, {48000}}, 344 }; 345 346 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 347 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 348 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 349 }; 350 351 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 352 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 353 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 354 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 355 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 356 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 357 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 358 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 359 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 360 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 361 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 362 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 363 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 364 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 365 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 366 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 367 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 368 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 369 #define PCIID_NFORCE430 PCI_ID_CODE0(NVIDIA, NFORCE430_AC) 370 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 371 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 372 373 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 374 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 375 #define PCIID_ICH6MODEM PCI_ID_CODE0(INTEL, 82801FB_ACM) 376 377 struct auich_devtype { 378 pcireg_t id; 379 const char *name; 380 const char *shortname; /* must be less than 11 characters */ 381 }; 382 383 static const struct auich_devtype auich_audio_devices[] = { 384 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 385 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 386 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 387 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 388 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 389 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 390 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 391 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 392 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 393 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 394 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 395 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 396 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 397 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 398 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 399 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 400 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 401 { PCIID_NFORCE430, "nForce430 (MCP51) AC-97 Audio", "nForce430" }, 402 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 403 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 404 { 0, NULL, NULL }, 405 }; 406 407 static const struct auich_devtype auich_modem_devices[] = { 408 #ifdef AUICH_ATTACH_MODEM 409 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 410 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 411 { PCIID_ICH6MODEM, "i82801FB (ICH6) AC-97 Modem", "ICH6MODEM" }, 412 #endif 413 { 0, NULL, NULL }, 414 }; 415 416 static const struct auich_devtype * 417 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 418 { 419 const struct auich_devtype *d; 420 421 for (d = auich_devices; d->name != NULL; d++) { 422 if (pa->pa_id == d->id) 423 return d; 424 } 425 426 return NULL; 427 } 428 429 static int 430 auich_match(device_t parent, cfdata_t match, void *aux) 431 { 432 struct pci_attach_args *pa; 433 434 pa = aux; 435 if (auich_lookup(pa, auich_audio_devices) != NULL) 436 return 1; 437 if (auich_lookup(pa, auich_modem_devices) != NULL) 438 return 1; 439 440 return 0; 441 } 442 443 static void 444 auich_attach(device_t parent, device_t self, void *aux) 445 { 446 struct auich_softc *sc = device_private(self); 447 struct pci_attach_args *pa; 448 pcireg_t v, subdev; 449 const char *intrstr; 450 const struct auich_devtype *d; 451 const struct sysctlnode *node, *node_ac97clock; 452 int err, node_mib, i; 453 454 sc->sc_dev = self; 455 pa = aux; 456 457 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 458 sc->sc_modem_offset = 0x10; 459 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 460 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 461 sc->sc_modem_offset = 0; 462 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 463 } else 464 panic("auich_attach: impossible"); 465 466 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 467 aprint_naive(": Audio controller\n"); 468 else 469 aprint_naive(": Modem controller\n"); 470 471 sc->sc_pc = pa->pa_pc; 472 sc->sc_pt = pa->pa_tag; 473 474 aprint_normal(": %s\n", d->name); 475 476 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 477 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 478 || d->id == PCIID_ICH4MODEM) { 479 sc->sc_native_mode = 1; 480 /* 481 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 482 */ 483 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 484 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 485 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 486 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 487 v | ICH_CFG_IOSE); 488 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 489 0, &sc->iot, &sc->mix_ioh, NULL, 490 &sc->mix_size)) { 491 aprint_error_dev(self, "can't map codec i/o space\n"); 492 return; 493 } 494 } 495 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 496 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 497 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 498 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 499 v | ICH_CFG_IOSE); 500 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 501 0, &sc->iot, &sc->aud_ioh, NULL, 502 &sc->aud_size)) { 503 aprint_error_dev(self, "can't map device i/o space\n"); 504 return; 505 } 506 } 507 } else { 508 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 509 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 510 aprint_error_dev(self, "can't map codec i/o space\n"); 511 return; 512 } 513 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 514 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 515 aprint_error_dev(self, "can't map device i/o space\n"); 516 return; 517 } 518 } 519 sc->dmat = pa->pa_dmat; 520 521 /* enable bus mastering */ 522 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 523 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 524 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 525 526 /* Map and establish the interrupt. */ 527 if (pci_intr_map(pa, &sc->intrh)) { 528 aprint_error_dev(self, "can't map interrupt\n"); 529 return; 530 } 531 intrstr = pci_intr_string(pa->pa_pc, sc->intrh); 532 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO, 533 auich_intr, sc); 534 if (sc->sc_ih == NULL) { 535 aprint_error_dev(self, "can't establish interrupt"); 536 if (intrstr != NULL) 537 aprint_normal(" at %s", intrstr); 538 aprint_normal("\n"); 539 return; 540 } 541 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 542 543 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 544 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 545 "0x%02x", PCI_REVISION(pa->pa_class)); 546 strlcpy(sc->sc_audev.config, device_xname(self), MAX_AUDIO_DEV_LEN); 547 548 /* SiS 7012 needs special handling */ 549 if (d->id == PCIID_SIS7012) { 550 sc->sc_sts_reg = ICH_PICB; 551 sc->sc_sample_shift = 0; 552 /* Un-mute output. From Linux. */ 553 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 554 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 555 ICH_SIS_CTL_UNMUTE); 556 } else { 557 sc->sc_sts_reg = ICH_STS; 558 sc->sc_sample_shift = 1; 559 } 560 561 /* Workaround for a 440MX B-stepping erratum */ 562 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 563 if (d->id == PCIID_440MX) { 564 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 565 aprint_normal_dev(self, "DMA bug workaround enabled\n"); 566 } 567 568 /* Set up DMA lists. */ 569 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 570 auich_alloc_cdata(sc); 571 572 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 573 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 574 575 /* Modem codecs are always the secondary codec on ICH */ 576 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 577 578 sc->host_if.arg = sc; 579 sc->host_if.attach = auich_attach_codec; 580 sc->host_if.read = auich_read_codec; 581 sc->host_if.write = auich_write_codec; 582 sc->host_if.reset = auich_reset_codec; 583 sc->host_if.flags = auich_flags_codec; 584 sc->host_if.spdif_event = auich_spdif_event; 585 586 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 587 switch (subdev) { 588 case 0x202f161f: /* Gateway 7326GZ */ 589 case 0x203a161f: /* Gateway 4028GZ */ 590 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 591 case 0x8144104d: /* Sony VAIO PCG-TR* */ 592 case 0x8197104d: /* Sony S1XP */ 593 case 0x81c0104d: /* Sony VAIO type T */ 594 case 0x81c5104d: /* Sony VAIO VGN-B1XP */ 595 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP; 596 break; 597 default: 598 sc->sc_codecflags = 0; 599 break; 600 } 601 602 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 603 return; 604 sc->codec_if->vtbl->unlock(sc->codec_if); 605 606 /* setup audio_format */ 607 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 608 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 609 if (!AC97_IS_4CH(sc->codec_if)) 610 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 611 if (!AC97_IS_6CH(sc->codec_if)) 612 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 613 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 614 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 615 sc->sc_audio_formats[i].frequency_type = 1; 616 sc->sc_audio_formats[i].frequency[0] = 48000; 617 } 618 } 619 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 620 &sc->sc_encodings)) 621 return; 622 if (0 != auconv_create_encodings(auich_spdif_formats, AUICH_SPDIF_NFORMATS, 623 &sc->sc_spdif_encodings)) 624 return; 625 } else { 626 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 627 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 628 &sc->sc_encodings)) 629 return; 630 } 631 632 /* Watch for power change */ 633 if (!pmf_device_register(self, NULL, auich_resume)) 634 aprint_error_dev(self, "couldn't establish power handler\n"); 635 636 config_interrupts(self, auich_finish_attach); 637 638 /* sysctl setup */ 639 if (AC97_IS_FIXED_RATE(sc->codec_if) && 640 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 641 return; 642 643 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 644 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 645 CTL_HW, CTL_EOL); 646 if (err != 0) 647 goto sysctl_err; 648 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 649 CTLTYPE_NODE, device_xname(self), NULL, NULL, 0, 650 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 651 if (err != 0) 652 goto sysctl_err; 653 node_mib = node->sysctl_num; 654 655 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 656 /* passing the sc address instead of &sc->sc_ac97_clock */ 657 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 658 CTLFLAG_READWRITE, 659 CTLTYPE_INT, "ac97rate", 660 SYSCTL_DESCR("AC'97 codec link rate"), 661 auich_sysctl_verify, 0, sc, 0, 662 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 663 if (err != 0) 664 goto sysctl_err; 665 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 666 } 667 668 return; 669 670 sysctl_err: 671 printf("%s: failed to add sysctl nodes. (%d)\n", 672 device_xname(self), err); 673 return; /* failure of sysctl is not fatal. */ 674 } 675 676 static int 677 auich_activate(struct device *self, enum devact act) 678 { 679 struct auich_softc *sc; 680 int ret; 681 682 sc = (struct auich_softc *)self; 683 ret = 0; 684 switch (act) { 685 case DVACT_ACTIVATE: 686 return EOPNOTSUPP; 687 case DVACT_DEACTIVATE: 688 if (sc->sc_audiodev != NULL) 689 ret = config_deactivate(sc->sc_audiodev); 690 return ret; 691 } 692 return EOPNOTSUPP; 693 } 694 695 static int 696 auich_detach(struct device *self, int flags) 697 { 698 struct auich_softc *sc; 699 700 sc = (struct auich_softc *)self; 701 702 /* audio */ 703 if (sc->sc_audiodev != NULL) 704 config_detach(sc->sc_audiodev, flags); 705 706 /* sysctl */ 707 sysctl_teardown(&sc->sc_log); 708 709 /* audio_encoding_set */ 710 auconv_delete_encodings(sc->sc_encodings); 711 auconv_delete_encodings(sc->sc_spdif_encodings); 712 713 /* ac97 */ 714 if (sc->codec_if != NULL) 715 sc->codec_if->vtbl->detach(sc->codec_if); 716 717 /* PCI */ 718 if (sc->sc_ih != NULL) 719 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 720 if (sc->mix_size != 0) 721 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 722 if (sc->aud_size != 0) 723 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 724 return 0; 725 } 726 727 static int 728 auich_sysctl_verify(SYSCTLFN_ARGS) 729 { 730 int error, tmp; 731 struct sysctlnode node; 732 struct auich_softc *sc; 733 734 node = *rnode; 735 sc = rnode->sysctl_data; 736 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 737 tmp = sc->sc_ac97_clock; 738 node.sysctl_data = &tmp; 739 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 740 if (error || newp == NULL) 741 return error; 742 743 if (tmp < 48000 || tmp > 96000) 744 return EINVAL; 745 sc->sc_ac97_clock = tmp; 746 } 747 748 return 0; 749 } 750 751 static void 752 auich_finish_attach(device_t self) 753 { 754 struct auich_softc *sc = device_private(self); 755 756 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 757 auich_calibrate(sc); 758 759 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, sc->sc_dev); 760 761 return; 762 } 763 764 #define ICH_CODECIO_INTERVAL 10 765 static int 766 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 767 { 768 struct auich_softc *sc; 769 int i; 770 uint32_t status; 771 772 sc = v; 773 /* wait for an access semaphore */ 774 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 775 bus_space_read_1(sc->iot, sc->aud_ioh, 776 ICH_CAS + sc->sc_modem_offset) & 1; 777 DELAY(ICH_CODECIO_INTERVAL)); 778 779 if (i > 0) { 780 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 781 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 782 DPRINTF(ICH_DEBUG_CODECIO, 783 ("auich_read_codec(%x, %x)\n", reg, *val)); 784 status = bus_space_read_4(sc->iot, sc->aud_ioh, 785 ICH_GSTS + sc->sc_modem_offset); 786 if (status & ICH_RCS) { 787 bus_space_write_4(sc->iot, sc->aud_ioh, 788 ICH_GSTS + sc->sc_modem_offset, 789 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 790 *val = 0xffff; 791 DPRINTF(ICH_DEBUG_CODECIO, 792 ("%s: read_codec error\n", device_xname(sc->sc_dev))); 793 if (reg == AC97_REG_GPIO_STATUS) 794 auich_clear_cas(sc); 795 return -1; 796 } 797 if (reg == AC97_REG_GPIO_STATUS) 798 auich_clear_cas(sc); 799 return 0; 800 } else { 801 aprint_normal_dev(sc->sc_dev, "read_codec timeout\n"); 802 if (reg == AC97_REG_GPIO_STATUS) 803 auich_clear_cas(sc); 804 return -1; 805 } 806 } 807 808 static int 809 auich_write_codec(void *v, uint8_t reg, uint16_t val) 810 { 811 struct auich_softc *sc; 812 int i; 813 814 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 815 sc = v; 816 /* wait for an access semaphore */ 817 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 818 bus_space_read_1(sc->iot, sc->aud_ioh, 819 ICH_CAS + sc->sc_modem_offset) & 1; 820 DELAY(ICH_CODECIO_INTERVAL)); 821 822 if (i > 0) { 823 bus_space_write_2(sc->iot, sc->mix_ioh, 824 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 825 return 0; 826 } else { 827 aprint_normal_dev(sc->sc_dev, "write_codec timeout\n"); 828 return -1; 829 } 830 } 831 832 static int 833 auich_attach_codec(void *v, struct ac97_codec_if *cif) 834 { 835 struct auich_softc *sc; 836 837 sc = v; 838 sc->codec_if = cif; 839 840 return 0; 841 } 842 843 static int 844 auich_reset_codec(void *v) 845 { 846 struct auich_softc *sc; 847 int i; 848 uint32_t control, status; 849 850 sc = v; 851 control = bus_space_read_4(sc->iot, sc->aud_ioh, 852 ICH_GCTRL + sc->sc_modem_offset); 853 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 854 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 855 } else { 856 control &= ~ICH_ACLSO; 857 control |= ICH_GIE; 858 } 859 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 860 bus_space_write_4(sc->iot, sc->aud_ioh, 861 ICH_GCTRL + sc->sc_modem_offset, control); 862 863 for (i = 500000; i >= 0; i--) { 864 status = bus_space_read_4(sc->iot, sc->aud_ioh, 865 ICH_GSTS + sc->sc_modem_offset); 866 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 867 break; 868 DELAY(1); 869 } 870 if (i <= 0) { 871 aprint_error_dev(sc->sc_dev, "auich_reset_codec: time out\n"); 872 return ETIMEDOUT; 873 } 874 #ifdef AUICH_DEBUG 875 if (status & ICH_SCR) 876 printf("%s: The 2nd codec is ready.\n", 877 device_xname(sc->sc_dev)); 878 if (status & ICH_S2CR) 879 printf("%s: The 3rd codec is ready.\n", 880 device_xname(sc->sc_dev)); 881 #endif 882 return 0; 883 } 884 885 static enum ac97_host_flags 886 auich_flags_codec(void *v) 887 { 888 struct auich_softc *sc = v; 889 return sc->sc_codecflags; 890 } 891 892 static void 893 auich_spdif_event(void *addr, bool flag) 894 { 895 struct auich_softc *sc; 896 897 sc = addr; 898 sc->sc_spdif = flag; 899 } 900 901 static int 902 auich_open(void *addr, int flags) 903 { 904 struct auich_softc *sc; 905 906 sc = (struct auich_softc *)addr; 907 sc->codec_if->vtbl->lock(sc->codec_if); 908 return 0; 909 } 910 911 static void 912 auich_close(void *addr) 913 { 914 struct auich_softc *sc; 915 916 sc = (struct auich_softc *)addr; 917 sc->codec_if->vtbl->unlock(sc->codec_if); 918 } 919 920 static int 921 auich_query_encoding(void *v, struct audio_encoding *aep) 922 { 923 struct auich_softc *sc; 924 925 sc = (struct auich_softc *)v; 926 return auconv_query_encoding( 927 sc->sc_spdif ? sc->sc_spdif_encodings : sc->sc_encodings, aep); 928 } 929 930 static int 931 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 932 { 933 int ret; 934 u_int ratetmp; 935 936 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 937 ratetmp = srate; 938 if (mode == AUMODE_RECORD) 939 return sc->codec_if->vtbl->set_rate(sc->codec_if, 940 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 941 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 942 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 943 if (ret) 944 return ret; 945 ratetmp = srate; 946 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 947 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 948 if (ret) 949 return ret; 950 ratetmp = srate; 951 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 952 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 953 return ret; 954 } 955 956 static int 957 auich_set_params(void *v, int setmode, int usemode, 958 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 959 stream_filter_list_t *rfil) 960 { 961 struct auich_softc *sc; 962 audio_params_t *p; 963 stream_filter_list_t *fil; 964 int mode, index; 965 uint32_t control; 966 967 sc = v; 968 for (mode = AUMODE_RECORD; mode != -1; 969 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 970 if ((setmode & mode) == 0) 971 continue; 972 973 p = mode == AUMODE_PLAY ? play : rec; 974 fil = mode == AUMODE_PLAY ? pfil : rfil; 975 if (p == NULL) 976 continue; 977 978 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 979 if (p->sample_rate < 8000 || 980 p->sample_rate > 48000) 981 return EINVAL; 982 983 if (!sc->sc_spdif) 984 index = auconv_set_converter(sc->sc_audio_formats, 985 AUICH_AUDIO_NFORMATS, mode, p, TRUE, fil); 986 else 987 index = auconv_set_converter(auich_spdif_formats, 988 AUICH_SPDIF_NFORMATS, mode, p, TRUE, fil); 989 } else { 990 if (p->sample_rate != 8000 && p->sample_rate != 16000) 991 return EINVAL; 992 index = auconv_set_converter(sc->sc_modem_formats, 993 AUICH_MODEM_NFORMATS, mode, p, TRUE, fil); 994 } 995 if (index < 0) 996 return EINVAL; 997 if (fil->req_size > 0) 998 p = &fil->filters[0].param; 999 /* p represents HW encoding */ 1000 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1001 if (sc->sc_audio_formats[index].frequency_type != 1 1002 && auich_set_rate(sc, mode, p->sample_rate)) 1003 return EINVAL; 1004 } else { 1005 if (sc->sc_modem_formats[index].frequency_type != 1 1006 && auich_set_rate(sc, mode, p->sample_rate)) 1007 return EINVAL; 1008 auich_write_codec(sc, AC97_REG_LINE1_RATE, 1009 p->sample_rate); 1010 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 1011 } 1012 if (mode == AUMODE_PLAY && 1013 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1014 control = bus_space_read_4(sc->iot, sc->aud_ioh, 1015 ICH_GCTRL + sc->sc_modem_offset); 1016 control &= ~ICH_PCM246_MASK; 1017 if (p->channels == 4) { 1018 control |= ICH_PCM4; 1019 } else if (p->channels == 6) { 1020 control |= ICH_PCM6; 1021 } 1022 bus_space_write_4(sc->iot, sc->aud_ioh, 1023 ICH_GCTRL + sc->sc_modem_offset, control); 1024 } 1025 } 1026 1027 return 0; 1028 } 1029 1030 static int 1031 auich_round_blocksize(void *v, int blk, int mode, 1032 const audio_params_t *param) 1033 { 1034 1035 return blk & ~0x3f; /* keep good alignment */ 1036 } 1037 1038 static void 1039 auich_halt_pipe(struct auich_softc *sc, int pipe) 1040 { 1041 int i; 1042 uint32_t status; 1043 1044 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 1045 for (i = 0; i < 100; i++) { 1046 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 1047 if (status & ICH_DCH) 1048 break; 1049 DELAY(1); 1050 } 1051 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 1052 1053 #if AUICH_DEBUG 1054 if (i > 0) 1055 printf("auich_halt_pipe: halt took %d cycles\n", i); 1056 #endif 1057 } 1058 1059 static int 1060 auich_halt_output(void *v) 1061 { 1062 struct auich_softc *sc; 1063 1064 sc = v; 1065 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", device_xname(sc->sc_dev))); 1066 1067 auich_halt_pipe(sc, ICH_PCMO); 1068 sc->pcmo.intr = NULL; 1069 1070 return 0; 1071 } 1072 1073 static int 1074 auich_halt_input(void *v) 1075 { 1076 struct auich_softc *sc; 1077 1078 sc = v; 1079 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", device_xname(sc->sc_dev))); 1080 1081 auich_halt_pipe(sc, ICH_PCMI); 1082 sc->pcmi.intr = NULL; 1083 1084 return 0; 1085 } 1086 1087 static int 1088 auich_getdev(void *v, struct audio_device *adp) 1089 { 1090 struct auich_softc *sc; 1091 1092 sc = v; 1093 *adp = sc->sc_audev; 1094 return 0; 1095 } 1096 1097 static int 1098 auich_set_port(void *v, mixer_ctrl_t *cp) 1099 { 1100 struct auich_softc *sc; 1101 1102 sc = v; 1103 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1104 } 1105 1106 static int 1107 auich_get_port(void *v, mixer_ctrl_t *cp) 1108 { 1109 struct auich_softc *sc; 1110 1111 sc = v; 1112 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1113 } 1114 1115 static int 1116 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1117 { 1118 struct auich_softc *sc; 1119 1120 sc = v; 1121 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1122 } 1123 1124 static void * 1125 auich_allocm(void *v, int direction, size_t size, 1126 struct malloc_type *pool, int flags) 1127 { 1128 struct auich_softc *sc; 1129 struct auich_dma *p; 1130 int error; 1131 1132 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1133 return NULL; 1134 1135 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1136 if (p == NULL) 1137 return NULL; 1138 1139 sc = v; 1140 error = auich_allocmem(sc, size, 0, p); 1141 if (error) { 1142 free(p, pool); 1143 return NULL; 1144 } 1145 1146 p->next = sc->sc_dmas; 1147 sc->sc_dmas = p; 1148 1149 return KERNADDR(p); 1150 } 1151 1152 static void 1153 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1154 { 1155 struct auich_softc *sc; 1156 struct auich_dma *p, **pp; 1157 1158 sc = v; 1159 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1160 if (KERNADDR(p) == ptr) { 1161 auich_freemem(sc, p); 1162 *pp = p->next; 1163 free(p, pool); 1164 return; 1165 } 1166 } 1167 } 1168 1169 static size_t 1170 auich_round_buffersize(void *v, int direction, size_t size) 1171 { 1172 1173 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1174 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1175 1176 return size; 1177 } 1178 1179 static paddr_t 1180 auich_mappage(void *v, void *mem, off_t off, int prot) 1181 { 1182 struct auich_softc *sc; 1183 struct auich_dma *p; 1184 1185 if (off < 0) 1186 return -1; 1187 sc = v; 1188 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1189 continue; 1190 if (!p) 1191 return -1; 1192 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1193 off, prot, BUS_DMA_WAITOK); 1194 } 1195 1196 static int 1197 auich_get_props(void *v) 1198 { 1199 struct auich_softc *sc; 1200 int props; 1201 1202 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1203 sc = v; 1204 /* 1205 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1206 * rate because of aurateconv. Applications can't know what rate the 1207 * device can process in the case of mmap(). 1208 */ 1209 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1210 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1211 props |= AUDIO_PROP_MMAP; 1212 return props; 1213 } 1214 1215 static int 1216 auich_intr(void *v) 1217 { 1218 struct auich_softc *sc; 1219 int ret, gsts; 1220 #ifdef DIAGNOSTIC 1221 int csts; 1222 #endif 1223 1224 sc = v; 1225 1226 if (!device_has_power(sc->sc_dev)) 1227 return (0); 1228 1229 ret = 0; 1230 #ifdef DIAGNOSTIC 1231 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1232 if (csts & PCI_STATUS_MASTER_ABORT) { 1233 printf("auich_intr: PCI master abort\n"); 1234 } 1235 #endif 1236 1237 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1238 ICH_GSTS + sc->sc_modem_offset); 1239 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1240 1241 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1242 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1243 int sts; 1244 1245 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1246 ICH_PCMO + sc->sc_sts_reg); 1247 DPRINTF(ICH_DEBUG_INTR, 1248 ("auich_intr: osts=0x%x\n", sts)); 1249 1250 if (sts & ICH_FIFOE) 1251 printf("%s: fifo underrun\n", device_xname(sc->sc_dev)); 1252 1253 if (sts & ICH_BCIS) 1254 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1255 1256 /* int ack */ 1257 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1258 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1259 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1260 bus_space_write_4(sc->iot, sc->aud_ioh, 1261 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1262 else 1263 bus_space_write_4(sc->iot, sc->aud_ioh, 1264 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1265 ret++; 1266 } 1267 1268 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1269 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1270 int sts; 1271 1272 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1273 ICH_PCMI + sc->sc_sts_reg); 1274 DPRINTF(ICH_DEBUG_INTR, 1275 ("auich_intr: ists=0x%x\n", sts)); 1276 1277 if (sts & ICH_FIFOE) 1278 printf("%s: fifo overrun\n", device_xname(sc->sc_dev)); 1279 1280 if (sts & ICH_BCIS) 1281 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1282 1283 /* int ack */ 1284 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1285 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1286 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1287 bus_space_write_4(sc->iot, sc->aud_ioh, 1288 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1289 else 1290 bus_space_write_4(sc->iot, sc->aud_ioh, 1291 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1292 ret++; 1293 } 1294 1295 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1296 int sts; 1297 1298 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1299 ICH_MICI + sc->sc_sts_reg); 1300 DPRINTF(ICH_DEBUG_INTR, 1301 ("auich_intr: ists=0x%x\n", sts)); 1302 1303 if (sts & ICH_FIFOE) 1304 printf("%s: fifo overrun\n", device_xname(sc->sc_dev)); 1305 1306 if (sts & ICH_BCIS) 1307 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1308 1309 /* int ack */ 1310 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1311 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1312 bus_space_write_4(sc->iot, sc->aud_ioh, 1313 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1314 ret++; 1315 } 1316 1317 #ifdef AUICH_MODEM_DEBUG 1318 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1319 printf("%s: gsts=0x%x\n", device_xname(sc->sc_dev), gsts); 1320 /* int ack */ 1321 bus_space_write_4(sc->iot, sc->aud_ioh, 1322 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1323 ret++; 1324 } 1325 #endif 1326 1327 return ret; 1328 } 1329 1330 static void 1331 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1332 { 1333 int blksize, qptr; 1334 struct auich_dmalist *q; 1335 1336 blksize = ring->blksize; 1337 1338 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1339 q = &ring->dmalist[qptr]; 1340 q->base = ring->p; 1341 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1342 1343 ring->p += blksize; 1344 if (ring->p >= ring->end) 1345 ring->p = ring->start; 1346 } 1347 ring->qptr = 0; 1348 1349 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1350 (qptr - 1) & ICH_LVI_MASK); 1351 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1352 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1353 } 1354 1355 static void 1356 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1357 { 1358 int blksize, qptr, nqptr; 1359 struct auich_dmalist *q; 1360 1361 blksize = ring->blksize; 1362 qptr = ring->qptr; 1363 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1364 1365 while (qptr != nqptr) { 1366 q = &ring->dmalist[qptr]; 1367 q->base = ring->p; 1368 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1369 1370 DPRINTF(ICH_DEBUG_INTR, 1371 ("auich_intr: %p, %p = %x @ 0x%x\n", 1372 &ring->dmalist[qptr], q, q->len, q->base)); 1373 1374 ring->p += blksize; 1375 if (ring->p >= ring->end) 1376 ring->p = ring->start; 1377 1378 qptr = (qptr + 1) & ICH_LVI_MASK; 1379 if (ring->intr) 1380 ring->intr(ring->arg); 1381 } 1382 ring->qptr = qptr; 1383 1384 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1385 (qptr - 1) & ICH_LVI_MASK); 1386 } 1387 1388 static int 1389 auich_trigger_output(void *v, void *start, void *end, int blksize, 1390 void (*intr)(void *), void *arg, const audio_params_t *param) 1391 { 1392 struct auich_softc *sc; 1393 struct auich_dma *p; 1394 size_t size; 1395 1396 DPRINTF(ICH_DEBUG_DMA, 1397 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1398 start, end, blksize, intr, arg, param)); 1399 sc = v; 1400 1401 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1402 continue; 1403 if (!p) { 1404 printf("auich_trigger_output: bad addr %p\n", start); 1405 return EINVAL; 1406 } 1407 1408 size = (size_t)((char *)end - (char *)start); 1409 1410 sc->pcmo.intr = intr; 1411 sc->pcmo.arg = arg; 1412 sc->pcmo.start = DMAADDR(p); 1413 sc->pcmo.p = sc->pcmo.start; 1414 sc->pcmo.end = sc->pcmo.start + size; 1415 sc->pcmo.blksize = blksize; 1416 1417 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1418 sc->sc_cddma + ICH_PCMO_OFF(0)); 1419 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1420 1421 return 0; 1422 } 1423 1424 static int 1425 auich_trigger_input(void *v, void *start, void *end, int blksize, 1426 void (*intr)(void *), void *arg, const audio_params_t *param) 1427 { 1428 struct auich_softc *sc; 1429 struct auich_dma *p; 1430 size_t size; 1431 1432 DPRINTF(ICH_DEBUG_DMA, 1433 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1434 start, end, blksize, intr, arg, param)); 1435 sc = v; 1436 1437 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1438 continue; 1439 if (!p) { 1440 printf("auich_trigger_input: bad addr %p\n", start); 1441 return EINVAL; 1442 } 1443 1444 size = (size_t)((char *)end - (char *)start); 1445 1446 sc->pcmi.intr = intr; 1447 sc->pcmi.arg = arg; 1448 sc->pcmi.start = DMAADDR(p); 1449 sc->pcmi.p = sc->pcmi.start; 1450 sc->pcmi.end = sc->pcmi.start + size; 1451 sc->pcmi.blksize = blksize; 1452 1453 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1454 sc->sc_cddma + ICH_PCMI_OFF(0)); 1455 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1456 1457 return 0; 1458 } 1459 1460 static int 1461 auich_powerstate(void *v, int state) 1462 { 1463 return 0; 1464 } 1465 1466 static int 1467 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1468 struct auich_dma *p) 1469 { 1470 int error; 1471 1472 p->size = size; 1473 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1474 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1475 &p->nsegs, BUS_DMA_NOWAIT); 1476 if (error) 1477 return error; 1478 1479 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1480 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1481 if (error) 1482 goto free; 1483 1484 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1485 0, BUS_DMA_NOWAIT, &p->map); 1486 if (error) 1487 goto unmap; 1488 1489 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1490 BUS_DMA_NOWAIT); 1491 if (error) 1492 goto destroy; 1493 return 0; 1494 1495 destroy: 1496 bus_dmamap_destroy(sc->dmat, p->map); 1497 unmap: 1498 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1499 free: 1500 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1501 return error; 1502 } 1503 1504 static int 1505 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1506 { 1507 1508 bus_dmamap_unload(sc->dmat, p->map); 1509 bus_dmamap_destroy(sc->dmat, p->map); 1510 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1511 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1512 return 0; 1513 } 1514 1515 static int 1516 auich_alloc_cdata(struct auich_softc *sc) 1517 { 1518 bus_dma_segment_t seg; 1519 int error, rseg; 1520 1521 /* 1522 * Allocate the control data structure, and create and load the 1523 * DMA map for it. 1524 */ 1525 if ((error = bus_dmamem_alloc(sc->dmat, 1526 sizeof(struct auich_cdata), 1527 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1528 aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n", error); 1529 goto fail_0; 1530 } 1531 1532 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1533 sizeof(struct auich_cdata), 1534 (void **) &sc->sc_cdata, 1535 sc->sc_dmamap_flags)) != 0) { 1536 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", error); 1537 goto fail_1; 1538 } 1539 1540 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1541 sizeof(struct auich_cdata), 0, 0, 1542 &sc->sc_cddmamap)) != 0) { 1543 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 1544 "error = %d\n", error); 1545 goto fail_2; 1546 } 1547 1548 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1549 sc->sc_cdata, sizeof(struct auich_cdata), 1550 NULL, 0)) != 0) { 1551 aprint_error_dev(sc->sc_dev, "unable tp load control data DMA map, " 1552 "error = %d\n", error); 1553 goto fail_3; 1554 } 1555 1556 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1557 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1558 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1559 1560 return 0; 1561 1562 fail_3: 1563 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1564 fail_2: 1565 bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata, 1566 sizeof(struct auich_cdata)); 1567 fail_1: 1568 bus_dmamem_free(sc->dmat, &seg, rseg); 1569 fail_0: 1570 return error; 1571 } 1572 1573 static bool 1574 auich_resume(device_t dv PMF_FN_ARGS) 1575 { 1576 struct auich_softc *sc = device_private(dv); 1577 pcireg_t v; 1578 1579 if (sc->sc_native_mode) { 1580 v = pci_conf_read(sc->sc_pc, sc->sc_pt, ICH_CFG); 1581 pci_conf_write(sc->sc_pc, sc->sc_pt, ICH_CFG, 1582 v | ICH_CFG_IOSE); 1583 } 1584 1585 auich_reset_codec(sc); 1586 DELAY(1000); 1587 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1588 1589 return true; 1590 } 1591 1592 /* 1593 * Calibrate card (some boards are overclocked and need scaling) 1594 */ 1595 static void 1596 auich_calibrate(struct auich_softc *sc) 1597 { 1598 struct timeval t1, t2; 1599 uint8_t ociv, nciv; 1600 uint64_t wait_us; 1601 uint32_t actual_48k_rate, bytes, ac97rate; 1602 void *temp_buffer; 1603 struct auich_dma *p; 1604 u_int rate; 1605 1606 /* 1607 * Grab audio from input for fixed interval and compare how 1608 * much we actually get with what we expect. Interval needs 1609 * to be sufficiently short that no interrupts are 1610 * generated. 1611 */ 1612 1613 /* Force the codec to a known state first. */ 1614 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1615 rate = sc->sc_ac97_clock = 48000; 1616 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1617 &rate); 1618 1619 /* Setup a buffer */ 1620 bytes = 64000; 1621 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1622 1623 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1624 continue; 1625 if (p == NULL) { 1626 printf("auich_calibrate: bad address %p\n", temp_buffer); 1627 return; 1628 } 1629 sc->pcmi.dmalist[0].base = DMAADDR(p); 1630 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1631 1632 /* 1633 * our data format is stereo, 16 bit so each sample is 4 bytes. 1634 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1635 * we're going to start recording with interrupts disabled and measure 1636 * the time taken for one block to complete. we know the block size, 1637 * we know the time in microseconds, we calculate the sample rate: 1638 * 1639 * actual_rate [bps] = bytes / (time [s] * 4) 1640 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1641 * actual_rate [Hz] = (bytes * 250000) / time [us] 1642 */ 1643 1644 /* prepare */ 1645 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1646 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1647 sc->sc_cddma + ICH_PCMI_OFF(0)); 1648 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1649 (0 - 1) & ICH_LVI_MASK); 1650 1651 /* start */ 1652 microtime(&t1); 1653 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1654 1655 /* wait */ 1656 nciv = ociv; 1657 do { 1658 microtime(&t2); 1659 if (t2.tv_sec - t1.tv_sec > 1) 1660 break; 1661 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1662 ICH_PCMI + ICH_CIV); 1663 } while (nciv == ociv); 1664 microtime(&t2); 1665 1666 /* stop */ 1667 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1668 1669 /* reset */ 1670 DELAY(100); 1671 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1672 1673 /* turn time delta into us */ 1674 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1675 1676 auich_freem(sc, temp_buffer, M_DEVBUF); 1677 1678 if (nciv == ociv) { 1679 printf("%s: ac97 link rate calibration timed out after %" 1680 PRIu64 " us\n", device_xname(sc->sc_dev), wait_us); 1681 return; 1682 } 1683 1684 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1685 1686 if (actual_48k_rate < 50000) 1687 ac97rate = 48000; 1688 else 1689 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1690 1691 printf("%s: measured ac97 link rate at %d Hz", 1692 device_xname(sc->sc_dev), actual_48k_rate); 1693 if (ac97rate != actual_48k_rate) 1694 printf(", will use %d Hz", ac97rate); 1695 printf("\n"); 1696 1697 sc->sc_ac97_clock = ac97rate; 1698 } 1699 1700 static void 1701 auich_clear_cas(struct auich_softc *sc) 1702 { 1703 /* Clear the codec access semaphore */ 1704 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1705 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1706 1707 return; 1708 } 1709
Indexes created Thu Oct 23 18:09:57 GMT 2025