auich.c revision 1.126
1 /* $NetBSD: auich.c,v 1.126 2008/04/28 20:23:54 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 2000 Michael Shalayeff 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 51 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 52 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 53 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 55 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 56 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 57 * THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 60 */ 61 62 /* 63 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 64 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 77 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 78 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 79 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 80 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 81 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 82 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 83 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 84 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 85 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 86 * SUCH DAMAGE. 87 * 88 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 89 */ 90 91 92 /* #define AUICH_DEBUG */ 93 /* 94 * AC'97 audio found on Intel 810/820/440MX chipsets. 95 * http://developer.intel.com/design/chipsets/datashts/290655.htm 96 * http://developer.intel.com/design/chipsets/manuals/298028.htm 97 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 98 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 99 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 100 * AMD8111: 101 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 102 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 103 * 104 * TODO: 105 * - Add support for the dedicated microphone input. 106 * 107 * NOTE: 108 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 109 * It causes PCI master abort and hangups until cold reboot. 110 * http://www.intel.com/design/chipsets/specupdt/245051.htm 111 */ 112 113 #include <sys/cdefs.h> 114 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.126 2008/04/28 20:23:54 martin Exp $"); 115 116 #include <sys/param.h> 117 #include <sys/systm.h> 118 #include <sys/kernel.h> 119 #include <sys/malloc.h> 120 #include <sys/device.h> 121 #include <sys/fcntl.h> 122 #include <sys/proc.h> 123 #include <sys/sysctl.h> 124 125 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 126 127 #include <dev/pci/pcidevs.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/auichreg.h> 130 131 #include <sys/audioio.h> 132 #include <dev/audio_if.h> 133 #include <dev/mulaw.h> 134 #include <dev/auconv.h> 135 136 #include <sys/bus.h> 137 138 #include <dev/ic/ac97reg.h> 139 #include <dev/ic/ac97var.h> 140 141 struct auich_dma { 142 bus_dmamap_t map; 143 void *addr; 144 bus_dma_segment_t segs[1]; 145 int nsegs; 146 size_t size; 147 struct auich_dma *next; 148 }; 149 150 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 151 #define KERNADDR(p) ((void *)((p)->addr)) 152 153 struct auich_cdata { 154 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 155 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 156 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 157 }; 158 159 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 160 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 161 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 162 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 163 164 struct auich_softc { 165 struct device sc_dev; 166 void *sc_ih; 167 168 struct device *sc_audiodev; 169 audio_device_t sc_audev; 170 171 pci_chipset_tag_t sc_pc; 172 pcitag_t sc_pt; 173 bus_space_tag_t iot; 174 bus_space_handle_t mix_ioh; 175 bus_size_t mix_size; 176 bus_space_handle_t aud_ioh; 177 bus_size_t aud_size; 178 bus_dma_tag_t dmat; 179 pci_intr_handle_t intrh; 180 181 struct ac97_codec_if *codec_if; 182 struct ac97_host_if host_if; 183 int sc_codecnum; 184 int sc_codectype; 185 enum ac97_host_flags sc_codecflags; 186 bool sc_spdif; 187 188 /* DMA scatter-gather lists. */ 189 bus_dmamap_t sc_cddmamap; 190 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 191 192 struct auich_cdata *sc_cdata; 193 194 struct auich_ring { 195 int qptr; 196 struct auich_dmalist *dmalist; 197 198 uint32_t start, p, end; 199 int blksize; 200 201 void (*intr)(void *); 202 void *arg; 203 } pcmo, pcmi, mici; 204 205 struct auich_dma *sc_dmas; 206 207 /* SiS 7012 hack */ 208 int sc_sample_shift; 209 int sc_sts_reg; 210 /* 440MX workaround */ 211 int sc_dmamap_flags; 212 /* Native mode? */ 213 int sc_native_mode; 214 215 /* sysctl */ 216 struct sysctllog *sc_log; 217 uint32_t sc_ac97_clock; 218 int sc_ac97_clock_mib; 219 220 int sc_modem_offset; 221 222 #define AUICH_AUDIO_NFORMATS 3 223 #define AUICH_MODEM_NFORMATS 1 224 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 225 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 226 struct audio_encoding_set *sc_encodings; 227 struct audio_encoding_set *sc_spdif_encodings; 228 }; 229 230 /* Debug */ 231 #ifdef AUICH_DEBUG 232 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 233 int auich_debug = 0xfffe; 234 #define ICH_DEBUG_CODECIO 0x0001 235 #define ICH_DEBUG_DMA 0x0002 236 #define ICH_DEBUG_INTR 0x0004 237 #else 238 #define DPRINTF(x,y) /* nothing */ 239 #endif 240 241 static int auich_match(struct device *, struct cfdata *, void *); 242 static void auich_attach(struct device *, struct device *, void *); 243 static int auich_detach(struct device *, int); 244 static int auich_activate(struct device *, enum devact); 245 static int auich_intr(void *); 246 247 CFATTACH_DECL(auich, sizeof(struct auich_softc), 248 auich_match, auich_attach, auich_detach, auich_activate); 249 250 static int auich_open(void *, int); 251 static void auich_close(void *); 252 static int auich_query_encoding(void *, struct audio_encoding *); 253 static int auich_set_params(void *, int, int, audio_params_t *, 254 audio_params_t *, stream_filter_list_t *, 255 stream_filter_list_t *); 256 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 257 static void auich_halt_pipe(struct auich_softc *, int); 258 static int auich_halt_output(void *); 259 static int auich_halt_input(void *); 260 static int auich_getdev(void *, struct audio_device *); 261 static int auich_set_port(void *, mixer_ctrl_t *); 262 static int auich_get_port(void *, mixer_ctrl_t *); 263 static int auich_query_devinfo(void *, mixer_devinfo_t *); 264 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 265 static void auich_freem(void *, void *, struct malloc_type *); 266 static size_t auich_round_buffersize(void *, int, size_t); 267 static paddr_t auich_mappage(void *, void *, off_t, int); 268 static int auich_get_props(void *); 269 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 270 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 271 static int auich_trigger_output(void *, void *, void *, int, 272 void (*)(void *), void *, const audio_params_t *); 273 static int auich_trigger_input(void *, void *, void *, int, 274 void (*)(void *), void *, const audio_params_t *); 275 static int auich_powerstate(void *, int); 276 277 static int auich_alloc_cdata(struct auich_softc *); 278 279 static int auich_allocmem(struct auich_softc *, size_t, size_t, 280 struct auich_dma *); 281 static int auich_freemem(struct auich_softc *, struct auich_dma *); 282 283 static bool auich_resume(device_t PMF_FN_PROTO); 284 static int auich_set_rate(struct auich_softc *, int, u_long); 285 static int auich_sysctl_verify(SYSCTLFN_ARGS); 286 static void auich_finish_attach(struct device *); 287 static void auich_calibrate(struct auich_softc *); 288 static void auich_clear_cas(struct auich_softc *); 289 290 static int auich_attach_codec(void *, struct ac97_codec_if *); 291 static int auich_read_codec(void *, uint8_t, uint16_t *); 292 static int auich_write_codec(void *, uint8_t, uint16_t); 293 static int auich_reset_codec(void *); 294 static enum ac97_host_flags auich_flags_codec(void *); 295 static void auich_spdif_event(void *, bool); 296 297 static const struct audio_hw_if auich_hw_if = { 298 auich_open, 299 auich_close, 300 NULL, /* drain */ 301 auich_query_encoding, 302 auich_set_params, 303 auich_round_blocksize, 304 NULL, /* commit_setting */ 305 NULL, /* init_output */ 306 NULL, /* init_input */ 307 NULL, /* start_output */ 308 NULL, /* start_input */ 309 auich_halt_output, 310 auich_halt_input, 311 NULL, /* speaker_ctl */ 312 auich_getdev, 313 NULL, /* getfd */ 314 auich_set_port, 315 auich_get_port, 316 auich_query_devinfo, 317 auich_allocm, 318 auich_freem, 319 auich_round_buffersize, 320 auich_mappage, 321 auich_get_props, 322 auich_trigger_output, 323 auich_trigger_input, 324 NULL, /* dev_ioctl */ 325 auich_powerstate, 326 }; 327 328 #define AUICH_FORMATS_1CH 0 329 #define AUICH_FORMATS_4CH 1 330 #define AUICH_FORMATS_6CH 2 331 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 332 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 333 2, AUFMT_STEREO, 0, {8000, 48000}}, 334 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 335 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 336 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 337 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 338 }; 339 340 #define AUICH_SPDIF_NFORMATS 1 341 static const struct audio_format auich_spdif_formats[AUICH_SPDIF_NFORMATS] = { 342 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 343 2, AUFMT_STEREO, 1, {48000}}, 344 }; 345 346 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 347 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 348 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 349 }; 350 351 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 352 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 353 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 354 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 355 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 356 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 357 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 358 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 359 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 360 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 361 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 362 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 363 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 364 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 365 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 366 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 367 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 368 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 369 #define PCIID_NFORCE430 PCI_ID_CODE0(NVIDIA, NFORCE430_AC) 370 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 371 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 372 373 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 374 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 375 #define PCIID_ICH6MODEM PCI_ID_CODE0(INTEL, 82801FB_ACM) 376 377 struct auich_devtype { 378 pcireg_t id; 379 const char *name; 380 const char *shortname; /* must be less than 11 characters */ 381 }; 382 383 static const struct auich_devtype auich_audio_devices[] = { 384 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 385 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 386 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 387 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 388 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 389 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 390 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 391 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 392 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 393 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 394 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 395 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 396 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 397 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 398 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 399 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 400 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 401 { PCIID_NFORCE430, "nForce430 (MCP51) AC-97 Audio", "nForce430" }, 402 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 403 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 404 { 0, NULL, NULL }, 405 }; 406 407 static const struct auich_devtype auich_modem_devices[] = { 408 #ifdef AUICH_ATTACH_MODEM 409 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 410 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 411 { PCIID_ICH6MODEM, "i82801FB (ICH6) AC-97 Modem", "ICH6MODEM" }, 412 #endif 413 { 0, NULL, NULL }, 414 }; 415 416 static const struct auich_devtype * 417 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 418 { 419 const struct auich_devtype *d; 420 421 for (d = auich_devices; d->name != NULL; d++) { 422 if (pa->pa_id == d->id) 423 return d; 424 } 425 426 return NULL; 427 } 428 429 static int 430 auich_match(struct device *parent, struct cfdata *match, 431 void *aux) 432 { 433 struct pci_attach_args *pa; 434 435 pa = aux; 436 if (auich_lookup(pa, auich_audio_devices) != NULL) 437 return 1; 438 if (auich_lookup(pa, auich_modem_devices) != NULL) 439 return 1; 440 441 return 0; 442 } 443 444 static void 445 auich_attach(struct device *parent, struct device *self, void *aux) 446 { 447 struct auich_softc *sc; 448 struct pci_attach_args *pa; 449 pcireg_t v, subdev; 450 const char *intrstr; 451 const struct auich_devtype *d; 452 const struct sysctlnode *node, *node_ac97clock; 453 int err, node_mib, i; 454 455 sc = (struct auich_softc *)self; 456 pa = aux; 457 458 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 459 sc->sc_modem_offset = 0x10; 460 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 461 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 462 sc->sc_modem_offset = 0; 463 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 464 } else 465 panic("auich_attach: impossible"); 466 467 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 468 aprint_naive(": Audio controller\n"); 469 else 470 aprint_naive(": Modem controller\n"); 471 472 sc->sc_pc = pa->pa_pc; 473 sc->sc_pt = pa->pa_tag; 474 475 aprint_normal(": %s\n", d->name); 476 477 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 478 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 479 || d->id == PCIID_ICH4MODEM) { 480 sc->sc_native_mode = 1; 481 /* 482 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 483 */ 484 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 485 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 486 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 487 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 488 v | ICH_CFG_IOSE); 489 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 490 0, &sc->iot, &sc->mix_ioh, NULL, 491 &sc->mix_size)) { 492 aprint_error_dev(&sc->sc_dev, "can't map codec i/o space\n"); 493 return; 494 } 495 } 496 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 497 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 498 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 499 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 500 v | ICH_CFG_IOSE); 501 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 502 0, &sc->iot, &sc->aud_ioh, NULL, 503 &sc->aud_size)) { 504 aprint_error_dev(&sc->sc_dev, "can't map device i/o space\n"); 505 return; 506 } 507 } 508 } else { 509 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 510 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 511 aprint_error_dev(&sc->sc_dev, "can't map codec i/o space\n"); 512 return; 513 } 514 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 515 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 516 aprint_error_dev(&sc->sc_dev, "can't map device i/o space\n"); 517 return; 518 } 519 } 520 sc->dmat = pa->pa_dmat; 521 522 /* enable bus mastering */ 523 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 524 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 525 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 526 527 /* Map and establish the interrupt. */ 528 if (pci_intr_map(pa, &sc->intrh)) { 529 aprint_error_dev(&sc->sc_dev, "can't map interrupt\n"); 530 return; 531 } 532 intrstr = pci_intr_string(pa->pa_pc, sc->intrh); 533 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO, 534 auich_intr, sc); 535 if (sc->sc_ih == NULL) { 536 aprint_error_dev(&sc->sc_dev, "can't establish interrupt"); 537 if (intrstr != NULL) 538 aprint_normal(" at %s", intrstr); 539 aprint_normal("\n"); 540 return; 541 } 542 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 543 544 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 545 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 546 "0x%02x", PCI_REVISION(pa->pa_class)); 547 strlcpy(sc->sc_audev.config, device_xname(&sc->sc_dev), MAX_AUDIO_DEV_LEN); 548 549 /* SiS 7012 needs special handling */ 550 if (d->id == PCIID_SIS7012) { 551 sc->sc_sts_reg = ICH_PICB; 552 sc->sc_sample_shift = 0; 553 /* Un-mute output. From Linux. */ 554 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 555 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 556 ICH_SIS_CTL_UNMUTE); 557 } else { 558 sc->sc_sts_reg = ICH_STS; 559 sc->sc_sample_shift = 1; 560 } 561 562 /* Workaround for a 440MX B-stepping erratum */ 563 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 564 if (d->id == PCIID_440MX) { 565 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 566 printf("%s: DMA bug workaround enabled\n", device_xname(&sc->sc_dev)); 567 } 568 569 /* Set up DMA lists. */ 570 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 571 auich_alloc_cdata(sc); 572 573 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 574 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 575 576 /* Modem codecs are always the secondary codec on ICH */ 577 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 578 579 sc->host_if.arg = sc; 580 sc->host_if.attach = auich_attach_codec; 581 sc->host_if.read = auich_read_codec; 582 sc->host_if.write = auich_write_codec; 583 sc->host_if.reset = auich_reset_codec; 584 sc->host_if.flags = auich_flags_codec; 585 sc->host_if.spdif_event = auich_spdif_event; 586 587 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 588 switch (subdev) { 589 case 0x202f161f: /* Gateway 7326GZ */ 590 case 0x203a161f: /* Gateway 4028GZ */ 591 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 592 case 0x8144104d: /* Sony VAIO PCG-TR* */ 593 case 0x8197104d: /* Sony S1XP */ 594 case 0x81c0104d: /* Sony VAIO type T */ 595 case 0x81c5104d: /* Sony VAIO VGN-B1XP */ 596 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP; 597 break; 598 default: 599 sc->sc_codecflags = 0; 600 break; 601 } 602 603 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 604 return; 605 sc->codec_if->vtbl->unlock(sc->codec_if); 606 607 /* setup audio_format */ 608 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 609 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 610 if (!AC97_IS_4CH(sc->codec_if)) 611 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 612 if (!AC97_IS_6CH(sc->codec_if)) 613 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 614 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 615 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 616 sc->sc_audio_formats[i].frequency_type = 1; 617 sc->sc_audio_formats[i].frequency[0] = 48000; 618 } 619 } 620 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 621 &sc->sc_encodings)) 622 return; 623 if (0 != auconv_create_encodings(auich_spdif_formats, AUICH_SPDIF_NFORMATS, 624 &sc->sc_spdif_encodings)) 625 return; 626 } else { 627 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 628 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 629 &sc->sc_encodings)) 630 return; 631 } 632 633 /* Watch for power change */ 634 if (!pmf_device_register(self, NULL, auich_resume)) 635 aprint_error_dev(self, "couldn't establish power handler\n"); 636 637 config_interrupts(self, auich_finish_attach); 638 639 /* sysctl setup */ 640 if (AC97_IS_FIXED_RATE(sc->codec_if) && 641 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 642 return; 643 644 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 645 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 646 CTL_HW, CTL_EOL); 647 if (err != 0) 648 goto sysctl_err; 649 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 650 CTLTYPE_NODE, device_xname(&sc->sc_dev), NULL, NULL, 0, 651 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 652 if (err != 0) 653 goto sysctl_err; 654 node_mib = node->sysctl_num; 655 656 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 657 /* passing the sc address instead of &sc->sc_ac97_clock */ 658 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 659 CTLFLAG_READWRITE, 660 CTLTYPE_INT, "ac97rate", 661 SYSCTL_DESCR("AC'97 codec link rate"), 662 auich_sysctl_verify, 0, sc, 0, 663 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 664 if (err != 0) 665 goto sysctl_err; 666 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 667 } 668 669 return; 670 671 sysctl_err: 672 printf("%s: failed to add sysctl nodes. (%d)\n", 673 device_xname(&sc->sc_dev), err); 674 return; /* failure of sysctl is not fatal. */ 675 } 676 677 static int 678 auich_activate(struct device *self, enum devact act) 679 { 680 struct auich_softc *sc; 681 int ret; 682 683 sc = (struct auich_softc *)self; 684 ret = 0; 685 switch (act) { 686 case DVACT_ACTIVATE: 687 return EOPNOTSUPP; 688 case DVACT_DEACTIVATE: 689 if (sc->sc_audiodev != NULL) 690 ret = config_deactivate(sc->sc_audiodev); 691 return ret; 692 } 693 return EOPNOTSUPP; 694 } 695 696 static int 697 auich_detach(struct device *self, int flags) 698 { 699 struct auich_softc *sc; 700 701 sc = (struct auich_softc *)self; 702 703 /* audio */ 704 if (sc->sc_audiodev != NULL) 705 config_detach(sc->sc_audiodev, flags); 706 707 /* sysctl */ 708 sysctl_teardown(&sc->sc_log); 709 710 /* audio_encoding_set */ 711 auconv_delete_encodings(sc->sc_encodings); 712 auconv_delete_encodings(sc->sc_spdif_encodings); 713 714 /* ac97 */ 715 if (sc->codec_if != NULL) 716 sc->codec_if->vtbl->detach(sc->codec_if); 717 718 /* PCI */ 719 if (sc->sc_ih != NULL) 720 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 721 if (sc->mix_size != 0) 722 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 723 if (sc->aud_size != 0) 724 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 725 return 0; 726 } 727 728 static int 729 auich_sysctl_verify(SYSCTLFN_ARGS) 730 { 731 int error, tmp; 732 struct sysctlnode node; 733 struct auich_softc *sc; 734 735 node = *rnode; 736 sc = rnode->sysctl_data; 737 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 738 tmp = sc->sc_ac97_clock; 739 node.sysctl_data = &tmp; 740 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 741 if (error || newp == NULL) 742 return error; 743 744 if (tmp < 48000 || tmp > 96000) 745 return EINVAL; 746 sc->sc_ac97_clock = tmp; 747 } 748 749 return 0; 750 } 751 752 static void 753 auich_finish_attach(struct device *self) 754 { 755 struct auich_softc *sc; 756 757 sc = (void *)self; 758 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 759 auich_calibrate(sc); 760 761 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 762 763 return; 764 } 765 766 #define ICH_CODECIO_INTERVAL 10 767 static int 768 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 769 { 770 struct auich_softc *sc; 771 int i; 772 uint32_t status; 773 774 sc = v; 775 /* wait for an access semaphore */ 776 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 777 bus_space_read_1(sc->iot, sc->aud_ioh, 778 ICH_CAS + sc->sc_modem_offset) & 1; 779 DELAY(ICH_CODECIO_INTERVAL)); 780 781 if (i > 0) { 782 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 783 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 784 DPRINTF(ICH_DEBUG_CODECIO, 785 ("auich_read_codec(%x, %x)\n", reg, *val)); 786 status = bus_space_read_4(sc->iot, sc->aud_ioh, 787 ICH_GSTS + sc->sc_modem_offset); 788 if (status & ICH_RCS) { 789 bus_space_write_4(sc->iot, sc->aud_ioh, 790 ICH_GSTS + sc->sc_modem_offset, 791 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 792 *val = 0xffff; 793 DPRINTF(ICH_DEBUG_CODECIO, 794 ("%s: read_codec error\n", device_xname(&sc->sc_dev))); 795 if (reg == AC97_REG_GPIO_STATUS) 796 auich_clear_cas(sc); 797 return -1; 798 } 799 if (reg == AC97_REG_GPIO_STATUS) 800 auich_clear_cas(sc); 801 return 0; 802 } else { 803 aprint_normal_dev(&sc->sc_dev, "read_codec timeout\n"); 804 if (reg == AC97_REG_GPIO_STATUS) 805 auich_clear_cas(sc); 806 return -1; 807 } 808 } 809 810 static int 811 auich_write_codec(void *v, uint8_t reg, uint16_t val) 812 { 813 struct auich_softc *sc; 814 int i; 815 816 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 817 sc = v; 818 /* wait for an access semaphore */ 819 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 820 bus_space_read_1(sc->iot, sc->aud_ioh, 821 ICH_CAS + sc->sc_modem_offset) & 1; 822 DELAY(ICH_CODECIO_INTERVAL)); 823 824 if (i > 0) { 825 bus_space_write_2(sc->iot, sc->mix_ioh, 826 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 827 return 0; 828 } else { 829 aprint_normal_dev(&sc->sc_dev, "write_codec timeout\n"); 830 return -1; 831 } 832 } 833 834 static int 835 auich_attach_codec(void *v, struct ac97_codec_if *cif) 836 { 837 struct auich_softc *sc; 838 839 sc = v; 840 sc->codec_if = cif; 841 842 return 0; 843 } 844 845 static int 846 auich_reset_codec(void *v) 847 { 848 struct auich_softc *sc; 849 int i; 850 uint32_t control, status; 851 852 sc = v; 853 control = bus_space_read_4(sc->iot, sc->aud_ioh, 854 ICH_GCTRL + sc->sc_modem_offset); 855 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 856 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 857 } else { 858 control &= ~ICH_ACLSO; 859 control |= ICH_GIE; 860 } 861 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 862 bus_space_write_4(sc->iot, sc->aud_ioh, 863 ICH_GCTRL + sc->sc_modem_offset, control); 864 865 for (i = 500000; i >= 0; i--) { 866 status = bus_space_read_4(sc->iot, sc->aud_ioh, 867 ICH_GSTS + sc->sc_modem_offset); 868 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 869 break; 870 DELAY(1); 871 } 872 if (i <= 0) { 873 aprint_error_dev(&sc->sc_dev, "auich_reset_codec: time out\n"); 874 return ETIMEDOUT; 875 } 876 #ifdef AUICH_DEBUG 877 if (status & ICH_SCR) 878 printf("%s: The 2nd codec is ready.\n", 879 device_xname(&sc->sc_dev)); 880 if (status & ICH_S2CR) 881 printf("%s: The 3rd codec is ready.\n", 882 device_xname(&sc->sc_dev)); 883 #endif 884 return 0; 885 } 886 887 static enum ac97_host_flags 888 auich_flags_codec(void *v) 889 { 890 struct auich_softc *sc = v; 891 return sc->sc_codecflags; 892 } 893 894 static void 895 auich_spdif_event(void *addr, bool flag) 896 { 897 struct auich_softc *sc; 898 899 sc = addr; 900 sc->sc_spdif = flag; 901 } 902 903 static int 904 auich_open(void *addr, int flags) 905 { 906 struct auich_softc *sc; 907 908 sc = (struct auich_softc *)addr; 909 sc->codec_if->vtbl->lock(sc->codec_if); 910 return 0; 911 } 912 913 static void 914 auich_close(void *addr) 915 { 916 struct auich_softc *sc; 917 918 sc = (struct auich_softc *)addr; 919 sc->codec_if->vtbl->unlock(sc->codec_if); 920 } 921 922 static int 923 auich_query_encoding(void *v, struct audio_encoding *aep) 924 { 925 struct auich_softc *sc; 926 927 sc = (struct auich_softc *)v; 928 return auconv_query_encoding( 929 sc->sc_spdif ? sc->sc_spdif_encodings : sc->sc_encodings, aep); 930 } 931 932 static int 933 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 934 { 935 int ret; 936 u_int ratetmp; 937 938 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 939 ratetmp = srate; 940 if (mode == AUMODE_RECORD) 941 return sc->codec_if->vtbl->set_rate(sc->codec_if, 942 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 943 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 944 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 945 if (ret) 946 return ret; 947 ratetmp = srate; 948 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 949 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 950 if (ret) 951 return ret; 952 ratetmp = srate; 953 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 954 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 955 return ret; 956 } 957 958 static int 959 auich_set_params(void *v, int setmode, int usemode, 960 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 961 stream_filter_list_t *rfil) 962 { 963 struct auich_softc *sc; 964 audio_params_t *p; 965 stream_filter_list_t *fil; 966 int mode, index; 967 uint32_t control; 968 969 sc = v; 970 for (mode = AUMODE_RECORD; mode != -1; 971 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 972 if ((setmode & mode) == 0) 973 continue; 974 975 p = mode == AUMODE_PLAY ? play : rec; 976 fil = mode == AUMODE_PLAY ? pfil : rfil; 977 if (p == NULL) 978 continue; 979 980 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 981 if (p->sample_rate < 8000 || 982 p->sample_rate > 48000) 983 return EINVAL; 984 985 if (!sc->sc_spdif) 986 index = auconv_set_converter(sc->sc_audio_formats, 987 AUICH_AUDIO_NFORMATS, mode, p, TRUE, fil); 988 else 989 index = auconv_set_converter(auich_spdif_formats, 990 AUICH_SPDIF_NFORMATS, mode, p, TRUE, fil); 991 } else { 992 if (p->sample_rate != 8000 && p->sample_rate != 16000) 993 return EINVAL; 994 index = auconv_set_converter(sc->sc_modem_formats, 995 AUICH_MODEM_NFORMATS, mode, p, TRUE, fil); 996 } 997 if (index < 0) 998 return EINVAL; 999 if (fil->req_size > 0) 1000 p = &fil->filters[0].param; 1001 /* p represents HW encoding */ 1002 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1003 if (sc->sc_audio_formats[index].frequency_type != 1 1004 && auich_set_rate(sc, mode, p->sample_rate)) 1005 return EINVAL; 1006 } else { 1007 if (sc->sc_modem_formats[index].frequency_type != 1 1008 && auich_set_rate(sc, mode, p->sample_rate)) 1009 return EINVAL; 1010 auich_write_codec(sc, AC97_REG_LINE1_RATE, 1011 p->sample_rate); 1012 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 1013 } 1014 if (mode == AUMODE_PLAY && 1015 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1016 control = bus_space_read_4(sc->iot, sc->aud_ioh, 1017 ICH_GCTRL + sc->sc_modem_offset); 1018 control &= ~ICH_PCM246_MASK; 1019 if (p->channels == 4) { 1020 control |= ICH_PCM4; 1021 } else if (p->channels == 6) { 1022 control |= ICH_PCM6; 1023 } 1024 bus_space_write_4(sc->iot, sc->aud_ioh, 1025 ICH_GCTRL + sc->sc_modem_offset, control); 1026 } 1027 } 1028 1029 return 0; 1030 } 1031 1032 static int 1033 auich_round_blocksize(void *v, int blk, int mode, 1034 const audio_params_t *param) 1035 { 1036 1037 return blk & ~0x3f; /* keep good alignment */ 1038 } 1039 1040 static void 1041 auich_halt_pipe(struct auich_softc *sc, int pipe) 1042 { 1043 int i; 1044 uint32_t status; 1045 1046 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 1047 for (i = 0; i < 100; i++) { 1048 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 1049 if (status & ICH_DCH) 1050 break; 1051 DELAY(1); 1052 } 1053 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 1054 1055 #if AUICH_DEBUG 1056 if (i > 0) 1057 printf("auich_halt_pipe: halt took %d cycles\n", i); 1058 #endif 1059 } 1060 1061 static int 1062 auich_halt_output(void *v) 1063 { 1064 struct auich_softc *sc; 1065 1066 sc = v; 1067 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", device_xname(&sc->sc_dev))); 1068 1069 auich_halt_pipe(sc, ICH_PCMO); 1070 sc->pcmo.intr = NULL; 1071 1072 return 0; 1073 } 1074 1075 static int 1076 auich_halt_input(void *v) 1077 { 1078 struct auich_softc *sc; 1079 1080 sc = v; 1081 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", device_xname(&sc->sc_dev))); 1082 1083 auich_halt_pipe(sc, ICH_PCMI); 1084 sc->pcmi.intr = NULL; 1085 1086 return 0; 1087 } 1088 1089 static int 1090 auich_getdev(void *v, struct audio_device *adp) 1091 { 1092 struct auich_softc *sc; 1093 1094 sc = v; 1095 *adp = sc->sc_audev; 1096 return 0; 1097 } 1098 1099 static int 1100 auich_set_port(void *v, mixer_ctrl_t *cp) 1101 { 1102 struct auich_softc *sc; 1103 1104 sc = v; 1105 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1106 } 1107 1108 static int 1109 auich_get_port(void *v, mixer_ctrl_t *cp) 1110 { 1111 struct auich_softc *sc; 1112 1113 sc = v; 1114 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1115 } 1116 1117 static int 1118 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1119 { 1120 struct auich_softc *sc; 1121 1122 sc = v; 1123 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1124 } 1125 1126 static void * 1127 auich_allocm(void *v, int direction, size_t size, 1128 struct malloc_type *pool, int flags) 1129 { 1130 struct auich_softc *sc; 1131 struct auich_dma *p; 1132 int error; 1133 1134 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1135 return NULL; 1136 1137 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1138 if (p == NULL) 1139 return NULL; 1140 1141 sc = v; 1142 error = auich_allocmem(sc, size, 0, p); 1143 if (error) { 1144 free(p, pool); 1145 return NULL; 1146 } 1147 1148 p->next = sc->sc_dmas; 1149 sc->sc_dmas = p; 1150 1151 return KERNADDR(p); 1152 } 1153 1154 static void 1155 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1156 { 1157 struct auich_softc *sc; 1158 struct auich_dma *p, **pp; 1159 1160 sc = v; 1161 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1162 if (KERNADDR(p) == ptr) { 1163 auich_freemem(sc, p); 1164 *pp = p->next; 1165 free(p, pool); 1166 return; 1167 } 1168 } 1169 } 1170 1171 static size_t 1172 auich_round_buffersize(void *v, int direction, size_t size) 1173 { 1174 1175 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1176 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1177 1178 return size; 1179 } 1180 1181 static paddr_t 1182 auich_mappage(void *v, void *mem, off_t off, int prot) 1183 { 1184 struct auich_softc *sc; 1185 struct auich_dma *p; 1186 1187 if (off < 0) 1188 return -1; 1189 sc = v; 1190 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1191 continue; 1192 if (!p) 1193 return -1; 1194 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1195 off, prot, BUS_DMA_WAITOK); 1196 } 1197 1198 static int 1199 auich_get_props(void *v) 1200 { 1201 struct auich_softc *sc; 1202 int props; 1203 1204 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1205 sc = v; 1206 /* 1207 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1208 * rate because of aurateconv. Applications can't know what rate the 1209 * device can process in the case of mmap(). 1210 */ 1211 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1212 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1213 props |= AUDIO_PROP_MMAP; 1214 return props; 1215 } 1216 1217 static int 1218 auich_intr(void *v) 1219 { 1220 struct auich_softc *sc; 1221 int ret, gsts; 1222 #ifdef DIAGNOSTIC 1223 int csts; 1224 #endif 1225 1226 sc = v; 1227 1228 if (!device_has_power(&sc->sc_dev)) 1229 return (0); 1230 1231 ret = 0; 1232 #ifdef DIAGNOSTIC 1233 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1234 if (csts & PCI_STATUS_MASTER_ABORT) { 1235 printf("auich_intr: PCI master abort\n"); 1236 } 1237 #endif 1238 1239 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1240 ICH_GSTS + sc->sc_modem_offset); 1241 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1242 1243 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1244 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1245 int sts; 1246 1247 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1248 ICH_PCMO + sc->sc_sts_reg); 1249 DPRINTF(ICH_DEBUG_INTR, 1250 ("auich_intr: osts=0x%x\n", sts)); 1251 1252 if (sts & ICH_FIFOE) 1253 printf("%s: fifo underrun\n", device_xname(&sc->sc_dev)); 1254 1255 if (sts & ICH_BCIS) 1256 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1257 1258 /* int ack */ 1259 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1260 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1261 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1262 bus_space_write_4(sc->iot, sc->aud_ioh, 1263 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1264 else 1265 bus_space_write_4(sc->iot, sc->aud_ioh, 1266 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1267 ret++; 1268 } 1269 1270 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1271 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1272 int sts; 1273 1274 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1275 ICH_PCMI + sc->sc_sts_reg); 1276 DPRINTF(ICH_DEBUG_INTR, 1277 ("auich_intr: ists=0x%x\n", sts)); 1278 1279 if (sts & ICH_FIFOE) 1280 printf("%s: fifo overrun\n", device_xname(&sc->sc_dev)); 1281 1282 if (sts & ICH_BCIS) 1283 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1284 1285 /* int ack */ 1286 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1287 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1288 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1289 bus_space_write_4(sc->iot, sc->aud_ioh, 1290 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1291 else 1292 bus_space_write_4(sc->iot, sc->aud_ioh, 1293 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1294 ret++; 1295 } 1296 1297 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1298 int sts; 1299 1300 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1301 ICH_MICI + sc->sc_sts_reg); 1302 DPRINTF(ICH_DEBUG_INTR, 1303 ("auich_intr: ists=0x%x\n", sts)); 1304 1305 if (sts & ICH_FIFOE) 1306 printf("%s: fifo overrun\n", device_xname(&sc->sc_dev)); 1307 1308 if (sts & ICH_BCIS) 1309 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1310 1311 /* int ack */ 1312 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1313 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1314 bus_space_write_4(sc->iot, sc->aud_ioh, 1315 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1316 ret++; 1317 } 1318 1319 #ifdef AUICH_MODEM_DEBUG 1320 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1321 printf("%s: gsts=0x%x\n", device_xname(&sc->sc_dev), gsts); 1322 /* int ack */ 1323 bus_space_write_4(sc->iot, sc->aud_ioh, 1324 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1325 ret++; 1326 } 1327 #endif 1328 1329 return ret; 1330 } 1331 1332 static void 1333 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1334 { 1335 int blksize, qptr; 1336 struct auich_dmalist *q; 1337 1338 blksize = ring->blksize; 1339 1340 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1341 q = &ring->dmalist[qptr]; 1342 q->base = ring->p; 1343 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1344 1345 ring->p += blksize; 1346 if (ring->p >= ring->end) 1347 ring->p = ring->start; 1348 } 1349 ring->qptr = 0; 1350 1351 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1352 (qptr - 1) & ICH_LVI_MASK); 1353 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1354 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1355 } 1356 1357 static void 1358 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1359 { 1360 int blksize, qptr, nqptr; 1361 struct auich_dmalist *q; 1362 1363 blksize = ring->blksize; 1364 qptr = ring->qptr; 1365 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1366 1367 while (qptr != nqptr) { 1368 q = &ring->dmalist[qptr]; 1369 q->base = ring->p; 1370 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1371 1372 DPRINTF(ICH_DEBUG_INTR, 1373 ("auich_intr: %p, %p = %x @ 0x%x\n", 1374 &ring->dmalist[qptr], q, q->len, q->base)); 1375 1376 ring->p += blksize; 1377 if (ring->p >= ring->end) 1378 ring->p = ring->start; 1379 1380 qptr = (qptr + 1) & ICH_LVI_MASK; 1381 if (ring->intr) 1382 ring->intr(ring->arg); 1383 } 1384 ring->qptr = qptr; 1385 1386 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1387 (qptr - 1) & ICH_LVI_MASK); 1388 } 1389 1390 static int 1391 auich_trigger_output(void *v, void *start, void *end, int blksize, 1392 void (*intr)(void *), void *arg, const audio_params_t *param) 1393 { 1394 struct auich_softc *sc; 1395 struct auich_dma *p; 1396 size_t size; 1397 1398 DPRINTF(ICH_DEBUG_DMA, 1399 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1400 start, end, blksize, intr, arg, param)); 1401 sc = v; 1402 1403 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1404 continue; 1405 if (!p) { 1406 printf("auich_trigger_output: bad addr %p\n", start); 1407 return EINVAL; 1408 } 1409 1410 size = (size_t)((char *)end - (char *)start); 1411 1412 sc->pcmo.intr = intr; 1413 sc->pcmo.arg = arg; 1414 sc->pcmo.start = DMAADDR(p); 1415 sc->pcmo.p = sc->pcmo.start; 1416 sc->pcmo.end = sc->pcmo.start + size; 1417 sc->pcmo.blksize = blksize; 1418 1419 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1420 sc->sc_cddma + ICH_PCMO_OFF(0)); 1421 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1422 1423 return 0; 1424 } 1425 1426 static int 1427 auich_trigger_input(void *v, void *start, void *end, int blksize, 1428 void (*intr)(void *), void *arg, const audio_params_t *param) 1429 { 1430 struct auich_softc *sc; 1431 struct auich_dma *p; 1432 size_t size; 1433 1434 DPRINTF(ICH_DEBUG_DMA, 1435 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1436 start, end, blksize, intr, arg, param)); 1437 sc = v; 1438 1439 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1440 continue; 1441 if (!p) { 1442 printf("auich_trigger_input: bad addr %p\n", start); 1443 return EINVAL; 1444 } 1445 1446 size = (size_t)((char *)end - (char *)start); 1447 1448 sc->pcmi.intr = intr; 1449 sc->pcmi.arg = arg; 1450 sc->pcmi.start = DMAADDR(p); 1451 sc->pcmi.p = sc->pcmi.start; 1452 sc->pcmi.end = sc->pcmi.start + size; 1453 sc->pcmi.blksize = blksize; 1454 1455 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1456 sc->sc_cddma + ICH_PCMI_OFF(0)); 1457 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1458 1459 return 0; 1460 } 1461 1462 static int 1463 auich_powerstate(void *v, int state) 1464 { 1465 return 0; 1466 } 1467 1468 static int 1469 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1470 struct auich_dma *p) 1471 { 1472 int error; 1473 1474 p->size = size; 1475 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1476 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1477 &p->nsegs, BUS_DMA_NOWAIT); 1478 if (error) 1479 return error; 1480 1481 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1482 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1483 if (error) 1484 goto free; 1485 1486 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1487 0, BUS_DMA_NOWAIT, &p->map); 1488 if (error) 1489 goto unmap; 1490 1491 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1492 BUS_DMA_NOWAIT); 1493 if (error) 1494 goto destroy; 1495 return 0; 1496 1497 destroy: 1498 bus_dmamap_destroy(sc->dmat, p->map); 1499 unmap: 1500 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1501 free: 1502 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1503 return error; 1504 } 1505 1506 static int 1507 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1508 { 1509 1510 bus_dmamap_unload(sc->dmat, p->map); 1511 bus_dmamap_destroy(sc->dmat, p->map); 1512 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1513 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1514 return 0; 1515 } 1516 1517 static int 1518 auich_alloc_cdata(struct auich_softc *sc) 1519 { 1520 bus_dma_segment_t seg; 1521 int error, rseg; 1522 1523 /* 1524 * Allocate the control data structure, and create and load the 1525 * DMA map for it. 1526 */ 1527 if ((error = bus_dmamem_alloc(sc->dmat, 1528 sizeof(struct auich_cdata), 1529 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1530 aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n", error); 1531 goto fail_0; 1532 } 1533 1534 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1535 sizeof(struct auich_cdata), 1536 (void **) &sc->sc_cdata, 1537 sc->sc_dmamap_flags)) != 0) { 1538 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", error); 1539 goto fail_1; 1540 } 1541 1542 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1543 sizeof(struct auich_cdata), 0, 0, 1544 &sc->sc_cddmamap)) != 0) { 1545 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 1546 "error = %d\n", error); 1547 goto fail_2; 1548 } 1549 1550 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1551 sc->sc_cdata, sizeof(struct auich_cdata), 1552 NULL, 0)) != 0) { 1553 aprint_error_dev(&sc->sc_dev, "unable tp load control data DMA map, " 1554 "error = %d\n", error); 1555 goto fail_3; 1556 } 1557 1558 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1559 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1560 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1561 1562 return 0; 1563 1564 fail_3: 1565 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1566 fail_2: 1567 bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata, 1568 sizeof(struct auich_cdata)); 1569 fail_1: 1570 bus_dmamem_free(sc->dmat, &seg, rseg); 1571 fail_0: 1572 return error; 1573 } 1574 1575 static bool 1576 auich_resume(device_t dv PMF_FN_ARGS) 1577 { 1578 struct auich_softc *sc = device_private(dv); 1579 pcireg_t v; 1580 1581 if (sc->sc_native_mode) { 1582 v = pci_conf_read(sc->sc_pc, sc->sc_pt, ICH_CFG); 1583 pci_conf_write(sc->sc_pc, sc->sc_pt, ICH_CFG, 1584 v | ICH_CFG_IOSE); 1585 } 1586 1587 auich_reset_codec(sc); 1588 DELAY(1000); 1589 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1590 1591 return true; 1592 } 1593 1594 /* 1595 * Calibrate card (some boards are overclocked and need scaling) 1596 */ 1597 static void 1598 auich_calibrate(struct auich_softc *sc) 1599 { 1600 struct timeval t1, t2; 1601 uint8_t ociv, nciv; 1602 uint64_t wait_us; 1603 uint32_t actual_48k_rate, bytes, ac97rate; 1604 void *temp_buffer; 1605 struct auich_dma *p; 1606 u_int rate; 1607 1608 /* 1609 * Grab audio from input for fixed interval and compare how 1610 * much we actually get with what we expect. Interval needs 1611 * to be sufficiently short that no interrupts are 1612 * generated. 1613 */ 1614 1615 /* Force the codec to a known state first. */ 1616 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1617 rate = sc->sc_ac97_clock = 48000; 1618 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1619 &rate); 1620 1621 /* Setup a buffer */ 1622 bytes = 64000; 1623 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1624 1625 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1626 continue; 1627 if (p == NULL) { 1628 printf("auich_calibrate: bad address %p\n", temp_buffer); 1629 return; 1630 } 1631 sc->pcmi.dmalist[0].base = DMAADDR(p); 1632 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1633 1634 /* 1635 * our data format is stereo, 16 bit so each sample is 4 bytes. 1636 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1637 * we're going to start recording with interrupts disabled and measure 1638 * the time taken for one block to complete. we know the block size, 1639 * we know the time in microseconds, we calculate the sample rate: 1640 * 1641 * actual_rate [bps] = bytes / (time [s] * 4) 1642 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1643 * actual_rate [Hz] = (bytes * 250000) / time [us] 1644 */ 1645 1646 /* prepare */ 1647 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1648 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1649 sc->sc_cddma + ICH_PCMI_OFF(0)); 1650 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1651 (0 - 1) & ICH_LVI_MASK); 1652 1653 /* start */ 1654 microtime(&t1); 1655 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1656 1657 /* wait */ 1658 nciv = ociv; 1659 do { 1660 microtime(&t2); 1661 if (t2.tv_sec - t1.tv_sec > 1) 1662 break; 1663 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1664 ICH_PCMI + ICH_CIV); 1665 } while (nciv == ociv); 1666 microtime(&t2); 1667 1668 /* stop */ 1669 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1670 1671 /* reset */ 1672 DELAY(100); 1673 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1674 1675 /* turn time delta into us */ 1676 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1677 1678 auich_freem(sc, temp_buffer, M_DEVBUF); 1679 1680 if (nciv == ociv) { 1681 printf("%s: ac97 link rate calibration timed out after %" 1682 PRIu64 " us\n", device_xname(&sc->sc_dev), wait_us); 1683 return; 1684 } 1685 1686 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1687 1688 if (actual_48k_rate < 50000) 1689 ac97rate = 48000; 1690 else 1691 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1692 1693 printf("%s: measured ac97 link rate at %d Hz", 1694 device_xname(&sc->sc_dev), actual_48k_rate); 1695 if (ac97rate != actual_48k_rate) 1696 printf(", will use %d Hz", ac97rate); 1697 printf("\n"); 1698 1699 sc->sc_ac97_clock = ac97rate; 1700 } 1701 1702 static void 1703 auich_clear_cas(struct auich_softc *sc) 1704 { 1705 /* Clear the codec access semaphore */ 1706 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1707 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1708 1709 return; 1710 } 1711
Indexes created Thu Oct 23 22:10:10 GMT 2025