auich.c revision 1.143
1 /* $NetBSD: auich.c,v 1.143 2014/03/29 19:28:24 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 2000 Michael Shalayeff 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 51 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 52 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 53 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 55 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 56 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 57 * THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 60 */ 61 62 /* 63 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 64 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 77 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 78 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 79 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 80 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 81 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 82 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 83 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 84 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 85 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 86 * SUCH DAMAGE. 87 * 88 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 89 */ 90 91 92 /* #define AUICH_DEBUG */ 93 /* 94 * AC'97 audio found on Intel 810/820/440MX chipsets. 95 * http://developer.intel.com/design/chipsets/datashts/290655.htm 96 * http://developer.intel.com/design/chipsets/manuals/298028.htm 97 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 98 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 99 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 100 * AMD8111: 101 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 102 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 103 * 104 * TODO: 105 * - Add support for the dedicated microphone input. 106 * 107 * NOTE: 108 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 109 * It causes PCI master abort and hangups until cold reboot. 110 * http://www.intel.com/design/chipsets/specupdt/245051.htm 111 */ 112 113 #include <sys/cdefs.h> 114 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.143 2014/03/29 19:28:24 christos Exp $"); 115 116 #include <sys/param.h> 117 #include <sys/systm.h> 118 #include <sys/kernel.h> 119 #include <sys/kmem.h> 120 #include <sys/device.h> 121 #include <sys/fcntl.h> 122 #include <sys/proc.h> 123 #include <sys/sysctl.h> 124 #include <sys/audioio.h> 125 #include <sys/bus.h> 126 127 #include <dev/pci/pcidevs.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/auichreg.h> 130 131 #include <dev/audio_if.h> 132 #include <dev/mulaw.h> 133 #include <dev/auconv.h> 134 135 #include <dev/ic/ac97reg.h> 136 #include <dev/ic/ac97var.h> 137 138 struct auich_dma { 139 bus_dmamap_t map; 140 void *addr; 141 bus_dma_segment_t segs[1]; 142 int nsegs; 143 size_t size; 144 struct auich_dma *next; 145 }; 146 147 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 148 #define KERNADDR(p) ((void *)((p)->addr)) 149 150 struct auich_cdata { 151 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 152 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 153 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 154 }; 155 156 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 157 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 158 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 159 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 160 161 struct auich_softc { 162 device_t sc_dev; 163 void *sc_ih; 164 kmutex_t sc_lock; 165 kmutex_t sc_intr_lock; 166 167 device_t sc_audiodev; 168 audio_device_t sc_audev; 169 170 pci_chipset_tag_t sc_pc; 171 pcitag_t sc_pt; 172 bus_space_tag_t iot; 173 bus_space_handle_t mix_ioh; 174 bus_size_t mix_size; 175 bus_space_handle_t aud_ioh; 176 bus_size_t aud_size; 177 bus_dma_tag_t dmat; 178 pci_intr_handle_t intrh; 179 180 struct ac97_codec_if *codec_if; 181 struct ac97_host_if host_if; 182 int sc_codecnum; 183 int sc_codectype; 184 int sc_fixedrate; 185 enum ac97_host_flags sc_codecflags; 186 bool sc_spdif; 187 188 /* multi-channel control bits */ 189 int sc_pcm246_mask; 190 int sc_pcm2; 191 int sc_pcm4; 192 int sc_pcm6; 193 194 /* DMA scatter-gather lists. */ 195 bus_dmamap_t sc_cddmamap; 196 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 197 198 struct auich_cdata *sc_cdata; 199 200 struct auich_ring { 201 int qptr; 202 struct auich_dmalist *dmalist; 203 204 uint32_t start, p, end; 205 int blksize; 206 207 void (*intr)(void *); 208 void *arg; 209 } pcmo, pcmi, mici; 210 211 struct auich_dma *sc_dmas; 212 213 /* SiS 7012 hack */ 214 int sc_sample_shift; 215 int sc_sts_reg; 216 /* 440MX workaround */ 217 int sc_dmamap_flags; 218 /* flags */ 219 int sc_iose :1, 220 :31; 221 222 /* sysctl */ 223 struct sysctllog *sc_log; 224 uint32_t sc_ac97_clock; 225 int sc_ac97_clock_mib; 226 227 int sc_modem_offset; 228 229 #define AUICH_AUDIO_NFORMATS 3 230 #define AUICH_MODEM_NFORMATS 1 231 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 232 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 233 struct audio_encoding_set *sc_encodings; 234 struct audio_encoding_set *sc_spdif_encodings; 235 }; 236 237 /* Debug */ 238 #ifdef AUICH_DEBUG 239 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 240 int auich_debug = 0xfffe; 241 #define ICH_DEBUG_CODECIO 0x0001 242 #define ICH_DEBUG_DMA 0x0002 243 #define ICH_DEBUG_INTR 0x0004 244 #else 245 #define DPRINTF(x,y) /* nothing */ 246 #endif 247 248 static int auich_match(device_t, cfdata_t, void *); 249 static void auich_attach(device_t, device_t, void *); 250 static int auich_detach(device_t, int); 251 static void auich_childdet(device_t, device_t); 252 static int auich_intr(void *); 253 254 CFATTACH_DECL2_NEW(auich, sizeof(struct auich_softc), 255 auich_match, auich_attach, auich_detach, NULL, NULL, auich_childdet); 256 257 static int auich_open(void *, int); 258 static void auich_close(void *); 259 static int auich_query_encoding(void *, struct audio_encoding *); 260 static int auich_set_params(void *, int, int, audio_params_t *, 261 audio_params_t *, stream_filter_list_t *, 262 stream_filter_list_t *); 263 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 264 static void auich_halt_pipe(struct auich_softc *, int); 265 static int auich_halt_output(void *); 266 static int auich_halt_input(void *); 267 static int auich_getdev(void *, struct audio_device *); 268 static int auich_set_port(void *, mixer_ctrl_t *); 269 static int auich_get_port(void *, mixer_ctrl_t *); 270 static int auich_query_devinfo(void *, mixer_devinfo_t *); 271 static void *auich_allocm(void *, int, size_t); 272 static void auich_freem(void *, void *, size_t); 273 static size_t auich_round_buffersize(void *, int, size_t); 274 static paddr_t auich_mappage(void *, void *, off_t, int); 275 static int auich_get_props(void *); 276 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 277 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 278 static int auich_trigger_output(void *, void *, void *, int, 279 void (*)(void *), void *, const audio_params_t *); 280 static int auich_trigger_input(void *, void *, void *, int, 281 void (*)(void *), void *, const audio_params_t *); 282 static void auich_get_locks(void *, kmutex_t **, kmutex_t **); 283 284 static int auich_alloc_cdata(struct auich_softc *); 285 286 static int auich_allocmem(struct auich_softc *, size_t, size_t, 287 struct auich_dma *); 288 static int auich_freemem(struct auich_softc *, struct auich_dma *); 289 290 static bool auich_resume(device_t, const pmf_qual_t *); 291 static int auich_set_rate(struct auich_softc *, int, u_long); 292 static int auich_sysctl_verify(SYSCTLFN_ARGS); 293 static void auich_finish_attach(device_t); 294 static void auich_calibrate(struct auich_softc *); 295 static void auich_clear_cas(struct auich_softc *); 296 297 static int auich_attach_codec(void *, struct ac97_codec_if *); 298 static int auich_read_codec(void *, uint8_t, uint16_t *); 299 static int auich_write_codec(void *, uint8_t, uint16_t); 300 static int auich_reset_codec(void *); 301 static enum ac97_host_flags auich_flags_codec(void *); 302 static void auich_spdif_event(void *, bool); 303 304 static const struct audio_hw_if auich_hw_if = { 305 auich_open, 306 auich_close, 307 NULL, /* drain */ 308 auich_query_encoding, 309 auich_set_params, 310 auich_round_blocksize, 311 NULL, /* commit_setting */ 312 NULL, /* init_output */ 313 NULL, /* init_input */ 314 NULL, /* start_output */ 315 NULL, /* start_input */ 316 auich_halt_output, 317 auich_halt_input, 318 NULL, /* speaker_ctl */ 319 auich_getdev, 320 NULL, /* getfd */ 321 auich_set_port, 322 auich_get_port, 323 auich_query_devinfo, 324 auich_allocm, 325 auich_freem, 326 auich_round_buffersize, 327 auich_mappage, 328 auich_get_props, 329 auich_trigger_output, 330 auich_trigger_input, 331 NULL, /* dev_ioctl */ 332 auich_get_locks, 333 }; 334 335 #define AUICH_FORMATS_1CH 0 336 #define AUICH_FORMATS_4CH 1 337 #define AUICH_FORMATS_6CH 2 338 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 339 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 340 2, AUFMT_STEREO, 0, {8000, 48000}}, 341 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 342 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 343 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 344 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 345 }; 346 347 #define AUICH_SPDIF_NFORMATS 1 348 static const struct audio_format auich_spdif_formats[AUICH_SPDIF_NFORMATS] = { 349 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 350 2, AUFMT_STEREO, 1, {48000}}, 351 }; 352 353 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 354 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 355 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 356 }; 357 358 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 359 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 360 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 361 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 362 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 363 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 364 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 365 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 366 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 367 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 368 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 369 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 370 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 371 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 372 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 373 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 374 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 375 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 376 #define PCIID_NFORCE430 PCI_ID_CODE0(NVIDIA, NFORCE430_AC) 377 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 378 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 379 380 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 381 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 382 #define PCIID_ICH6MODEM PCI_ID_CODE0(INTEL, 82801FB_ACM) 383 384 struct auich_devtype { 385 pcireg_t id; 386 const char *name; 387 const char *shortname; /* must be less than 11 characters */ 388 }; 389 390 static const struct auich_devtype auich_audio_devices[] = { 391 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 392 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 393 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 394 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 395 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 396 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 397 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 398 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 399 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 400 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 401 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 402 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 403 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 404 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 405 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 406 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 407 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 408 { PCIID_NFORCE430, "nForce430 (MCP51) AC-97 Audio", "nForce430" }, 409 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 410 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 411 { 0, NULL, NULL }, 412 }; 413 414 static const struct auich_devtype auich_modem_devices[] = { 415 #ifdef AUICH_ATTACH_MODEM 416 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 417 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 418 { PCIID_ICH6MODEM, "i82801FB (ICH6) AC-97 Modem", "ICH6MODEM" }, 419 #endif 420 { 0, NULL, NULL }, 421 }; 422 423 static const struct auich_devtype * 424 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 425 { 426 const struct auich_devtype *d; 427 428 for (d = auich_devices; d->name != NULL; d++) { 429 if (pa->pa_id == d->id) 430 return d; 431 } 432 433 return NULL; 434 } 435 436 static int 437 auich_match(device_t parent, cfdata_t match, void *aux) 438 { 439 struct pci_attach_args *pa; 440 441 pa = aux; 442 if (auich_lookup(pa, auich_audio_devices) != NULL) 443 return 1; 444 if (auich_lookup(pa, auich_modem_devices) != NULL) 445 return 1; 446 447 return 0; 448 } 449 450 static void 451 auich_attach(device_t parent, device_t self, void *aux) 452 { 453 struct auich_softc *sc = device_private(self); 454 struct pci_attach_args *pa; 455 pcireg_t v, subdev; 456 const char *intrstr; 457 const struct auich_devtype *d; 458 const struct sysctlnode *node, *node_ac97clock; 459 int err, node_mib, i; 460 char intrbuf[PCI_INTRSTR_LEN]; 461 462 sc->sc_dev = self; 463 pa = aux; 464 465 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 466 sc->sc_modem_offset = 0x10; 467 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 468 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 469 sc->sc_modem_offset = 0; 470 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 471 } else 472 panic("auich_attach: impossible"); 473 474 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 475 aprint_naive(": Audio controller\n"); 476 else 477 aprint_naive(": Modem controller\n"); 478 479 sc->sc_pc = pa->pa_pc; 480 sc->sc_pt = pa->pa_tag; 481 482 aprint_normal(": %s\n", d->name); 483 484 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 485 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 486 || d->id == PCIID_ICH4MODEM) { 487 /* 488 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 489 */ 490 491 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 492 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 493 goto retry_map; 494 } 495 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 496 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 497 goto retry_map; 498 } 499 goto map_done; 500 } else 501 goto non_native_map; 502 503 retry_map: 504 sc->sc_iose = 1; 505 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 506 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 507 v | ICH_CFG_IOSE); 508 509 non_native_map: 510 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 511 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 512 aprint_error_dev(self, "can't map codec i/o space\n"); 513 return; 514 } 515 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 516 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 517 aprint_error_dev(self, "can't map device i/o space\n"); 518 return; 519 } 520 521 map_done: 522 sc->dmat = pa->pa_dmat; 523 524 /* enable bus mastering */ 525 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 526 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 527 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 528 529 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 530 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 531 532 /* Map and establish the interrupt. */ 533 if (pci_intr_map(pa, &sc->intrh)) { 534 aprint_error_dev(self, "can't map interrupt\n"); 535 return; 536 } 537 intrstr = pci_intr_string(pa->pa_pc, sc->intrh, intrbuf, sizeof(intrbuf)); 538 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO, 539 auich_intr, sc); 540 if (sc->sc_ih == NULL) { 541 aprint_error_dev(self, "can't establish interrupt"); 542 if (intrstr != NULL) 543 aprint_error(" at %s", intrstr); 544 aprint_error("\n"); 545 return; 546 } 547 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 548 549 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 550 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 551 "0x%02x", PCI_REVISION(pa->pa_class)); 552 strlcpy(sc->sc_audev.config, device_xname(self), MAX_AUDIO_DEV_LEN); 553 554 /* SiS 7012 needs special handling */ 555 if (d->id == PCIID_SIS7012) { 556 sc->sc_sts_reg = ICH_PICB; 557 sc->sc_sample_shift = 0; 558 sc->sc_pcm246_mask = ICH_SIS_PCM246_MASK; 559 sc->sc_pcm2 = ICH_SIS_PCM2; 560 sc->sc_pcm4 = ICH_SIS_PCM4; 561 sc->sc_pcm6 = ICH_SIS_PCM6; 562 /* Un-mute output. From Linux. */ 563 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 564 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 565 ICH_SIS_CTL_UNMUTE); 566 } else { 567 sc->sc_sts_reg = ICH_STS; 568 sc->sc_sample_shift = 1; 569 sc->sc_pcm246_mask = ICH_PCM246_MASK; 570 sc->sc_pcm2 = ICH_PCM2; 571 sc->sc_pcm4 = ICH_PCM4; 572 sc->sc_pcm6 = ICH_PCM6; 573 } 574 575 /* Workaround for a 440MX B-stepping erratum */ 576 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 577 if (d->id == PCIID_440MX) { 578 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 579 aprint_normal_dev(self, "DMA bug workaround enabled\n"); 580 } 581 582 /* Set up DMA lists. */ 583 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 584 auich_alloc_cdata(sc); 585 586 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 587 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 588 589 /* Modem codecs are always the secondary codec on ICH */ 590 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 591 592 sc->host_if.arg = sc; 593 sc->host_if.attach = auich_attach_codec; 594 sc->host_if.read = auich_read_codec; 595 sc->host_if.write = auich_write_codec; 596 sc->host_if.reset = auich_reset_codec; 597 sc->host_if.flags = auich_flags_codec; 598 sc->host_if.spdif_event = auich_spdif_event; 599 600 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 601 switch (subdev) { 602 case 0x202f161f: /* Gateway 7326GZ */ 603 case 0x203a161f: /* Gateway 4028GZ */ 604 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 605 case 0x8144104d: /* Sony VAIO PCG-TR* */ 606 case 0x8197104d: /* Sony S1XP */ 607 case 0x81c0104d: /* Sony VAIO type T */ 608 case 0x81c5104d: /* Sony VAIO VGN-B1XP */ 609 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP; 610 break; 611 default: 612 sc->sc_codecflags = 0; 613 break; 614 } 615 616 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype, 617 &sc->sc_lock) != 0) 618 return; 619 620 mutex_enter(&sc->sc_lock); 621 sc->codec_if->vtbl->unlock(sc->codec_if); 622 sc->sc_fixedrate = AC97_IS_FIXED_RATE(sc->codec_if); 623 624 /* setup audio_format */ 625 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 626 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 627 if (!AC97_IS_4CH(sc->codec_if)) 628 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 629 if (!AC97_IS_6CH(sc->codec_if)) 630 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 631 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 632 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 633 sc->sc_audio_formats[i].frequency_type = 1; 634 sc->sc_audio_formats[i].frequency[0] = 48000; 635 } 636 } 637 mutex_exit(&sc->sc_lock); 638 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 639 &sc->sc_encodings)) 640 return; 641 if (0 != auconv_create_encodings(auich_spdif_formats, AUICH_SPDIF_NFORMATS, 642 &sc->sc_spdif_encodings)) 643 return; 644 } else { 645 mutex_exit(&sc->sc_lock); 646 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 647 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 648 &sc->sc_encodings)) 649 return; 650 } 651 652 /* Watch for power change */ 653 if (!pmf_device_register(self, NULL, auich_resume)) 654 aprint_error_dev(self, "couldn't establish power handler\n"); 655 656 config_interrupts(self, auich_finish_attach); 657 658 /* sysctl setup */ 659 if (sc->sc_fixedrate && sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 660 return; 661 662 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 663 CTLTYPE_NODE, device_xname(self), NULL, NULL, 0, 664 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 665 if (err != 0) 666 goto sysctl_err; 667 node_mib = node->sysctl_num; 668 669 if (!sc->sc_fixedrate) { 670 /* passing the sc address instead of &sc->sc_ac97_clock */ 671 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 672 CTLFLAG_READWRITE, 673 CTLTYPE_INT, "ac97rate", 674 SYSCTL_DESCR("AC'97 codec link rate"), 675 auich_sysctl_verify, 0, (void *)sc, 0, 676 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 677 if (err != 0) 678 goto sysctl_err; 679 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 680 } 681 682 return; 683 684 sysctl_err: 685 printf("%s: failed to add sysctl nodes. (%d)\n", 686 device_xname(self), err); 687 return; /* failure of sysctl is not fatal. */ 688 } 689 690 static void 691 auich_childdet(device_t self, device_t child) 692 { 693 struct auich_softc *sc = device_private(self); 694 695 KASSERT(sc->sc_audiodev == child); 696 sc->sc_audiodev = NULL; 697 } 698 699 static int 700 auich_detach(device_t self, int flags) 701 { 702 struct auich_softc *sc = device_private(self); 703 704 /* audio */ 705 if (sc->sc_audiodev != NULL) 706 config_detach(sc->sc_audiodev, flags); 707 708 /* sysctl */ 709 sysctl_teardown(&sc->sc_log); 710 711 mutex_enter(&sc->sc_lock); 712 713 /* audio_encoding_set */ 714 auconv_delete_encodings(sc->sc_encodings); 715 auconv_delete_encodings(sc->sc_spdif_encodings); 716 717 /* ac97 */ 718 if (sc->codec_if != NULL) 719 sc->codec_if->vtbl->detach(sc->codec_if); 720 721 mutex_exit(&sc->sc_lock); 722 mutex_destroy(&sc->sc_lock); 723 mutex_destroy(&sc->sc_intr_lock); 724 725 /* PCI */ 726 if (sc->sc_ih != NULL) 727 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 728 if (sc->mix_size != 0) 729 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 730 if (sc->aud_size != 0) 731 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 732 return 0; 733 } 734 735 static int 736 auich_sysctl_verify(SYSCTLFN_ARGS) 737 { 738 int error, tmp; 739 struct sysctlnode node; 740 struct auich_softc *sc; 741 742 node = *rnode; 743 sc = rnode->sysctl_data; 744 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 745 tmp = sc->sc_ac97_clock; 746 node.sysctl_data = &tmp; 747 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 748 if (error || newp == NULL) 749 return error; 750 751 if (tmp < 48000 || tmp > 96000) 752 return EINVAL; 753 mutex_enter(&sc->sc_lock); 754 sc->sc_ac97_clock = tmp; 755 mutex_exit(&sc->sc_lock); 756 } 757 758 return 0; 759 } 760 761 static void 762 auich_finish_attach(device_t self) 763 { 764 struct auich_softc *sc = device_private(self); 765 766 mutex_enter(&sc->sc_lock); 767 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 768 auich_calibrate(sc); 769 mutex_exit(&sc->sc_lock); 770 771 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, sc->sc_dev); 772 773 return; 774 } 775 776 #define ICH_CODECIO_INTERVAL 10 777 static int 778 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 779 { 780 struct auich_softc *sc; 781 int i; 782 uint32_t status; 783 784 sc = v; 785 /* wait for an access semaphore */ 786 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 787 bus_space_read_1(sc->iot, sc->aud_ioh, 788 ICH_CAS + sc->sc_modem_offset) & 1; 789 DELAY(ICH_CODECIO_INTERVAL)); 790 791 if (i > 0) { 792 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 793 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 794 DPRINTF(ICH_DEBUG_CODECIO, 795 ("auich_read_codec(%x, %x)\n", reg, *val)); 796 status = bus_space_read_4(sc->iot, sc->aud_ioh, 797 ICH_GSTS + sc->sc_modem_offset); 798 if (status & ICH_RCS) { 799 bus_space_write_4(sc->iot, sc->aud_ioh, 800 ICH_GSTS + sc->sc_modem_offset, 801 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 802 *val = 0xffff; 803 DPRINTF(ICH_DEBUG_CODECIO, 804 ("%s: read_codec error\n", device_xname(sc->sc_dev))); 805 if (reg == AC97_REG_GPIO_STATUS) 806 auich_clear_cas(sc); 807 return -1; 808 } 809 if (reg == AC97_REG_GPIO_STATUS) 810 auich_clear_cas(sc); 811 return 0; 812 } else { 813 aprint_normal_dev(sc->sc_dev, "read_codec timeout\n"); 814 if (reg == AC97_REG_GPIO_STATUS) 815 auich_clear_cas(sc); 816 return -1; 817 } 818 } 819 820 static int 821 auich_write_codec(void *v, uint8_t reg, uint16_t val) 822 { 823 struct auich_softc *sc; 824 int i; 825 826 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 827 sc = v; 828 /* wait for an access semaphore */ 829 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 830 bus_space_read_1(sc->iot, sc->aud_ioh, 831 ICH_CAS + sc->sc_modem_offset) & 1; 832 DELAY(ICH_CODECIO_INTERVAL)); 833 834 if (i > 0) { 835 bus_space_write_2(sc->iot, sc->mix_ioh, 836 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 837 return 0; 838 } else { 839 aprint_normal_dev(sc->sc_dev, "write_codec timeout\n"); 840 return -1; 841 } 842 } 843 844 static int 845 auich_attach_codec(void *v, struct ac97_codec_if *cif) 846 { 847 struct auich_softc *sc; 848 849 sc = v; 850 sc->codec_if = cif; 851 852 return 0; 853 } 854 855 static int 856 auich_reset_codec(void *v) 857 { 858 struct auich_softc *sc; 859 int i; 860 uint32_t control, status; 861 862 sc = v; 863 control = bus_space_read_4(sc->iot, sc->aud_ioh, 864 ICH_GCTRL + sc->sc_modem_offset); 865 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 866 control &= ~(ICH_ACLSO | sc->sc_pcm246_mask); 867 } else { 868 control &= ~ICH_ACLSO; 869 control |= ICH_GIE; 870 } 871 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 872 bus_space_write_4(sc->iot, sc->aud_ioh, 873 ICH_GCTRL + sc->sc_modem_offset, control); 874 875 for (i = 500000; i >= 0; i--) { 876 status = bus_space_read_4(sc->iot, sc->aud_ioh, 877 ICH_GSTS + sc->sc_modem_offset); 878 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 879 break; 880 DELAY(1); 881 } 882 if (i <= 0) { 883 aprint_error_dev(sc->sc_dev, "auich_reset_codec: time out\n"); 884 return ETIMEDOUT; 885 } 886 #ifdef AUICH_DEBUG 887 if (status & ICH_SCR) 888 printf("%s: The 2nd codec is ready.\n", 889 device_xname(sc->sc_dev)); 890 if (status & ICH_S2CR) 891 printf("%s: The 3rd codec is ready.\n", 892 device_xname(sc->sc_dev)); 893 #endif 894 return 0; 895 } 896 897 static enum ac97_host_flags 898 auich_flags_codec(void *v) 899 { 900 struct auich_softc *sc = v; 901 return sc->sc_codecflags; 902 } 903 904 static void 905 auich_spdif_event(void *addr, bool flag) 906 { 907 struct auich_softc *sc; 908 909 sc = addr; 910 sc->sc_spdif = flag; 911 } 912 913 static int 914 auich_open(void *addr, int flags) 915 { 916 struct auich_softc *sc; 917 918 sc = (struct auich_softc *)addr; 919 mutex_spin_exit(&sc->sc_intr_lock); 920 sc->codec_if->vtbl->lock(sc->codec_if); 921 mutex_spin_enter(&sc->sc_intr_lock); 922 return 0; 923 } 924 925 static void 926 auich_close(void *addr) 927 { 928 struct auich_softc *sc; 929 930 sc = (struct auich_softc *)addr; 931 mutex_spin_exit(&sc->sc_intr_lock); 932 sc->codec_if->vtbl->unlock(sc->codec_if); 933 mutex_spin_enter(&sc->sc_intr_lock); 934 } 935 936 static int 937 auich_query_encoding(void *v, struct audio_encoding *aep) 938 { 939 struct auich_softc *sc; 940 941 sc = (struct auich_softc *)v; 942 return auconv_query_encoding( 943 sc->sc_spdif ? sc->sc_spdif_encodings : sc->sc_encodings, aep); 944 } 945 946 static int 947 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 948 { 949 int ret; 950 u_int ratetmp; 951 952 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 953 ratetmp = srate; 954 if (mode == AUMODE_RECORD) 955 return sc->codec_if->vtbl->set_rate(sc->codec_if, 956 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 957 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 958 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 959 if (ret) 960 return ret; 961 ratetmp = srate; 962 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 963 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 964 if (ret) 965 return ret; 966 ratetmp = srate; 967 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 968 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 969 return ret; 970 } 971 972 static int 973 auich_set_params(void *v, int setmode, int usemode, 974 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 975 stream_filter_list_t *rfil) 976 { 977 struct auich_softc *sc; 978 audio_params_t *p; 979 stream_filter_list_t *fil; 980 int mode, index; 981 uint32_t control; 982 983 sc = v; 984 for (mode = AUMODE_RECORD; mode != -1; 985 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 986 if ((setmode & mode) == 0) 987 continue; 988 989 p = mode == AUMODE_PLAY ? play : rec; 990 fil = mode == AUMODE_PLAY ? pfil : rfil; 991 if (p == NULL) 992 continue; 993 994 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 995 if (p->sample_rate < 8000 || 996 p->sample_rate > 48000) 997 return EINVAL; 998 999 if (!sc->sc_spdif) 1000 index = auconv_set_converter(sc->sc_audio_formats, 1001 AUICH_AUDIO_NFORMATS, mode, p, TRUE, fil); 1002 else 1003 index = auconv_set_converter(auich_spdif_formats, 1004 AUICH_SPDIF_NFORMATS, mode, p, TRUE, fil); 1005 } else { 1006 if (p->sample_rate != 8000 && p->sample_rate != 16000) 1007 return EINVAL; 1008 index = auconv_set_converter(sc->sc_modem_formats, 1009 AUICH_MODEM_NFORMATS, mode, p, TRUE, fil); 1010 } 1011 if (index < 0) 1012 return EINVAL; 1013 if (fil->req_size > 0) 1014 p = &fil->filters[0].param; 1015 /* p represents HW encoding */ 1016 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1017 if (sc->sc_audio_formats[index].frequency_type != 1 1018 && auich_set_rate(sc, mode, p->sample_rate)) 1019 return EINVAL; 1020 } else { 1021 if (sc->sc_modem_formats[index].frequency_type != 1 1022 && auich_set_rate(sc, mode, p->sample_rate)) 1023 return EINVAL; 1024 auich_write_codec(sc, AC97_REG_LINE1_RATE, 1025 p->sample_rate); 1026 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 1027 } 1028 if (mode == AUMODE_PLAY && 1029 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1030 control = bus_space_read_4(sc->iot, sc->aud_ioh, 1031 ICH_GCTRL + sc->sc_modem_offset); 1032 control &= ~sc->sc_pcm246_mask; 1033 if (p->channels == 4) { 1034 control |= sc->sc_pcm4; 1035 } else if (p->channels == 6) { 1036 control |= sc->sc_pcm6; 1037 } 1038 bus_space_write_4(sc->iot, sc->aud_ioh, 1039 ICH_GCTRL + sc->sc_modem_offset, control); 1040 } 1041 } 1042 1043 return 0; 1044 } 1045 1046 static int 1047 auich_round_blocksize(void *v, int blk, int mode, 1048 const audio_params_t *param) 1049 { 1050 1051 return blk & ~0x3f; /* keep good alignment */ 1052 } 1053 1054 static void 1055 auich_halt_pipe(struct auich_softc *sc, int pipe) 1056 { 1057 int i; 1058 uint32_t status; 1059 1060 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 1061 for (i = 0; i < 100; i++) { 1062 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 1063 if (status & ICH_DCH) 1064 break; 1065 DELAY(1); 1066 } 1067 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 1068 1069 #if AUICH_DEBUG 1070 if (i > 0) 1071 printf("auich_halt_pipe: halt took %d cycles\n", i); 1072 #endif 1073 } 1074 1075 static int 1076 auich_halt_output(void *v) 1077 { 1078 struct auich_softc *sc; 1079 1080 sc = v; 1081 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", device_xname(sc->sc_dev))); 1082 1083 auich_halt_pipe(sc, ICH_PCMO); 1084 sc->pcmo.intr = NULL; 1085 1086 return 0; 1087 } 1088 1089 static int 1090 auich_halt_input(void *v) 1091 { 1092 struct auich_softc *sc; 1093 1094 sc = v; 1095 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", device_xname(sc->sc_dev))); 1096 1097 auich_halt_pipe(sc, ICH_PCMI); 1098 sc->pcmi.intr = NULL; 1099 1100 return 0; 1101 } 1102 1103 static int 1104 auich_getdev(void *v, struct audio_device *adp) 1105 { 1106 struct auich_softc *sc; 1107 1108 sc = v; 1109 *adp = sc->sc_audev; 1110 return 0; 1111 } 1112 1113 static int 1114 auich_set_port(void *v, mixer_ctrl_t *cp) 1115 { 1116 struct auich_softc *sc; 1117 1118 sc = v; 1119 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1120 } 1121 1122 static int 1123 auich_get_port(void *v, mixer_ctrl_t *cp) 1124 { 1125 struct auich_softc *sc; 1126 1127 sc = v; 1128 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1129 } 1130 1131 static int 1132 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1133 { 1134 struct auich_softc *sc; 1135 1136 sc = v; 1137 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1138 } 1139 1140 static void * 1141 auich_allocm(void *v, int direction, size_t size) 1142 { 1143 struct auich_softc *sc; 1144 struct auich_dma *p; 1145 int error; 1146 1147 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1148 return NULL; 1149 1150 p = kmem_alloc(sizeof(*p), KM_SLEEP); 1151 if (p == NULL) 1152 return NULL; 1153 1154 sc = v; 1155 error = auich_allocmem(sc, size, 0, p); 1156 if (error) { 1157 kmem_free(p, sizeof(*p)); 1158 return NULL; 1159 } 1160 1161 p->next = sc->sc_dmas; 1162 sc->sc_dmas = p; 1163 1164 return KERNADDR(p); 1165 } 1166 1167 static void 1168 auich_freem(void *v, void *ptr, size_t size) 1169 { 1170 struct auich_softc *sc; 1171 struct auich_dma *p, **pp; 1172 1173 sc = v; 1174 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1175 if (KERNADDR(p) == ptr) { 1176 auich_freemem(sc, p); 1177 *pp = p->next; 1178 kmem_free(p, sizeof(*p)); 1179 return; 1180 } 1181 } 1182 } 1183 1184 static size_t 1185 auich_round_buffersize(void *v, int direction, size_t size) 1186 { 1187 1188 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1189 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1190 1191 return size; 1192 } 1193 1194 static paddr_t 1195 auich_mappage(void *v, void *mem, off_t off, int prot) 1196 { 1197 struct auich_softc *sc; 1198 struct auich_dma *p; 1199 1200 if (off < 0) 1201 return -1; 1202 sc = v; 1203 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1204 continue; 1205 if (!p) 1206 return -1; 1207 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1208 off, prot, BUS_DMA_WAITOK); 1209 } 1210 1211 static int 1212 auich_get_props(void *v) 1213 { 1214 struct auich_softc *sc; 1215 int props; 1216 1217 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1218 sc = v; 1219 /* 1220 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1221 * rate because of aurateconv. Applications can't know what rate the 1222 * device can process in the case of mmap(). 1223 */ 1224 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1225 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1226 props |= AUDIO_PROP_MMAP; 1227 return props; 1228 } 1229 1230 static int 1231 auich_intr(void *v) 1232 { 1233 struct auich_softc *sc; 1234 int ret, gsts; 1235 #ifdef DIAGNOSTIC 1236 int csts; 1237 #endif 1238 1239 sc = v; 1240 1241 if (!device_has_power(sc->sc_dev)) 1242 return (0); 1243 1244 mutex_spin_enter(&sc->sc_intr_lock); 1245 1246 ret = 0; 1247 #ifdef DIAGNOSTIC 1248 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1249 if (csts & PCI_STATUS_MASTER_ABORT) { 1250 printf("auich_intr: PCI master abort\n"); 1251 } 1252 #endif 1253 1254 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1255 ICH_GSTS + sc->sc_modem_offset); 1256 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1257 1258 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1259 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1260 int sts; 1261 1262 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1263 ICH_PCMO + sc->sc_sts_reg); 1264 DPRINTF(ICH_DEBUG_INTR, 1265 ("auich_intr: osts=0x%x\n", sts)); 1266 1267 if (sts & ICH_FIFOE) 1268 printf("%s: fifo underrun\n", device_xname(sc->sc_dev)); 1269 1270 if (sts & ICH_BCIS) 1271 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1272 1273 /* int ack */ 1274 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1275 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1276 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1277 bus_space_write_4(sc->iot, sc->aud_ioh, 1278 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1279 else 1280 bus_space_write_4(sc->iot, sc->aud_ioh, 1281 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1282 ret++; 1283 } 1284 1285 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1286 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1287 int sts; 1288 1289 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1290 ICH_PCMI + sc->sc_sts_reg); 1291 DPRINTF(ICH_DEBUG_INTR, 1292 ("auich_intr: ists=0x%x\n", sts)); 1293 1294 if (sts & ICH_FIFOE) 1295 printf("%s: fifo overrun\n", device_xname(sc->sc_dev)); 1296 1297 if (sts & ICH_BCIS) 1298 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1299 1300 /* int ack */ 1301 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1302 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1303 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1304 bus_space_write_4(sc->iot, sc->aud_ioh, 1305 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1306 else 1307 bus_space_write_4(sc->iot, sc->aud_ioh, 1308 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1309 ret++; 1310 } 1311 1312 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1313 int sts; 1314 1315 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1316 ICH_MICI + sc->sc_sts_reg); 1317 DPRINTF(ICH_DEBUG_INTR, 1318 ("auich_intr: ists=0x%x\n", sts)); 1319 1320 if (sts & ICH_FIFOE) 1321 printf("%s: fifo overrun\n", device_xname(sc->sc_dev)); 1322 1323 if (sts & ICH_BCIS) 1324 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1325 1326 /* int ack */ 1327 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1328 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1329 bus_space_write_4(sc->iot, sc->aud_ioh, 1330 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1331 ret++; 1332 } 1333 1334 #ifdef AUICH_MODEM_DEBUG 1335 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1336 printf("%s: gsts=0x%x\n", device_xname(sc->sc_dev), gsts); 1337 /* int ack */ 1338 bus_space_write_4(sc->iot, sc->aud_ioh, 1339 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1340 ret++; 1341 } 1342 #endif 1343 1344 mutex_spin_exit(&sc->sc_intr_lock); 1345 1346 return ret; 1347 } 1348 1349 static void 1350 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1351 { 1352 int blksize, qptr; 1353 struct auich_dmalist *q; 1354 1355 blksize = ring->blksize; 1356 1357 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1358 q = &ring->dmalist[qptr]; 1359 q->base = ring->p; 1360 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1361 1362 ring->p += blksize; 1363 if (ring->p >= ring->end) 1364 ring->p = ring->start; 1365 } 1366 ring->qptr = 0; 1367 1368 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1369 (qptr - 1) & ICH_LVI_MASK); 1370 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1371 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1372 } 1373 1374 static void 1375 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1376 { 1377 int blksize, qptr, nqptr; 1378 struct auich_dmalist *q; 1379 1380 blksize = ring->blksize; 1381 qptr = ring->qptr; 1382 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1383 1384 while (qptr != nqptr) { 1385 q = &ring->dmalist[qptr]; 1386 q->base = ring->p; 1387 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1388 1389 DPRINTF(ICH_DEBUG_INTR, 1390 ("auich_intr: %p, %p = %x @ 0x%x\n", 1391 &ring->dmalist[qptr], q, q->len, q->base)); 1392 1393 ring->p += blksize; 1394 if (ring->p >= ring->end) 1395 ring->p = ring->start; 1396 1397 qptr = (qptr + 1) & ICH_LVI_MASK; 1398 if (ring->intr) 1399 ring->intr(ring->arg); 1400 } 1401 ring->qptr = qptr; 1402 1403 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1404 (qptr - 1) & ICH_LVI_MASK); 1405 } 1406 1407 static int 1408 auich_trigger_output(void *v, void *start, void *end, int blksize, 1409 void (*intr)(void *), void *arg, const audio_params_t *param) 1410 { 1411 struct auich_softc *sc; 1412 struct auich_dma *p; 1413 size_t size; 1414 1415 DPRINTF(ICH_DEBUG_DMA, 1416 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1417 start, end, blksize, intr, arg, param)); 1418 sc = v; 1419 1420 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1421 continue; 1422 if (!p) { 1423 printf("auich_trigger_output: bad addr %p\n", start); 1424 return EINVAL; 1425 } 1426 1427 size = (size_t)((char *)end - (char *)start); 1428 1429 sc->pcmo.intr = intr; 1430 sc->pcmo.arg = arg; 1431 sc->pcmo.start = DMAADDR(p); 1432 sc->pcmo.p = sc->pcmo.start; 1433 sc->pcmo.end = sc->pcmo.start + size; 1434 sc->pcmo.blksize = blksize; 1435 1436 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1437 sc->sc_cddma + ICH_PCMO_OFF(0)); 1438 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1439 1440 return 0; 1441 } 1442 1443 static int 1444 auich_trigger_input(void *v, void *start, void *end, int blksize, 1445 void (*intr)(void *), void *arg, const audio_params_t *param) 1446 { 1447 struct auich_softc *sc; 1448 struct auich_dma *p; 1449 size_t size; 1450 1451 DPRINTF(ICH_DEBUG_DMA, 1452 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1453 start, end, blksize, intr, arg, param)); 1454 sc = v; 1455 1456 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1457 continue; 1458 if (!p) { 1459 printf("auich_trigger_input: bad addr %p\n", start); 1460 return EINVAL; 1461 } 1462 1463 size = (size_t)((char *)end - (char *)start); 1464 1465 sc->pcmi.intr = intr; 1466 sc->pcmi.arg = arg; 1467 sc->pcmi.start = DMAADDR(p); 1468 sc->pcmi.p = sc->pcmi.start; 1469 sc->pcmi.end = sc->pcmi.start + size; 1470 sc->pcmi.blksize = blksize; 1471 1472 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1473 sc->sc_cddma + ICH_PCMI_OFF(0)); 1474 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1475 1476 return 0; 1477 } 1478 1479 static int 1480 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1481 struct auich_dma *p) 1482 { 1483 int error; 1484 1485 p->size = size; 1486 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1487 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1488 &p->nsegs, BUS_DMA_WAITOK); 1489 if (error) 1490 return error; 1491 1492 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1493 &p->addr, BUS_DMA_WAITOK|sc->sc_dmamap_flags); 1494 if (error) 1495 goto free; 1496 1497 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1498 0, BUS_DMA_WAITOK, &p->map); 1499 if (error) 1500 goto unmap; 1501 1502 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1503 BUS_DMA_WAITOK); 1504 if (error) 1505 goto destroy; 1506 return 0; 1507 1508 destroy: 1509 bus_dmamap_destroy(sc->dmat, p->map); 1510 unmap: 1511 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1512 free: 1513 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1514 return error; 1515 } 1516 1517 static int 1518 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1519 { 1520 1521 bus_dmamap_unload(sc->dmat, p->map); 1522 bus_dmamap_destroy(sc->dmat, p->map); 1523 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1524 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1525 return 0; 1526 } 1527 1528 static int 1529 auich_alloc_cdata(struct auich_softc *sc) 1530 { 1531 bus_dma_segment_t seg; 1532 int error, rseg; 1533 1534 /* 1535 * Allocate the control data structure, and create and load the 1536 * DMA map for it. 1537 */ 1538 if ((error = bus_dmamem_alloc(sc->dmat, 1539 sizeof(struct auich_cdata), 1540 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1541 aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n", error); 1542 goto fail_0; 1543 } 1544 1545 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1546 sizeof(struct auich_cdata), 1547 (void **) &sc->sc_cdata, 1548 sc->sc_dmamap_flags)) != 0) { 1549 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", error); 1550 goto fail_1; 1551 } 1552 1553 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1554 sizeof(struct auich_cdata), 0, 0, 1555 &sc->sc_cddmamap)) != 0) { 1556 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 1557 "error = %d\n", error); 1558 goto fail_2; 1559 } 1560 1561 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1562 sc->sc_cdata, sizeof(struct auich_cdata), 1563 NULL, 0)) != 0) { 1564 aprint_error_dev(sc->sc_dev, "unable tp load control data DMA map, " 1565 "error = %d\n", error); 1566 goto fail_3; 1567 } 1568 1569 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1570 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1571 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1572 1573 return 0; 1574 1575 fail_3: 1576 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1577 fail_2: 1578 bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata, 1579 sizeof(struct auich_cdata)); 1580 fail_1: 1581 bus_dmamem_free(sc->dmat, &seg, rseg); 1582 fail_0: 1583 return error; 1584 } 1585 1586 static bool 1587 auich_resume(device_t dv, const pmf_qual_t *qual) 1588 { 1589 struct auich_softc *sc = device_private(dv); 1590 pcireg_t v; 1591 1592 mutex_enter(&sc->sc_lock); 1593 mutex_spin_enter(&sc->sc_intr_lock); 1594 1595 if (sc->sc_iose) { 1596 v = pci_conf_read(sc->sc_pc, sc->sc_pt, ICH_CFG); 1597 pci_conf_write(sc->sc_pc, sc->sc_pt, ICH_CFG, 1598 v | ICH_CFG_IOSE); 1599 } 1600 1601 auich_reset_codec(sc); 1602 mutex_spin_exit(&sc->sc_intr_lock); 1603 DELAY(1000); 1604 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1605 mutex_exit(&sc->sc_lock); 1606 1607 return true; 1608 } 1609 1610 /* 1611 * Calibrate card (some boards are overclocked and need scaling) 1612 */ 1613 static void 1614 auich_calibrate(struct auich_softc *sc) 1615 { 1616 struct timeval t1, t2; 1617 uint8_t ociv, nciv; 1618 uint64_t wait_us; 1619 uint32_t actual_48k_rate, bytes, ac97rate; 1620 void *temp_buffer; 1621 struct auich_dma *p; 1622 u_int rate; 1623 1624 /* 1625 * Grab audio from input for fixed interval and compare how 1626 * much we actually get with what we expect. Interval needs 1627 * to be sufficiently short that no interrupts are 1628 * generated. 1629 */ 1630 1631 /* Force the codec to a known state first. */ 1632 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1633 rate = sc->sc_ac97_clock = 48000; 1634 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1635 &rate); 1636 1637 /* Setup a buffer */ 1638 bytes = 64000; 1639 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes); 1640 1641 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1642 continue; 1643 if (p == NULL) { 1644 printf("auich_calibrate: bad address %p\n", temp_buffer); 1645 return; 1646 } 1647 sc->pcmi.dmalist[0].base = DMAADDR(p); 1648 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1649 1650 /* 1651 * our data format is stereo, 16 bit so each sample is 4 bytes. 1652 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1653 * we're going to start recording with interrupts disabled and measure 1654 * the time taken for one block to complete. we know the block size, 1655 * we know the time in microseconds, we calculate the sample rate: 1656 * 1657 * actual_rate [bps] = bytes / (time [s] * 4) 1658 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1659 * actual_rate [Hz] = (bytes * 250000) / time [us] 1660 */ 1661 1662 /* prepare */ 1663 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1664 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1665 sc->sc_cddma + ICH_PCMI_OFF(0)); 1666 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1667 (0 - 1) & ICH_LVI_MASK); 1668 1669 /* start */ 1670 kpreempt_disable(); 1671 microtime(&t1); 1672 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1673 1674 /* wait */ 1675 nciv = ociv; 1676 do { 1677 microtime(&t2); 1678 if (t2.tv_sec - t1.tv_sec > 1) 1679 break; 1680 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1681 ICH_PCMI + ICH_CIV); 1682 } while (nciv == ociv); 1683 microtime(&t2); 1684 1685 /* stop */ 1686 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1687 kpreempt_enable(); 1688 1689 /* reset */ 1690 DELAY(100); 1691 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1692 1693 /* turn time delta into us */ 1694 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1695 1696 auich_freem(sc, temp_buffer, bytes); 1697 1698 if (nciv == ociv) { 1699 printf("%s: ac97 link rate calibration timed out after %" 1700 PRIu64 " us\n", device_xname(sc->sc_dev), wait_us); 1701 return; 1702 } 1703 1704 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1705 1706 if (actual_48k_rate < 50000) 1707 ac97rate = 48000; 1708 else 1709 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1710 1711 aprint_verbose_dev(sc->sc_dev, "measured ac97 link rate at %d Hz", 1712 actual_48k_rate); 1713 if (ac97rate != actual_48k_rate) 1714 aprint_verbose(", will use %d Hz", ac97rate); 1715 aprint_verbose("\n"); 1716 1717 sc->sc_ac97_clock = ac97rate; 1718 } 1719 1720 static void 1721 auich_clear_cas(struct auich_softc *sc) 1722 { 1723 /* Clear the codec access semaphore */ 1724 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1725 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1726 1727 return; 1728 } 1729 1730 static void 1731 auich_get_locks(void *addr, kmutex_t **intr, kmutex_t **thread) 1732 { 1733 struct auich_softc *sc; 1734 1735 sc = addr; 1736 *intr = &sc->sc_intr_lock; 1737 *thread = &sc->sc_lock; 1738 } 1739
Indexes created Thu Oct 23 18:09:57 GMT 2025