auich.c revision 1.143.2.1
1 /* $NetBSD: auich.c,v 1.143.2.1 2014/04/07 03:37:33 tls Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 2000 Michael Shalayeff 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 51 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 52 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 53 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 55 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 56 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 57 * THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 60 */ 61 62 /* 63 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 64 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 77 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 78 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 79 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 80 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 81 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 82 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 83 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 84 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 85 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 86 * SUCH DAMAGE. 87 * 88 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 89 */ 90 91 92 /* #define AUICH_DEBUG */ 93 /* 94 * AC'97 audio found on Intel 810/820/440MX chipsets. 95 * http://developer.intel.com/design/chipsets/datashts/290655.htm 96 * http://developer.intel.com/design/chipsets/manuals/298028.htm 97 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 98 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 99 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 100 * AMD8111: 101 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 102 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 103 * 104 * TODO: 105 * - Add support for the dedicated microphone input. 106 * 107 * NOTE: 108 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 109 * It causes PCI master abort and hangups until cold reboot. 110 * http://www.intel.com/design/chipsets/specupdt/245051.htm 111 */ 112 113 #include <sys/cdefs.h> 114 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.143.2.1 2014/04/07 03:37:33 tls Exp $"); 115 116 #include <sys/param.h> 117 #include <sys/systm.h> 118 #include <sys/kernel.h> 119 #include <sys/kmem.h> 120 #include <sys/device.h> 121 #include <sys/fcntl.h> 122 #include <sys/proc.h> 123 #include <sys/sysctl.h> 124 #include <sys/audioio.h> 125 #include <sys/bus.h> 126 #include <sys/rnd.h> 127 128 #include <dev/pci/pcidevs.h> 129 #include <dev/pci/pcivar.h> 130 #include <dev/pci/auichreg.h> 131 132 #include <dev/audio_if.h> 133 #include <dev/mulaw.h> 134 #include <dev/auconv.h> 135 136 #include <dev/ic/ac97reg.h> 137 #include <dev/ic/ac97var.h> 138 139 struct auich_dma { 140 bus_dmamap_t map; 141 void *addr; 142 bus_dma_segment_t segs[1]; 143 int nsegs; 144 size_t size; 145 struct auich_dma *next; 146 }; 147 148 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 149 #define KERNADDR(p) ((void *)((p)->addr)) 150 151 struct auich_cdata { 152 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 153 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 154 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 155 }; 156 157 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 158 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 159 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 160 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 161 162 struct auich_softc { 163 device_t sc_dev; 164 void *sc_ih; 165 kmutex_t sc_lock; 166 kmutex_t sc_intr_lock; 167 168 device_t sc_audiodev; 169 audio_device_t sc_audev; 170 171 pci_chipset_tag_t sc_pc; 172 pcitag_t sc_pt; 173 bus_space_tag_t iot; 174 bus_space_handle_t mix_ioh; 175 bus_size_t mix_size; 176 bus_space_handle_t aud_ioh; 177 bus_size_t aud_size; 178 bus_dma_tag_t dmat; 179 pci_intr_handle_t intrh; 180 181 struct ac97_codec_if *codec_if; 182 struct ac97_host_if host_if; 183 int sc_codecnum; 184 int sc_codectype; 185 int sc_fixedrate; 186 enum ac97_host_flags sc_codecflags; 187 bool sc_spdif; 188 189 /* multi-channel control bits */ 190 int sc_pcm246_mask; 191 int sc_pcm2; 192 int sc_pcm4; 193 int sc_pcm6; 194 195 /* DMA scatter-gather lists. */ 196 bus_dmamap_t sc_cddmamap; 197 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 198 199 struct auich_cdata *sc_cdata; 200 201 struct auich_ring { 202 int qptr; 203 struct auich_dmalist *dmalist; 204 205 uint32_t start, p, end; 206 int blksize; 207 208 void (*intr)(void *); 209 void *arg; 210 } pcmo, pcmi, mici; 211 212 struct auich_dma *sc_dmas; 213 214 /* SiS 7012 hack */ 215 int sc_sample_shift; 216 int sc_sts_reg; 217 /* 440MX workaround */ 218 int sc_dmamap_flags; 219 /* flags */ 220 int sc_iose :1, 221 :31; 222 223 /* sysctl */ 224 struct sysctllog *sc_log; 225 uint32_t sc_ac97_clock; 226 int sc_ac97_clock_mib; 227 228 int sc_modem_offset; 229 230 #define AUICH_AUDIO_NFORMATS 3 231 #define AUICH_MODEM_NFORMATS 1 232 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 233 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 234 struct audio_encoding_set *sc_encodings; 235 struct audio_encoding_set *sc_spdif_encodings; 236 }; 237 238 /* Debug */ 239 #ifdef AUICH_DEBUG 240 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 241 int auich_debug = 0xfffe; 242 #define ICH_DEBUG_CODECIO 0x0001 243 #define ICH_DEBUG_DMA 0x0002 244 #define ICH_DEBUG_INTR 0x0004 245 #else 246 #define DPRINTF(x,y) /* nothing */ 247 #endif 248 249 static int auich_match(device_t, cfdata_t, void *); 250 static void auich_attach(device_t, device_t, void *); 251 static int auich_detach(device_t, int); 252 static void auich_childdet(device_t, device_t); 253 static int auich_intr(void *); 254 255 CFATTACH_DECL2_NEW(auich, sizeof(struct auich_softc), 256 auich_match, auich_attach, auich_detach, NULL, NULL, auich_childdet); 257 258 static int auich_open(void *, int); 259 static void auich_close(void *); 260 static int auich_query_encoding(void *, struct audio_encoding *); 261 static int auich_set_params(void *, int, int, audio_params_t *, 262 audio_params_t *, stream_filter_list_t *, 263 stream_filter_list_t *); 264 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 265 static void auich_halt_pipe(struct auich_softc *, int); 266 static int auich_halt_output(void *); 267 static int auich_halt_input(void *); 268 static int auich_getdev(void *, struct audio_device *); 269 static int auich_set_port(void *, mixer_ctrl_t *); 270 static int auich_get_port(void *, mixer_ctrl_t *); 271 static int auich_query_devinfo(void *, mixer_devinfo_t *); 272 static void *auich_allocm(void *, int, size_t); 273 static void auich_freem(void *, void *, size_t); 274 static size_t auich_round_buffersize(void *, int, size_t); 275 static paddr_t auich_mappage(void *, void *, off_t, int); 276 static int auich_get_props(void *); 277 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 278 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 279 static int auich_trigger_output(void *, void *, void *, int, 280 void (*)(void *), void *, const audio_params_t *); 281 static int auich_trigger_input(void *, void *, void *, int, 282 void (*)(void *), void *, const audio_params_t *); 283 static void auich_get_locks(void *, kmutex_t **, kmutex_t **); 284 285 static int auich_alloc_cdata(struct auich_softc *); 286 287 static int auich_allocmem(struct auich_softc *, size_t, size_t, 288 struct auich_dma *); 289 static int auich_freemem(struct auich_softc *, struct auich_dma *); 290 291 static bool auich_resume(device_t, const pmf_qual_t *); 292 static int auich_set_rate(struct auich_softc *, int, u_long); 293 static int auich_sysctl_verify(SYSCTLFN_ARGS); 294 static void auich_finish_attach(device_t); 295 static void auich_calibrate(struct auich_softc *); 296 static void auich_clear_cas(struct auich_softc *); 297 298 static int auich_attach_codec(void *, struct ac97_codec_if *); 299 static int auich_read_codec(void *, uint8_t, uint16_t *); 300 static int auich_write_codec(void *, uint8_t, uint16_t); 301 static int auich_reset_codec(void *); 302 static enum ac97_host_flags auich_flags_codec(void *); 303 static void auich_spdif_event(void *, bool); 304 305 static const struct audio_hw_if auich_hw_if = { 306 auich_open, 307 auich_close, 308 NULL, /* drain */ 309 auich_query_encoding, 310 auich_set_params, 311 auich_round_blocksize, 312 NULL, /* commit_setting */ 313 NULL, /* init_output */ 314 NULL, /* init_input */ 315 NULL, /* start_output */ 316 NULL, /* start_input */ 317 auich_halt_output, 318 auich_halt_input, 319 NULL, /* speaker_ctl */ 320 auich_getdev, 321 NULL, /* getfd */ 322 auich_set_port, 323 auich_get_port, 324 auich_query_devinfo, 325 auich_allocm, 326 auich_freem, 327 auich_round_buffersize, 328 auich_mappage, 329 auich_get_props, 330 auich_trigger_output, 331 auich_trigger_input, 332 NULL, /* dev_ioctl */ 333 auich_get_locks, 334 }; 335 336 #define AUICH_FORMATS_1CH 0 337 #define AUICH_FORMATS_4CH 1 338 #define AUICH_FORMATS_6CH 2 339 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 340 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 341 2, AUFMT_STEREO, 0, {8000, 48000}}, 342 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 343 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 344 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 345 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 346 }; 347 348 #define AUICH_SPDIF_NFORMATS 1 349 static const struct audio_format auich_spdif_formats[AUICH_SPDIF_NFORMATS] = { 350 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 351 2, AUFMT_STEREO, 1, {48000}}, 352 }; 353 354 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 355 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 356 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 357 }; 358 359 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 360 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 361 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 362 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 363 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 364 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 365 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 366 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 367 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 368 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 369 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 370 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 371 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 372 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 373 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 374 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 375 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 376 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 377 #define PCIID_NFORCE430 PCI_ID_CODE0(NVIDIA, NFORCE430_AC) 378 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 379 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 380 381 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 382 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 383 #define PCIID_ICH6MODEM PCI_ID_CODE0(INTEL, 82801FB_ACM) 384 385 struct auich_devtype { 386 pcireg_t id; 387 const char *name; 388 const char *shortname; /* must be less than 11 characters */ 389 }; 390 391 static const struct auich_devtype auich_audio_devices[] = { 392 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 393 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 394 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 395 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 396 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 397 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 398 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 399 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 400 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 401 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 402 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 403 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 404 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 405 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 406 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 407 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 408 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 409 { PCIID_NFORCE430, "nForce430 (MCP51) AC-97 Audio", "nForce430" }, 410 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 411 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 412 { 0, NULL, NULL }, 413 }; 414 415 static const struct auich_devtype auich_modem_devices[] = { 416 #ifdef AUICH_ATTACH_MODEM 417 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 418 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 419 { PCIID_ICH6MODEM, "i82801FB (ICH6) AC-97 Modem", "ICH6MODEM" }, 420 #endif 421 { 0, NULL, NULL }, 422 }; 423 424 static const struct auich_devtype * 425 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 426 { 427 const struct auich_devtype *d; 428 429 for (d = auich_devices; d->name != NULL; d++) { 430 if (pa->pa_id == d->id) 431 return d; 432 } 433 434 return NULL; 435 } 436 437 static int 438 auich_match(device_t parent, cfdata_t match, void *aux) 439 { 440 struct pci_attach_args *pa; 441 442 pa = aux; 443 if (auich_lookup(pa, auich_audio_devices) != NULL) 444 return 1; 445 if (auich_lookup(pa, auich_modem_devices) != NULL) 446 return 1; 447 448 return 0; 449 } 450 451 static void 452 auich_attach(device_t parent, device_t self, void *aux) 453 { 454 struct auich_softc *sc = device_private(self); 455 struct pci_attach_args *pa; 456 pcireg_t v, subdev; 457 const char *intrstr; 458 const struct auich_devtype *d; 459 const struct sysctlnode *node, *node_ac97clock; 460 int err, node_mib, i; 461 char intrbuf[PCI_INTRSTR_LEN]; 462 463 sc->sc_dev = self; 464 pa = aux; 465 466 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 467 sc->sc_modem_offset = 0x10; 468 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 469 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 470 sc->sc_modem_offset = 0; 471 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 472 } else 473 panic("auich_attach: impossible"); 474 475 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 476 aprint_naive(": Audio controller\n"); 477 else 478 aprint_naive(": Modem controller\n"); 479 480 sc->sc_pc = pa->pa_pc; 481 sc->sc_pt = pa->pa_tag; 482 483 aprint_normal(": %s\n", d->name); 484 485 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 486 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 487 || d->id == PCIID_ICH4MODEM) { 488 /* 489 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 490 */ 491 492 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 493 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 494 goto retry_map; 495 } 496 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 497 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 498 goto retry_map; 499 } 500 goto map_done; 501 } else 502 goto non_native_map; 503 504 retry_map: 505 sc->sc_iose = 1; 506 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 507 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 508 v | ICH_CFG_IOSE); 509 510 non_native_map: 511 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 512 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 513 aprint_error_dev(self, "can't map codec i/o space\n"); 514 return; 515 } 516 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 517 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 518 aprint_error_dev(self, "can't map device i/o space\n"); 519 return; 520 } 521 522 map_done: 523 sc->dmat = pa->pa_dmat; 524 525 /* enable bus mastering */ 526 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 527 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 528 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 529 530 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 531 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 532 533 /* Map and establish the interrupt. */ 534 if (pci_intr_map(pa, &sc->intrh)) { 535 aprint_error_dev(self, "can't map interrupt\n"); 536 return; 537 } 538 intrstr = pci_intr_string(pa->pa_pc, sc->intrh, intrbuf, sizeof(intrbuf)); 539 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO, 540 auich_intr, sc); 541 if (sc->sc_ih == NULL) { 542 aprint_error_dev(self, "can't establish interrupt"); 543 if (intrstr != NULL) 544 aprint_error(" at %s", intrstr); 545 aprint_error("\n"); 546 return; 547 } 548 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 549 550 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 551 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 552 "0x%02x", PCI_REVISION(pa->pa_class)); 553 strlcpy(sc->sc_audev.config, device_xname(self), MAX_AUDIO_DEV_LEN); 554 555 /* SiS 7012 needs special handling */ 556 if (d->id == PCIID_SIS7012) { 557 sc->sc_sts_reg = ICH_PICB; 558 sc->sc_sample_shift = 0; 559 sc->sc_pcm246_mask = ICH_SIS_PCM246_MASK; 560 sc->sc_pcm2 = ICH_SIS_PCM2; 561 sc->sc_pcm4 = ICH_SIS_PCM4; 562 sc->sc_pcm6 = ICH_SIS_PCM6; 563 /* Un-mute output. From Linux. */ 564 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 565 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 566 ICH_SIS_CTL_UNMUTE); 567 } else { 568 sc->sc_sts_reg = ICH_STS; 569 sc->sc_sample_shift = 1; 570 sc->sc_pcm246_mask = ICH_PCM246_MASK; 571 sc->sc_pcm2 = ICH_PCM2; 572 sc->sc_pcm4 = ICH_PCM4; 573 sc->sc_pcm6 = ICH_PCM6; 574 } 575 576 /* Workaround for a 440MX B-stepping erratum */ 577 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 578 if (d->id == PCIID_440MX) { 579 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 580 aprint_normal_dev(self, "DMA bug workaround enabled\n"); 581 } 582 583 /* Set up DMA lists. */ 584 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 585 auich_alloc_cdata(sc); 586 587 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 588 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 589 590 /* Modem codecs are always the secondary codec on ICH */ 591 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 592 593 sc->host_if.arg = sc; 594 sc->host_if.attach = auich_attach_codec; 595 sc->host_if.read = auich_read_codec; 596 sc->host_if.write = auich_write_codec; 597 sc->host_if.reset = auich_reset_codec; 598 sc->host_if.flags = auich_flags_codec; 599 sc->host_if.spdif_event = auich_spdif_event; 600 601 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 602 switch (subdev) { 603 case 0x202f161f: /* Gateway 7326GZ */ 604 case 0x203a161f: /* Gateway 4028GZ */ 605 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 606 case 0x8144104d: /* Sony VAIO PCG-TR* */ 607 case 0x8197104d: /* Sony S1XP */ 608 case 0x81c0104d: /* Sony VAIO type T */ 609 case 0x81c5104d: /* Sony VAIO VGN-B1XP */ 610 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP; 611 break; 612 default: 613 sc->sc_codecflags = 0; 614 break; 615 } 616 617 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype, 618 &sc->sc_lock) != 0) 619 return; 620 621 mutex_enter(&sc->sc_lock); 622 sc->codec_if->vtbl->unlock(sc->codec_if); 623 sc->sc_fixedrate = AC97_IS_FIXED_RATE(sc->codec_if); 624 625 /* setup audio_format */ 626 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 627 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 628 if (!AC97_IS_4CH(sc->codec_if)) 629 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 630 if (!AC97_IS_6CH(sc->codec_if)) 631 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 632 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 633 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 634 sc->sc_audio_formats[i].frequency_type = 1; 635 sc->sc_audio_formats[i].frequency[0] = 48000; 636 } 637 } 638 mutex_exit(&sc->sc_lock); 639 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 640 &sc->sc_encodings)) 641 return; 642 if (0 != auconv_create_encodings(auich_spdif_formats, AUICH_SPDIF_NFORMATS, 643 &sc->sc_spdif_encodings)) 644 return; 645 } else { 646 mutex_exit(&sc->sc_lock); 647 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 648 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 649 &sc->sc_encodings)) 650 return; 651 } 652 653 /* Watch for power change */ 654 if (!pmf_device_register(self, NULL, auich_resume)) 655 aprint_error_dev(self, "couldn't establish power handler\n"); 656 657 config_interrupts(self, auich_finish_attach); 658 659 /* sysctl setup */ 660 if (sc->sc_fixedrate && sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 661 return; 662 663 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 664 CTLTYPE_NODE, device_xname(self), NULL, NULL, 0, 665 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 666 if (err != 0) 667 goto sysctl_err; 668 node_mib = node->sysctl_num; 669 670 if (!sc->sc_fixedrate) { 671 /* passing the sc address instead of &sc->sc_ac97_clock */ 672 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 673 CTLFLAG_READWRITE, 674 CTLTYPE_INT, "ac97rate", 675 SYSCTL_DESCR("AC'97 codec link rate"), 676 auich_sysctl_verify, 0, (void *)sc, 0, 677 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 678 if (err != 0) 679 goto sysctl_err; 680 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 681 } 682 683 return; 684 685 sysctl_err: 686 printf("%s: failed to add sysctl nodes. (%d)\n", 687 device_xname(self), err); 688 return; /* failure of sysctl is not fatal. */ 689 } 690 691 static void 692 auich_childdet(device_t self, device_t child) 693 { 694 struct auich_softc *sc = device_private(self); 695 696 KASSERT(sc->sc_audiodev == child); 697 sc->sc_audiodev = NULL; 698 } 699 700 static int 701 auich_detach(device_t self, int flags) 702 { 703 struct auich_softc *sc = device_private(self); 704 705 /* audio */ 706 if (sc->sc_audiodev != NULL) 707 config_detach(sc->sc_audiodev, flags); 708 709 /* sysctl */ 710 sysctl_teardown(&sc->sc_log); 711 712 mutex_enter(&sc->sc_lock); 713 714 /* audio_encoding_set */ 715 auconv_delete_encodings(sc->sc_encodings); 716 auconv_delete_encodings(sc->sc_spdif_encodings); 717 718 /* ac97 */ 719 if (sc->codec_if != NULL) 720 sc->codec_if->vtbl->detach(sc->codec_if); 721 722 mutex_exit(&sc->sc_lock); 723 mutex_destroy(&sc->sc_lock); 724 mutex_destroy(&sc->sc_intr_lock); 725 726 /* PCI */ 727 if (sc->sc_ih != NULL) 728 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 729 if (sc->mix_size != 0) 730 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 731 if (sc->aud_size != 0) 732 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 733 return 0; 734 } 735 736 static int 737 auich_sysctl_verify(SYSCTLFN_ARGS) 738 { 739 int error, tmp; 740 struct sysctlnode node; 741 struct auich_softc *sc; 742 743 node = *rnode; 744 sc = rnode->sysctl_data; 745 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 746 tmp = sc->sc_ac97_clock; 747 node.sysctl_data = &tmp; 748 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 749 if (error || newp == NULL) 750 return error; 751 752 if (tmp < 48000 || tmp > 96000) 753 return EINVAL; 754 mutex_enter(&sc->sc_lock); 755 sc->sc_ac97_clock = tmp; 756 mutex_exit(&sc->sc_lock); 757 } 758 759 return 0; 760 } 761 762 static void 763 auich_finish_attach(device_t self) 764 { 765 struct auich_softc *sc = device_private(self); 766 767 mutex_enter(&sc->sc_lock); 768 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 769 auich_calibrate(sc); 770 mutex_exit(&sc->sc_lock); 771 772 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, sc->sc_dev); 773 774 return; 775 } 776 777 #define ICH_CODECIO_INTERVAL 10 778 static int 779 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 780 { 781 struct auich_softc *sc; 782 int i; 783 uint32_t status; 784 785 sc = v; 786 /* wait for an access semaphore */ 787 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 788 bus_space_read_1(sc->iot, sc->aud_ioh, 789 ICH_CAS + sc->sc_modem_offset) & 1; 790 DELAY(ICH_CODECIO_INTERVAL)); 791 792 if (i > 0) { 793 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 794 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 795 DPRINTF(ICH_DEBUG_CODECIO, 796 ("auich_read_codec(%x, %x)\n", reg, *val)); 797 status = bus_space_read_4(sc->iot, sc->aud_ioh, 798 ICH_GSTS + sc->sc_modem_offset); 799 if (status & ICH_RCS) { 800 bus_space_write_4(sc->iot, sc->aud_ioh, 801 ICH_GSTS + sc->sc_modem_offset, 802 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 803 *val = 0xffff; 804 DPRINTF(ICH_DEBUG_CODECIO, 805 ("%s: read_codec error\n", device_xname(sc->sc_dev))); 806 if (reg == AC97_REG_GPIO_STATUS) 807 auich_clear_cas(sc); 808 return -1; 809 } 810 if (reg == AC97_REG_GPIO_STATUS) 811 auich_clear_cas(sc); 812 return 0; 813 } else { 814 aprint_normal_dev(sc->sc_dev, "read_codec timeout\n"); 815 if (reg == AC97_REG_GPIO_STATUS) 816 auich_clear_cas(sc); 817 return -1; 818 } 819 } 820 821 static int 822 auich_write_codec(void *v, uint8_t reg, uint16_t val) 823 { 824 struct auich_softc *sc; 825 int i; 826 827 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 828 sc = v; 829 /* wait for an access semaphore */ 830 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 831 bus_space_read_1(sc->iot, sc->aud_ioh, 832 ICH_CAS + sc->sc_modem_offset) & 1; 833 DELAY(ICH_CODECIO_INTERVAL)); 834 835 if (i > 0) { 836 bus_space_write_2(sc->iot, sc->mix_ioh, 837 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 838 return 0; 839 } else { 840 aprint_normal_dev(sc->sc_dev, "write_codec timeout\n"); 841 return -1; 842 } 843 } 844 845 static int 846 auich_attach_codec(void *v, struct ac97_codec_if *cif) 847 { 848 struct auich_softc *sc; 849 850 sc = v; 851 sc->codec_if = cif; 852 853 return 0; 854 } 855 856 static int 857 auich_reset_codec(void *v) 858 { 859 struct auich_softc *sc; 860 int i; 861 uint32_t control, status; 862 863 sc = v; 864 control = bus_space_read_4(sc->iot, sc->aud_ioh, 865 ICH_GCTRL + sc->sc_modem_offset); 866 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 867 control &= ~(ICH_ACLSO | sc->sc_pcm246_mask); 868 } else { 869 control &= ~ICH_ACLSO; 870 control |= ICH_GIE; 871 } 872 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 873 bus_space_write_4(sc->iot, sc->aud_ioh, 874 ICH_GCTRL + sc->sc_modem_offset, control); 875 876 for (i = 500000; i >= 0; i--) { 877 status = bus_space_read_4(sc->iot, sc->aud_ioh, 878 ICH_GSTS + sc->sc_modem_offset); 879 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 880 break; 881 DELAY(1); 882 } 883 if (i <= 0) { 884 aprint_error_dev(sc->sc_dev, "auich_reset_codec: time out\n"); 885 return ETIMEDOUT; 886 } 887 #ifdef AUICH_DEBUG 888 if (status & ICH_SCR) 889 printf("%s: The 2nd codec is ready.\n", 890 device_xname(sc->sc_dev)); 891 if (status & ICH_S2CR) 892 printf("%s: The 3rd codec is ready.\n", 893 device_xname(sc->sc_dev)); 894 #endif 895 return 0; 896 } 897 898 static enum ac97_host_flags 899 auich_flags_codec(void *v) 900 { 901 struct auich_softc *sc = v; 902 return sc->sc_codecflags; 903 } 904 905 static void 906 auich_spdif_event(void *addr, bool flag) 907 { 908 struct auich_softc *sc; 909 910 sc = addr; 911 sc->sc_spdif = flag; 912 } 913 914 static int 915 auich_open(void *addr, int flags) 916 { 917 struct auich_softc *sc; 918 919 sc = (struct auich_softc *)addr; 920 mutex_spin_exit(&sc->sc_intr_lock); 921 sc->codec_if->vtbl->lock(sc->codec_if); 922 mutex_spin_enter(&sc->sc_intr_lock); 923 return 0; 924 } 925 926 static void 927 auich_close(void *addr) 928 { 929 struct auich_softc *sc; 930 931 sc = (struct auich_softc *)addr; 932 mutex_spin_exit(&sc->sc_intr_lock); 933 sc->codec_if->vtbl->unlock(sc->codec_if); 934 mutex_spin_enter(&sc->sc_intr_lock); 935 } 936 937 static int 938 auich_query_encoding(void *v, struct audio_encoding *aep) 939 { 940 struct auich_softc *sc; 941 942 sc = (struct auich_softc *)v; 943 return auconv_query_encoding( 944 sc->sc_spdif ? sc->sc_spdif_encodings : sc->sc_encodings, aep); 945 } 946 947 static int 948 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 949 { 950 int ret; 951 u_int ratetmp; 952 953 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 954 ratetmp = srate; 955 if (mode == AUMODE_RECORD) 956 return sc->codec_if->vtbl->set_rate(sc->codec_if, 957 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 958 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 959 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 960 if (ret) 961 return ret; 962 ratetmp = srate; 963 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 964 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 965 if (ret) 966 return ret; 967 ratetmp = srate; 968 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 969 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 970 return ret; 971 } 972 973 static int 974 auich_set_params(void *v, int setmode, int usemode, 975 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 976 stream_filter_list_t *rfil) 977 { 978 struct auich_softc *sc; 979 audio_params_t *p; 980 stream_filter_list_t *fil; 981 int mode, index; 982 uint32_t control; 983 984 sc = v; 985 for (mode = AUMODE_RECORD; mode != -1; 986 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 987 if ((setmode & mode) == 0) 988 continue; 989 990 p = mode == AUMODE_PLAY ? play : rec; 991 fil = mode == AUMODE_PLAY ? pfil : rfil; 992 if (p == NULL) 993 continue; 994 995 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 996 if (p->sample_rate < 8000 || 997 p->sample_rate > 48000) 998 return EINVAL; 999 1000 if (!sc->sc_spdif) 1001 index = auconv_set_converter(sc->sc_audio_formats, 1002 AUICH_AUDIO_NFORMATS, mode, p, TRUE, fil); 1003 else 1004 index = auconv_set_converter(auich_spdif_formats, 1005 AUICH_SPDIF_NFORMATS, mode, p, TRUE, fil); 1006 } else { 1007 if (p->sample_rate != 8000 && p->sample_rate != 16000) 1008 return EINVAL; 1009 index = auconv_set_converter(sc->sc_modem_formats, 1010 AUICH_MODEM_NFORMATS, mode, p, TRUE, fil); 1011 } 1012 if (index < 0) 1013 return EINVAL; 1014 if (fil->req_size > 0) 1015 p = &fil->filters[0].param; 1016 /* p represents HW encoding */ 1017 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1018 if (sc->sc_audio_formats[index].frequency_type != 1 1019 && auich_set_rate(sc, mode, p->sample_rate)) 1020 return EINVAL; 1021 } else { 1022 if (sc->sc_modem_formats[index].frequency_type != 1 1023 && auich_set_rate(sc, mode, p->sample_rate)) 1024 return EINVAL; 1025 auich_write_codec(sc, AC97_REG_LINE1_RATE, 1026 p->sample_rate); 1027 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 1028 } 1029 if (mode == AUMODE_PLAY && 1030 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1031 control = bus_space_read_4(sc->iot, sc->aud_ioh, 1032 ICH_GCTRL + sc->sc_modem_offset); 1033 control &= ~sc->sc_pcm246_mask; 1034 if (p->channels == 4) { 1035 control |= sc->sc_pcm4; 1036 } else if (p->channels == 6) { 1037 control |= sc->sc_pcm6; 1038 } 1039 bus_space_write_4(sc->iot, sc->aud_ioh, 1040 ICH_GCTRL + sc->sc_modem_offset, control); 1041 } 1042 } 1043 1044 return 0; 1045 } 1046 1047 static int 1048 auich_round_blocksize(void *v, int blk, int mode, 1049 const audio_params_t *param) 1050 { 1051 1052 return blk & ~0x3f; /* keep good alignment */ 1053 } 1054 1055 static void 1056 auich_halt_pipe(struct auich_softc *sc, int pipe) 1057 { 1058 int i; 1059 uint32_t status; 1060 1061 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 1062 for (i = 0; i < 100; i++) { 1063 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 1064 if (status & ICH_DCH) 1065 break; 1066 DELAY(1); 1067 } 1068 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 1069 1070 #if AUICH_DEBUG 1071 if (i > 0) 1072 printf("auich_halt_pipe: halt took %d cycles\n", i); 1073 #endif 1074 } 1075 1076 static int 1077 auich_halt_output(void *v) 1078 { 1079 struct auich_softc *sc; 1080 1081 sc = v; 1082 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", device_xname(sc->sc_dev))); 1083 1084 auich_halt_pipe(sc, ICH_PCMO); 1085 sc->pcmo.intr = NULL; 1086 1087 return 0; 1088 } 1089 1090 static int 1091 auich_halt_input(void *v) 1092 { 1093 struct auich_softc *sc; 1094 1095 sc = v; 1096 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", device_xname(sc->sc_dev))); 1097 1098 auich_halt_pipe(sc, ICH_PCMI); 1099 sc->pcmi.intr = NULL; 1100 1101 return 0; 1102 } 1103 1104 static int 1105 auich_getdev(void *v, struct audio_device *adp) 1106 { 1107 struct auich_softc *sc; 1108 1109 sc = v; 1110 *adp = sc->sc_audev; 1111 return 0; 1112 } 1113 1114 static int 1115 auich_set_port(void *v, mixer_ctrl_t *cp) 1116 { 1117 struct auich_softc *sc; 1118 1119 sc = v; 1120 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1121 } 1122 1123 static int 1124 auich_get_port(void *v, mixer_ctrl_t *cp) 1125 { 1126 struct auich_softc *sc; 1127 1128 sc = v; 1129 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1130 } 1131 1132 static int 1133 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1134 { 1135 struct auich_softc *sc; 1136 1137 sc = v; 1138 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1139 } 1140 1141 static void * 1142 auich_allocm(void *v, int direction, size_t size) 1143 { 1144 struct auich_softc *sc; 1145 struct auich_dma *p; 1146 int error; 1147 1148 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1149 return NULL; 1150 1151 p = kmem_alloc(sizeof(*p), KM_SLEEP); 1152 if (p == NULL) 1153 return NULL; 1154 1155 sc = v; 1156 error = auich_allocmem(sc, size, 0, p); 1157 if (error) { 1158 kmem_free(p, sizeof(*p)); 1159 return NULL; 1160 } 1161 1162 p->next = sc->sc_dmas; 1163 sc->sc_dmas = p; 1164 1165 return KERNADDR(p); 1166 } 1167 1168 static void 1169 auich_freem(void *v, void *ptr, size_t size) 1170 { 1171 struct auich_softc *sc; 1172 struct auich_dma *p, **pp; 1173 1174 sc = v; 1175 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1176 if (KERNADDR(p) == ptr) { 1177 auich_freemem(sc, p); 1178 *pp = p->next; 1179 kmem_free(p, sizeof(*p)); 1180 return; 1181 } 1182 } 1183 } 1184 1185 static size_t 1186 auich_round_buffersize(void *v, int direction, size_t size) 1187 { 1188 1189 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1190 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1191 1192 return size; 1193 } 1194 1195 static paddr_t 1196 auich_mappage(void *v, void *mem, off_t off, int prot) 1197 { 1198 struct auich_softc *sc; 1199 struct auich_dma *p; 1200 1201 if (off < 0) 1202 return -1; 1203 sc = v; 1204 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1205 continue; 1206 if (!p) 1207 return -1; 1208 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1209 off, prot, BUS_DMA_WAITOK); 1210 } 1211 1212 static int 1213 auich_get_props(void *v) 1214 { 1215 struct auich_softc *sc; 1216 int props; 1217 1218 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1219 sc = v; 1220 /* 1221 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1222 * rate because of aurateconv. Applications can't know what rate the 1223 * device can process in the case of mmap(). 1224 */ 1225 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1226 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1227 props |= AUDIO_PROP_MMAP; 1228 return props; 1229 } 1230 1231 static int 1232 auich_intr(void *v) 1233 { 1234 struct auich_softc *sc; 1235 int ret, gsts; 1236 #ifdef DIAGNOSTIC 1237 int csts; 1238 #endif 1239 1240 sc = v; 1241 1242 if (!device_has_power(sc->sc_dev)) 1243 return (0); 1244 1245 mutex_spin_enter(&sc->sc_intr_lock); 1246 1247 ret = 0; 1248 #ifdef DIAGNOSTIC 1249 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1250 if (csts & PCI_STATUS_MASTER_ABORT) { 1251 printf("auich_intr: PCI master abort\n"); 1252 } 1253 #endif 1254 1255 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1256 ICH_GSTS + sc->sc_modem_offset); 1257 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1258 1259 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1260 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1261 int sts; 1262 1263 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1264 ICH_PCMO + sc->sc_sts_reg); 1265 DPRINTF(ICH_DEBUG_INTR, 1266 ("auich_intr: osts=0x%x\n", sts)); 1267 1268 if (sts & ICH_FIFOE) 1269 printf("%s: fifo underrun\n", device_xname(sc->sc_dev)); 1270 1271 if (sts & ICH_BCIS) 1272 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1273 1274 /* int ack */ 1275 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1276 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1277 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1278 bus_space_write_4(sc->iot, sc->aud_ioh, 1279 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1280 else 1281 bus_space_write_4(sc->iot, sc->aud_ioh, 1282 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1283 ret++; 1284 } 1285 1286 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1287 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1288 int sts; 1289 1290 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1291 ICH_PCMI + sc->sc_sts_reg); 1292 DPRINTF(ICH_DEBUG_INTR, 1293 ("auich_intr: ists=0x%x\n", sts)); 1294 1295 if (sts & ICH_FIFOE) 1296 printf("%s: fifo overrun\n", device_xname(sc->sc_dev)); 1297 1298 if (sts & ICH_BCIS) 1299 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1300 1301 /* int ack */ 1302 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1303 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1304 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1305 bus_space_write_4(sc->iot, sc->aud_ioh, 1306 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1307 else 1308 bus_space_write_4(sc->iot, sc->aud_ioh, 1309 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1310 ret++; 1311 } 1312 1313 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1314 int sts; 1315 1316 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1317 ICH_MICI + sc->sc_sts_reg); 1318 DPRINTF(ICH_DEBUG_INTR, 1319 ("auich_intr: ists=0x%x\n", sts)); 1320 1321 if (sts & ICH_FIFOE) 1322 printf("%s: fifo overrun\n", device_xname(sc->sc_dev)); 1323 1324 if (sts & ICH_BCIS) 1325 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1326 1327 /* int ack */ 1328 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1329 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1330 bus_space_write_4(sc->iot, sc->aud_ioh, 1331 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1332 ret++; 1333 } 1334 1335 #ifdef AUICH_MODEM_DEBUG 1336 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1337 printf("%s: gsts=0x%x\n", device_xname(sc->sc_dev), gsts); 1338 /* int ack */ 1339 bus_space_write_4(sc->iot, sc->aud_ioh, 1340 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1341 ret++; 1342 } 1343 #endif 1344 1345 mutex_spin_exit(&sc->sc_intr_lock); 1346 1347 return ret; 1348 } 1349 1350 static void 1351 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1352 { 1353 int blksize, qptr; 1354 struct auich_dmalist *q; 1355 1356 blksize = ring->blksize; 1357 1358 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1359 q = &ring->dmalist[qptr]; 1360 q->base = ring->p; 1361 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1362 1363 ring->p += blksize; 1364 if (ring->p >= ring->end) 1365 ring->p = ring->start; 1366 } 1367 ring->qptr = 0; 1368 1369 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1370 (qptr - 1) & ICH_LVI_MASK); 1371 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1372 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1373 } 1374 1375 static void 1376 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1377 { 1378 int blksize, qptr, nqptr; 1379 struct auich_dmalist *q; 1380 1381 blksize = ring->blksize; 1382 qptr = ring->qptr; 1383 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1384 1385 while (qptr != nqptr) { 1386 q = &ring->dmalist[qptr]; 1387 q->base = ring->p; 1388 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1389 1390 DPRINTF(ICH_DEBUG_INTR, 1391 ("auich_intr: %p, %p = %x @ 0x%x\n", 1392 &ring->dmalist[qptr], q, q->len, q->base)); 1393 1394 ring->p += blksize; 1395 if (ring->p >= ring->end) 1396 ring->p = ring->start; 1397 1398 qptr = (qptr + 1) & ICH_LVI_MASK; 1399 if (ring->intr) 1400 ring->intr(ring->arg); 1401 } 1402 ring->qptr = qptr; 1403 1404 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1405 (qptr - 1) & ICH_LVI_MASK); 1406 } 1407 1408 static int 1409 auich_trigger_output(void *v, void *start, void *end, int blksize, 1410 void (*intr)(void *), void *arg, const audio_params_t *param) 1411 { 1412 struct auich_softc *sc; 1413 struct auich_dma *p; 1414 size_t size; 1415 1416 DPRINTF(ICH_DEBUG_DMA, 1417 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1418 start, end, blksize, intr, arg, param)); 1419 sc = v; 1420 1421 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1422 continue; 1423 if (!p) { 1424 printf("auich_trigger_output: bad addr %p\n", start); 1425 return EINVAL; 1426 } 1427 1428 size = (size_t)((char *)end - (char *)start); 1429 1430 sc->pcmo.intr = intr; 1431 sc->pcmo.arg = arg; 1432 sc->pcmo.start = DMAADDR(p); 1433 sc->pcmo.p = sc->pcmo.start; 1434 sc->pcmo.end = sc->pcmo.start + size; 1435 sc->pcmo.blksize = blksize; 1436 1437 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1438 sc->sc_cddma + ICH_PCMO_OFF(0)); 1439 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1440 1441 return 0; 1442 } 1443 1444 static int 1445 auich_trigger_input(void *v, void *start, void *end, int blksize, 1446 void (*intr)(void *), void *arg, const audio_params_t *param) 1447 { 1448 struct auich_softc *sc; 1449 struct auich_dma *p; 1450 size_t size; 1451 1452 DPRINTF(ICH_DEBUG_DMA, 1453 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1454 start, end, blksize, intr, arg, param)); 1455 sc = v; 1456 1457 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1458 continue; 1459 if (!p) { 1460 printf("auich_trigger_input: bad addr %p\n", start); 1461 return EINVAL; 1462 } 1463 1464 size = (size_t)((char *)end - (char *)start); 1465 1466 sc->pcmi.intr = intr; 1467 sc->pcmi.arg = arg; 1468 sc->pcmi.start = DMAADDR(p); 1469 sc->pcmi.p = sc->pcmi.start; 1470 sc->pcmi.end = sc->pcmi.start + size; 1471 sc->pcmi.blksize = blksize; 1472 1473 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1474 sc->sc_cddma + ICH_PCMI_OFF(0)); 1475 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1476 1477 return 0; 1478 } 1479 1480 static int 1481 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1482 struct auich_dma *p) 1483 { 1484 int error; 1485 1486 p->size = size; 1487 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1488 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1489 &p->nsegs, BUS_DMA_WAITOK); 1490 if (error) 1491 return error; 1492 1493 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1494 &p->addr, BUS_DMA_WAITOK|sc->sc_dmamap_flags); 1495 if (error) 1496 goto free; 1497 1498 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1499 0, BUS_DMA_WAITOK, &p->map); 1500 if (error) 1501 goto unmap; 1502 1503 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1504 BUS_DMA_WAITOK); 1505 if (error) 1506 goto destroy; 1507 return 0; 1508 1509 destroy: 1510 bus_dmamap_destroy(sc->dmat, p->map); 1511 unmap: 1512 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1513 free: 1514 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1515 return error; 1516 } 1517 1518 static int 1519 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1520 { 1521 1522 bus_dmamap_unload(sc->dmat, p->map); 1523 bus_dmamap_destroy(sc->dmat, p->map); 1524 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1525 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1526 return 0; 1527 } 1528 1529 static int 1530 auich_alloc_cdata(struct auich_softc *sc) 1531 { 1532 bus_dma_segment_t seg; 1533 int error, rseg; 1534 1535 /* 1536 * Allocate the control data structure, and create and load the 1537 * DMA map for it. 1538 */ 1539 if ((error = bus_dmamem_alloc(sc->dmat, 1540 sizeof(struct auich_cdata), 1541 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1542 aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n", error); 1543 goto fail_0; 1544 } 1545 1546 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1547 sizeof(struct auich_cdata), 1548 (void **) &sc->sc_cdata, 1549 sc->sc_dmamap_flags)) != 0) { 1550 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", error); 1551 goto fail_1; 1552 } 1553 1554 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1555 sizeof(struct auich_cdata), 0, 0, 1556 &sc->sc_cddmamap)) != 0) { 1557 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 1558 "error = %d\n", error); 1559 goto fail_2; 1560 } 1561 1562 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1563 sc->sc_cdata, sizeof(struct auich_cdata), 1564 NULL, 0)) != 0) { 1565 aprint_error_dev(sc->sc_dev, "unable tp load control data DMA map, " 1566 "error = %d\n", error); 1567 goto fail_3; 1568 } 1569 1570 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1571 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1572 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1573 1574 return 0; 1575 1576 fail_3: 1577 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1578 fail_2: 1579 bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata, 1580 sizeof(struct auich_cdata)); 1581 fail_1: 1582 bus_dmamem_free(sc->dmat, &seg, rseg); 1583 fail_0: 1584 return error; 1585 } 1586 1587 static bool 1588 auich_resume(device_t dv, const pmf_qual_t *qual) 1589 { 1590 struct auich_softc *sc = device_private(dv); 1591 pcireg_t v; 1592 1593 mutex_enter(&sc->sc_lock); 1594 mutex_spin_enter(&sc->sc_intr_lock); 1595 1596 if (sc->sc_iose) { 1597 v = pci_conf_read(sc->sc_pc, sc->sc_pt, ICH_CFG); 1598 pci_conf_write(sc->sc_pc, sc->sc_pt, ICH_CFG, 1599 v | ICH_CFG_IOSE); 1600 } 1601 1602 auich_reset_codec(sc); 1603 mutex_spin_exit(&sc->sc_intr_lock); 1604 DELAY(1000); 1605 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1606 mutex_exit(&sc->sc_lock); 1607 1608 return true; 1609 } 1610 1611 /* 1612 * Calibrate card (some boards are overclocked and need scaling) 1613 */ 1614 static void 1615 auich_calibrate(struct auich_softc *sc) 1616 { 1617 struct timeval t1, t2; 1618 uint8_t ociv, nciv; 1619 uint64_t wait_us; 1620 uint32_t actual_48k_rate, bytes, ac97rate; 1621 void *temp_buffer; 1622 struct auich_dma *p; 1623 u_int rate; 1624 1625 /* 1626 * Grab audio from input for fixed interval and compare how 1627 * much we actually get with what we expect. Interval needs 1628 * to be sufficiently short that no interrupts are 1629 * generated. 1630 */ 1631 1632 /* Force the codec to a known state first. */ 1633 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1634 rate = sc->sc_ac97_clock = 48000; 1635 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1636 &rate); 1637 1638 /* Setup a buffer */ 1639 bytes = 64000; 1640 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes); 1641 1642 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1643 continue; 1644 if (p == NULL) { 1645 printf("auich_calibrate: bad address %p\n", temp_buffer); 1646 return; 1647 } 1648 sc->pcmi.dmalist[0].base = DMAADDR(p); 1649 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1650 1651 /* 1652 * our data format is stereo, 16 bit so each sample is 4 bytes. 1653 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1654 * we're going to start recording with interrupts disabled and measure 1655 * the time taken for one block to complete. we know the block size, 1656 * we know the time in microseconds, we calculate the sample rate: 1657 * 1658 * actual_rate [bps] = bytes / (time [s] * 4) 1659 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1660 * actual_rate [Hz] = (bytes * 250000) / time [us] 1661 */ 1662 1663 /* prepare */ 1664 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1665 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1666 sc->sc_cddma + ICH_PCMI_OFF(0)); 1667 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1668 (0 - 1) & ICH_LVI_MASK); 1669 1670 /* start */ 1671 kpreempt_disable(); 1672 microtime(&t1); 1673 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1674 1675 /* wait */ 1676 nciv = ociv; 1677 do { 1678 microtime(&t2); 1679 if (t2.tv_sec - t1.tv_sec > 1) 1680 break; 1681 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1682 ICH_PCMI + ICH_CIV); 1683 } while (nciv == ociv); 1684 microtime(&t2); 1685 1686 /* stop */ 1687 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1688 kpreempt_enable(); 1689 1690 /* reset */ 1691 DELAY(100); 1692 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1693 1694 /* turn time delta into us */ 1695 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1696 1697 auich_freem(sc, temp_buffer, bytes); 1698 1699 if (nciv == ociv) { 1700 printf("%s: ac97 link rate calibration timed out after %" 1701 PRIu64 " us\n", device_xname(sc->sc_dev), wait_us); 1702 return; 1703 } 1704 1705 rnd_add_data(NULL, &wait_us, sizeof(wait_us), 1); 1706 1707 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1708 1709 if (actual_48k_rate < 50000) 1710 ac97rate = 48000; 1711 else 1712 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1713 1714 aprint_verbose_dev(sc->sc_dev, "measured ac97 link rate at %d Hz", 1715 actual_48k_rate); 1716 if (ac97rate != actual_48k_rate) 1717 aprint_verbose(", will use %d Hz", ac97rate); 1718 aprint_verbose("\n"); 1719 1720 sc->sc_ac97_clock = ac97rate; 1721 } 1722 1723 static void 1724 auich_clear_cas(struct auich_softc *sc) 1725 { 1726 /* Clear the codec access semaphore */ 1727 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1728 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1729 1730 return; 1731 } 1732 1733 static void 1734 auich_get_locks(void *addr, kmutex_t **intr, kmutex_t **thread) 1735 { 1736 struct auich_softc *sc; 1737 1738 sc = addr; 1739 *intr = &sc->sc_intr_lock; 1740 *thread = &sc->sc_lock; 1741 } 1742
Indexes created Wed Oct 22 13:09:56 GMT 2025