auich.c revision 1.16
1 /* $NetBSD: auich.c,v 1.16 2002/03/23 17:17:11 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* #define ICH_DEBUG */ 70 /* 71 * AC'97 audio found on Intel 810/820/440MX chipsets. 72 * http://developer.intel.com/design/chipsets/datashts/290655.htm 73 * http://developer.intel.com/design/chipsets/manuals/298028.htm 74 * 75 * TODO: 76 * 77 * - Probe codecs for supported sample rates. 78 * 79 * - Add support for the microphone input. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.16 2002/03/23 17:17:11 kent Exp $"); 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/malloc.h> 89 #include <sys/device.h> 90 #include <sys/fcntl.h> 91 #include <sys/proc.h> 92 93 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 94 95 #include <dev/pci/pcidevs.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/auichreg.h> 98 99 #include <sys/audioio.h> 100 #include <dev/audio_if.h> 101 #include <dev/mulaw.h> 102 #include <dev/auconv.h> 103 104 #include <machine/bus.h> 105 106 #include <dev/ic/ac97reg.h> 107 #include <dev/ic/ac97var.h> 108 109 struct auich_dma { 110 bus_dmamap_t map; 111 caddr_t addr; 112 bus_dma_segment_t segs[1]; 113 int nsegs; 114 size_t size; 115 struct auich_dma *next; 116 }; 117 118 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 119 #define KERNADDR(p) ((void *)((p)->addr)) 120 121 struct auich_cdata { 122 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 123 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 124 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 125 }; 126 127 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 128 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 129 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 130 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 131 132 struct auich_softc { 133 struct device sc_dev; 134 void *sc_ih; 135 136 audio_device_t sc_audev; 137 138 bus_space_tag_t iot; 139 bus_space_handle_t mix_ioh; 140 bus_space_handle_t aud_ioh; 141 bus_dma_tag_t dmat; 142 143 struct ac97_codec_if *codec_if; 144 struct ac97_host_if host_if; 145 146 /* DMA scatter-gather lists. */ 147 bus_dmamap_t sc_cddmamap; 148 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 149 150 struct auich_cdata *sc_cdata; 151 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 152 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 153 #define dmalist_mici sc_cdata->ic_dmalist_mici 154 155 int ptr_pcmo, 156 ptr_pcmi, 157 ptr_mici; 158 159 /* i/o buffer pointers */ 160 u_int32_t pcmo_start, pcmo_p, pcmo_end; 161 int pcmo_blksize, pcmo_fifoe; 162 163 u_int32_t pcmi_start, pcmi_p, pcmi_end; 164 int pcmi_blksize, pcmi_fifoe; 165 166 u_int32_t mici_start, mici_p, mici_end; 167 int mici_blksize, mici_fifoe; 168 169 struct auich_dma *sc_dmas; 170 171 int sc_fixed_rate; 172 173 void (*sc_pintr)(void *); 174 void *sc_parg; 175 176 void (*sc_rintr)(void *); 177 void *sc_rarg; 178 179 /* Power Management */ 180 void *sc_powerhook; 181 int sc_suspend; 182 u_int16_t ext_status; 183 }; 184 185 /* Debug */ 186 #ifdef AUDIO_DEBUG 187 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 188 int auich_debug = 0xfffe; 189 #define ICH_DEBUG_CODECIO 0x0001 190 #define ICH_DEBUG_DMA 0x0002 191 #define ICH_DEBUG_PARAM 0x0004 192 #else 193 #define DPRINTF(x,y) /* nothing */ 194 #endif 195 196 int auich_match(struct device *, struct cfdata *, void *); 197 void auich_attach(struct device *, struct device *, void *); 198 int auich_intr(void *); 199 200 struct cfattach auich_ca = { 201 sizeof(struct auich_softc), auich_match, auich_attach 202 }; 203 204 int auich_open(void *, int); 205 void auich_close(void *); 206 int auich_query_encoding(void *, struct audio_encoding *); 207 int auich_set_params(void *, int, int, struct audio_params *, 208 struct audio_params *); 209 int auich_round_blocksize(void *, int); 210 int auich_halt_output(void *); 211 int auich_halt_input(void *); 212 int auich_getdev(void *, struct audio_device *); 213 int auich_set_port(void *, mixer_ctrl_t *); 214 int auich_get_port(void *, mixer_ctrl_t *); 215 int auich_query_devinfo(void *, mixer_devinfo_t *); 216 void *auich_allocm(void *, int, size_t, int, int); 217 void auich_freem(void *, void *, int); 218 size_t auich_round_buffersize(void *, int, size_t); 219 paddr_t auich_mappage(void *, void *, off_t, int); 220 int auich_get_props(void *); 221 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 222 void *, struct audio_params *); 223 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 224 void *, struct audio_params *); 225 226 int auich_alloc_cdata(struct auich_softc *); 227 228 int auich_allocmem(struct auich_softc *, size_t, size_t, 229 struct auich_dma *); 230 int auich_freemem(struct auich_softc *, struct auich_dma *); 231 232 void auich_powerhook(int, void *); 233 234 struct audio_hw_if auich_hw_if = { 235 auich_open, 236 auich_close, 237 NULL, /* drain */ 238 auich_query_encoding, 239 auich_set_params, 240 auich_round_blocksize, 241 NULL, /* commit_setting */ 242 NULL, /* init_output */ 243 NULL, /* init_input */ 244 NULL, /* start_output */ 245 NULL, /* start_input */ 246 auich_halt_output, 247 auich_halt_input, 248 NULL, /* speaker_ctl */ 249 auich_getdev, 250 NULL, /* getfd */ 251 auich_set_port, 252 auich_get_port, 253 auich_query_devinfo, 254 auich_allocm, 255 auich_freem, 256 auich_round_buffersize, 257 auich_mappage, 258 auich_get_props, 259 auich_trigger_output, 260 auich_trigger_input, 261 NULL, /* dev_ioctl */ 262 }; 263 264 int auich_attach_codec(void *, struct ac97_codec_if *); 265 int auich_read_codec(void *, u_int8_t, u_int16_t *); 266 int auich_write_codec(void *, u_int8_t, u_int16_t); 267 void auich_reset_codec(void *); 268 269 static const struct auich_devtype { 270 int product; 271 const char *name; 272 const char *shortname; 273 } auich_devices[] = { 274 { PCI_PRODUCT_INTEL_82801AA_ACA, 275 "i82801AA (ICH) AC-97 Audio", "ICH" }, 276 { PCI_PRODUCT_INTEL_82801AB_ACA, 277 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 278 { PCI_PRODUCT_INTEL_82801BA_ACA, 279 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 280 { PCI_PRODUCT_INTEL_82440MX_ACA, 281 "i82440MX AC-97 Audio", "440MX" }, 282 { PCI_PRODUCT_INTEL_82801CA_AC, 283 "i82801CA AC-97 Audio", "i830M" }, 284 285 { 0, 286 NULL, NULL }, 287 }; 288 289 static const struct auich_devtype * 290 auich_lookup(struct pci_attach_args *pa) 291 { 292 const struct auich_devtype *d; 293 294 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 295 return (NULL); 296 297 for (d = auich_devices; d->name != NULL; d++) { 298 if (PCI_PRODUCT(pa->pa_id) == d->product) 299 return (d); 300 } 301 302 return (NULL); 303 } 304 305 int 306 auich_match(struct device *parent, struct cfdata *match, void *aux) 307 { 308 struct pci_attach_args *pa = aux; 309 310 if (auich_lookup(pa) != NULL) 311 return (1); 312 313 return (0); 314 } 315 316 void 317 auich_attach(struct device *parent, struct device *self, void *aux) 318 { 319 struct auich_softc *sc = (struct auich_softc *)self; 320 struct pci_attach_args *pa = aux; 321 pci_intr_handle_t ih; 322 bus_size_t mix_size, aud_size; 323 pcireg_t csr; 324 const char *intrstr; 325 const struct auich_devtype *d; 326 u_int16_t ext_id, ext_status; 327 328 d = auich_lookup(pa); 329 if (d == NULL) 330 panic("auich_attach: impossible"); 331 332 printf(": %s\n", d->name); 333 334 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 335 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 336 printf("%s: can't map codec i/o space\n", 337 sc->sc_dev.dv_xname); 338 return; 339 } 340 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 341 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 342 printf("%s: can't map device i/o space\n", 343 sc->sc_dev.dv_xname); 344 return; 345 } 346 sc->dmat = pa->pa_dmat; 347 348 /* enable bus mastering */ 349 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 350 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 351 csr | PCI_COMMAND_MASTER_ENABLE); 352 353 /* Map and establish the interrupt. */ 354 if (pci_intr_map(pa, &ih)) { 355 printf("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 356 return; 357 } 358 intrstr = pci_intr_string(pa->pa_pc, ih); 359 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 360 auich_intr, sc); 361 if (sc->sc_ih == NULL) { 362 printf("%s: can't establish interrupt", sc->sc_dev.dv_xname); 363 if (intrstr != NULL) 364 printf(" at %s", intrstr); 365 printf("\n"); 366 return; 367 } 368 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 369 370 sprintf(sc->sc_audev.name, "%s AC97", d->shortname); 371 sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class)); 372 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 373 374 /* Set up DMA lists. */ 375 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 376 auich_alloc_cdata(sc); 377 378 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 379 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 380 381 /* Reset codec and AC'97 */ 382 auich_reset_codec(sc); 383 384 sc->host_if.arg = sc; 385 sc->host_if.attach = auich_attach_codec; 386 sc->host_if.read = auich_read_codec; 387 sc->host_if.write = auich_write_codec; 388 sc->host_if.reset = auich_reset_codec; 389 390 if (ac97_attach(&sc->host_if) != 0) 391 return; 392 393 auich_read_codec(sc, AC97_REG_EXTENDED_ID, &ext_id); 394 if ((ext_id & (AC97_CODEC_DOES_VRA | AC97_CODEC_DOES_MICVRA)) != 0) { 395 auich_read_codec(sc, AC97_REG_EXTENDED_STATUS, &ext_status); 396 if ((ext_id & AC97_CODEC_DOES_VRA) !=0) 397 ext_status |= AC97_ENAB_VRA; 398 if ((ext_id & AC97_CODEC_DOES_MICVRA) !=0) 399 ext_status |= AC97_ENAB_MICVRA; 400 auich_write_codec(sc, AC97_REG_EXTENDED_STATUS, ext_status); 401 sc->sc_fixed_rate = 0; 402 } else { 403 sc->sc_fixed_rate = 48000; 404 printf("%s: warning, fixed rate codec\n", sc->sc_dev.dv_xname); 405 } 406 407 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 408 409 /* Watch for power change */ 410 sc->sc_suspend = PWR_RESUME; 411 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 412 } 413 414 #define ICH_CODECIO_INTERVAL 10 415 int 416 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 417 { 418 struct auich_softc *sc = v; 419 int i; 420 uint32_t status; 421 422 if (!(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) { 423 printf("auich_read_codec: codec is not ready."); 424 *val = 0xffff; 425 return -1; 426 } 427 /* wait for an access semaphore */ 428 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 429 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 430 DELAY(ICH_CODECIO_INTERVAL)); 431 432 if (i > 0) { 433 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 434 DPRINTF(ICH_DEBUG_CODECIO, 435 ("auich_read_codec(%x, %x)\n", reg, *val)); 436 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 437 if (status & ICH_RCS) { 438 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 439 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 440 *val = 0xffff; 441 } 442 return 0; 443 } else { 444 DPRINTF(ICH_DEBUG_CODECIO, 445 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 446 return -1; 447 } 448 } 449 450 int 451 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 452 { 453 struct auich_softc *sc = v; 454 int i; 455 456 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 457 if (!(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) { 458 printf("auich_write_codec: codec is not ready."); 459 return -1; 460 } 461 /* wait for an access semaphore */ 462 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 463 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 464 DELAY(ICH_CODECIO_INTERVAL)); 465 466 if (i > 0) { 467 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 468 return 0; 469 } else { 470 DPRINTF(ICH_DEBUG_CODECIO, 471 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 472 return -1; 473 } 474 } 475 476 int 477 auich_attach_codec(void *v, struct ac97_codec_if *cif) 478 { 479 struct auich_softc *sc = v; 480 481 sc->codec_if = cif; 482 return 0; 483 } 484 485 void 486 auich_reset_codec(void *v) 487 { 488 struct auich_softc *sc = v; 489 int i; 490 491 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, 0); 492 DELAY(10); 493 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, ICH_CRESET); 494 495 for (i = 500000; i-- && 496 !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR); 497 DELAY(1)); /* or ICH_SCR? */ 498 } 499 500 int 501 auich_open(void *v, int flags) 502 { 503 504 return 0; 505 } 506 507 void 508 auich_close(void *v) 509 { 510 struct auich_softc *sc = v; 511 512 auich_halt_output(sc); 513 auich_halt_input(sc); 514 515 sc->sc_pintr = NULL; 516 sc->sc_rintr = NULL; 517 } 518 519 int 520 auich_query_encoding(void *v, struct audio_encoding *aep) 521 { 522 523 switch (aep->index) { 524 case 0: 525 strcpy(aep->name, AudioEulinear); 526 aep->encoding = AUDIO_ENCODING_ULINEAR; 527 aep->precision = 8; 528 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 529 return (0); 530 case 1: 531 strcpy(aep->name, AudioEmulaw); 532 aep->encoding = AUDIO_ENCODING_ULAW; 533 aep->precision = 8; 534 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 535 return (0); 536 case 2: 537 strcpy(aep->name, AudioEalaw); 538 aep->encoding = AUDIO_ENCODING_ALAW; 539 aep->precision = 8; 540 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 541 return (0); 542 case 3: 543 strcpy(aep->name, AudioEslinear); 544 aep->encoding = AUDIO_ENCODING_SLINEAR; 545 aep->precision = 8; 546 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 547 return (0); 548 case 4: 549 strcpy(aep->name, AudioEslinear_le); 550 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 551 aep->precision = 16; 552 aep->flags = 0; 553 return (0); 554 case 5: 555 strcpy(aep->name, AudioEulinear_le); 556 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 557 aep->precision = 16; 558 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 559 return (0); 560 case 6: 561 strcpy(aep->name, AudioEslinear_be); 562 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 563 aep->precision = 16; 564 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 565 return (0); 566 case 7: 567 strcpy(aep->name, AudioEulinear_be); 568 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 569 aep->precision = 16; 570 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 571 return (0); 572 default: 573 return (EINVAL); 574 } 575 } 576 577 int 578 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 579 struct audio_params *rec) 580 { 581 struct auich_softc *sc = v; 582 struct audio_params *p; 583 int mode; 584 u_int16_t val, rate, inout; 585 586 for (mode = AUMODE_RECORD; mode != -1; 587 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 588 if ((setmode & mode) == 0) 589 continue; 590 591 p = mode == AUMODE_PLAY ? play : rec; 592 if (p == NULL) 593 continue; 594 595 inout = mode == AUMODE_PLAY ? ICH_PM_PCMO : ICH_PM_PCMI; 596 597 if ((p->sample_rate != 8000) && 598 (p->sample_rate != 11025) && 599 (p->sample_rate != 16000) && 600 (p->sample_rate != 22050) && 601 (p->sample_rate != 32000) && 602 (p->sample_rate != 44100) && 603 (p->sample_rate != 48000)) 604 return (EINVAL); 605 606 p->factor = 1; 607 if (p->precision == 8) 608 p->factor *= 2; 609 610 p->sw_code = NULL; 611 /* setup hardware formats */ 612 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 613 p->hw_precision = 16; 614 if (p->channels < 2) 615 p->hw_channels = 2; 616 switch (p->encoding) { 617 case AUDIO_ENCODING_SLINEAR_BE: 618 if (p->precision == 16) { 619 p->sw_code = swap_bytes; 620 } else { 621 if (mode == AUMODE_PLAY) 622 p->sw_code = linear8_to_linear16_le; 623 else 624 p->sw_code = linear16_to_linear8_le; 625 } 626 break; 627 628 case AUDIO_ENCODING_SLINEAR_LE: 629 if (p->precision != 16) { 630 if (mode == AUMODE_PLAY) 631 p->sw_code = linear8_to_linear16_le; 632 else 633 p->sw_code = linear16_to_linear8_le; 634 } 635 break; 636 637 case AUDIO_ENCODING_ULINEAR_BE: 638 if (p->precision == 16) { 639 if (mode == AUMODE_PLAY) 640 p->sw_code = 641 swap_bytes_change_sign16_le; 642 else 643 p->sw_code = 644 change_sign16_swap_bytes_le; 645 } else { 646 if (mode == AUMODE_PLAY) 647 p->sw_code = 648 ulinear8_to_slinear16_le; 649 else 650 p->sw_code = 651 slinear16_to_ulinear8_le; 652 } 653 break; 654 655 case AUDIO_ENCODING_ULINEAR_LE: 656 if (p->precision == 16) { 657 p->sw_code = change_sign16_le; 658 } else { 659 if (mode == AUMODE_PLAY) 660 p->sw_code = 661 ulinear8_to_slinear16_le; 662 else 663 p->sw_code = 664 slinear16_to_ulinear8_le; 665 } 666 break; 667 668 case AUDIO_ENCODING_ULAW: 669 if (mode == AUMODE_PLAY) { 670 p->sw_code = mulaw_to_slinear16_le; 671 } else { 672 p->sw_code = slinear16_to_mulaw_le; 673 } 674 break; 675 676 case AUDIO_ENCODING_ALAW: 677 if (mode == AUMODE_PLAY) { 678 p->sw_code = alaw_to_slinear16_le; 679 } else { 680 p->sw_code = slinear16_to_alaw_le; 681 } 682 break; 683 684 default: 685 return (EINVAL); 686 } 687 688 auich_read_codec(sc, AC97_REG_POWER, &val); 689 auich_write_codec(sc, AC97_REG_POWER, val | inout); 690 691 if (sc->sc_fixed_rate) { 692 p->hw_sample_rate = sc->sc_fixed_rate; 693 } else { 694 if (mode == AUMODE_PLAY) { 695 auich_write_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, 696 p->sample_rate); 697 auich_read_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, 698 &rate); 699 } else { 700 auich_write_codec(sc, AC97_REG_PCM_LR_ADC_RATE, 701 p->sample_rate); 702 auich_read_codec(sc, AC97_REG_PCM_LR_ADC_RATE, 703 &rate); 704 } 705 p->hw_sample_rate = rate; 706 } 707 708 auich_write_codec(sc, AC97_REG_POWER, val); 709 } 710 711 return (0); 712 } 713 714 int 715 auich_round_blocksize(void *v, int blk) 716 { 717 718 return (blk & ~0x3f); /* keep good alignment */ 719 } 720 721 int 722 auich_halt_output(void *v) 723 { 724 struct auich_softc *sc = v; 725 726 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 727 728 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 729 730 return (0); 731 } 732 733 int 734 auich_halt_input(void *v) 735 { 736 struct auich_softc *sc = v; 737 738 DPRINTF(ICH_DEBUG_DMA, 739 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 740 741 /* XXX halt both unless known otherwise */ 742 743 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 744 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 745 746 return (0); 747 } 748 749 int 750 auich_getdev(void *v, struct audio_device *adp) 751 { 752 struct auich_softc *sc = v; 753 754 *adp = sc->sc_audev; 755 return (0); 756 } 757 758 int 759 auich_set_port(void *v, mixer_ctrl_t *cp) 760 { 761 struct auich_softc *sc = v; 762 763 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 764 } 765 766 int 767 auich_get_port(void *v, mixer_ctrl_t *cp) 768 { 769 struct auich_softc *sc = v; 770 771 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 772 } 773 774 int 775 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 776 { 777 struct auich_softc *sc = v; 778 779 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 780 } 781 782 void * 783 auich_allocm(void *v, int direction, size_t size, int pool, int flags) 784 { 785 struct auich_softc *sc = v; 786 struct auich_dma *p; 787 int error; 788 789 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 790 return (NULL); 791 792 p = malloc(sizeof(*p), pool, flags|M_ZERO); 793 if (p == NULL) 794 return (NULL); 795 796 error = auich_allocmem(sc, size, 0, p); 797 if (error) { 798 free(p, pool); 799 return (NULL); 800 } 801 802 p->next = sc->sc_dmas; 803 sc->sc_dmas = p; 804 805 return (KERNADDR(p)); 806 } 807 808 void 809 auich_freem(void *v, void *ptr, int pool) 810 { 811 struct auich_softc *sc = v; 812 struct auich_dma *p, **pp; 813 814 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 815 if (KERNADDR(p) == ptr) { 816 auich_freemem(sc, p); 817 *pp = p->next; 818 free(p, pool); 819 return; 820 } 821 } 822 } 823 824 size_t 825 auich_round_buffersize(void *v, int direction, size_t size) 826 { 827 828 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 829 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 830 831 return size; 832 } 833 834 paddr_t 835 auich_mappage(void *v, void *mem, off_t off, int prot) 836 { 837 struct auich_softc *sc = v; 838 struct auich_dma *p; 839 840 if (off < 0) 841 return (-1); 842 843 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 844 ; 845 if (!p) 846 return (-1); 847 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 848 off, prot, BUS_DMA_WAITOK)); 849 } 850 851 int 852 auich_get_props(void *v) 853 { 854 855 return (AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | 856 AUDIO_PROP_FULLDUPLEX); 857 } 858 859 int 860 auich_intr(void *v) 861 { 862 struct auich_softc *sc = v; 863 int ret = 0, sts, gsts, i, qptr; 864 865 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 866 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 867 868 if (gsts & ICH_POINT) { 869 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+ICH_STS); 870 DPRINTF(ICH_DEBUG_DMA, 871 ("auich_intr: osts=0x%x\n", sts)); 872 873 if (sts & ICH_FIFOE) { 874 printf("%s: fifo underrun # %u\n", 875 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 876 } 877 878 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 879 if (sts & (ICH_LVBCI | ICH_CELV)) { 880 struct auich_dmalist *q; 881 882 qptr = sc->ptr_pcmo; 883 884 while (qptr != i) { 885 q = &sc->dmalist_pcmo[qptr]; 886 887 q->base = sc->pcmo_p; 888 q->len = (sc->pcmo_blksize / 2) | ICH_DMAF_IOC; 889 DPRINTF(ICH_DEBUG_DMA, 890 ("auich_intr: %p, %p = %x @ 0x%x\n", 891 &sc->dmalist_pcmo[i], q, 892 sc->pcmo_blksize / 2, sc->pcmo_p)); 893 894 sc->pcmo_p += sc->pcmo_blksize; 895 if (sc->pcmo_p >= sc->pcmo_end) 896 sc->pcmo_p = sc->pcmo_start; 897 898 if (++qptr == ICH_DMALIST_MAX) 899 qptr = 0; 900 } 901 902 sc->ptr_pcmo = qptr; 903 bus_space_write_1(sc->iot, sc->aud_ioh, 904 ICH_PCMO + ICH_LVI, 905 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 906 } 907 908 if (sts & ICH_BCIS && sc->sc_pintr) 909 sc->sc_pintr(sc->sc_parg); 910 911 /* int ack */ 912 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_STS, 913 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 914 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 915 ret++; 916 } 917 918 if (gsts & ICH_PIINT) { 919 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+ICH_STS); 920 DPRINTF(ICH_DEBUG_DMA, 921 ("auich_intr: ists=0x%x\n", sts)); 922 923 if (sts & ICH_FIFOE) { 924 printf("%s: fifo overrun # %u\n", 925 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 926 } 927 928 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 929 if (sts & (ICH_LVBCI | ICH_CELV)) { 930 struct auich_dmalist *q; 931 932 qptr = sc->ptr_pcmi; 933 934 while (qptr != i) { 935 q = &sc->dmalist_pcmi[qptr]; 936 937 q->base = sc->pcmi_p; 938 q->len = (sc->pcmi_blksize / 2) | ICH_DMAF_IOC; 939 DPRINTF(ICH_DEBUG_DMA, 940 ("auich_intr: %p, %p = %x @ 0x%x\n", 941 &sc->dmalist_pcmi[i], q, 942 sc->pcmi_blksize / 2, sc->pcmi_p)); 943 944 sc->pcmi_p += sc->pcmi_blksize; 945 if (sc->pcmi_p >= sc->pcmi_end) 946 sc->pcmi_p = sc->pcmi_start; 947 948 if (++qptr == ICH_DMALIST_MAX) 949 qptr = 0; 950 } 951 952 sc->ptr_pcmi = qptr; 953 bus_space_write_1(sc->iot, sc->aud_ioh, 954 ICH_PCMI + ICH_LVI, 955 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 956 } 957 958 if (sts & ICH_BCIS && sc->sc_rintr) 959 sc->sc_rintr(sc->sc_rarg); 960 961 /* int ack */ 962 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_STS, 963 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 964 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 965 ret++; 966 } 967 968 if (gsts & ICH_MIINT) { 969 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+ICH_STS); 970 DPRINTF(ICH_DEBUG_DMA, 971 ("auich_intr: ists=0x%x\n", sts)); 972 if (sts & ICH_FIFOE) 973 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 974 975 /* TODO mic input dma */ 976 977 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 978 } 979 980 return ret; 981 } 982 983 int 984 auich_trigger_output(void *v, void *start, void *end, int blksize, 985 void (*intr)(void *), void *arg, struct audio_params *param) 986 { 987 struct auich_softc *sc = v; 988 struct auich_dmalist *q; 989 struct auich_dma *p; 990 size_t size; 991 992 DPRINTF(ICH_DEBUG_DMA, 993 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 994 start, end, blksize, intr, arg, param)); 995 996 sc->sc_pintr = intr; 997 sc->sc_parg = arg; 998 999 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1000 ; 1001 if (!p) { 1002 printf("auich_trigger_output: bad addr %p\n", start); 1003 return (EINVAL); 1004 } 1005 1006 size = (size_t)((caddr_t)end - (caddr_t)start); 1007 1008 /* 1009 * The logic behind this is: 1010 * setup one buffer to play, then LVI dump out the rest 1011 * to the scatter-gather chain. 1012 */ 1013 sc->pcmo_start = DMAADDR(p); 1014 sc->pcmo_p = sc->pcmo_start + blksize; 1015 sc->pcmo_end = sc->pcmo_start + size; 1016 sc->pcmo_blksize = blksize; 1017 1018 sc->ptr_pcmo = 0; 1019 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1020 q->base = sc->pcmo_start; 1021 q->len = (blksize / 2) | ICH_DMAF_IOC; 1022 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1023 sc->ptr_pcmo = 0; 1024 1025 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1026 sc->sc_cddma + ICH_PCMO_OFF(0)); 1027 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1028 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1029 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1030 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1031 1032 return (0); 1033 } 1034 1035 int 1036 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1037 void *v; 1038 void *start, *end; 1039 int blksize; 1040 void (*intr)(void *); 1041 void *arg; 1042 struct audio_params *param; 1043 { 1044 struct auich_softc *sc = v; 1045 struct auich_dmalist *q; 1046 struct auich_dma *p; 1047 size_t size; 1048 1049 DPRINTF(ICH_DEBUG_DMA, 1050 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1051 start, end, blksize, intr, arg, param)); 1052 1053 sc->sc_rintr = intr; 1054 sc->sc_rarg = arg; 1055 1056 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1057 ; 1058 if (!p) { 1059 printf("auich_trigger_input: bad addr %p\n", start); 1060 return (EINVAL); 1061 } 1062 1063 size = (size_t)((caddr_t)end - (caddr_t)start); 1064 1065 /* 1066 * The logic behind this is: 1067 * setup one buffer to play, then LVI dump out the rest 1068 * to the scatter-gather chain. 1069 */ 1070 sc->pcmi_start = DMAADDR(p); 1071 sc->pcmi_p = sc->pcmi_start + blksize; 1072 sc->pcmi_end = sc->pcmi_start + size; 1073 sc->pcmi_blksize = blksize; 1074 1075 sc->ptr_pcmi = 0; 1076 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1077 q->base = sc->pcmi_start; 1078 q->len = (blksize / 2) | ICH_DMAF_IOC; 1079 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1080 sc->ptr_pcmi = 0; 1081 1082 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1083 sc->sc_cddma + ICH_PCMI_OFF(0)); 1084 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1085 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1086 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1087 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1088 1089 return (0); 1090 } 1091 1092 int 1093 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1094 struct auich_dma *p) 1095 { 1096 int error; 1097 1098 p->size = size; 1099 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1100 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1101 &p->nsegs, BUS_DMA_NOWAIT); 1102 if (error) 1103 return (error); 1104 1105 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1106 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1107 if (error) 1108 goto free; 1109 1110 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1111 0, BUS_DMA_NOWAIT, &p->map); 1112 if (error) 1113 goto unmap; 1114 1115 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1116 BUS_DMA_NOWAIT); 1117 if (error) 1118 goto destroy; 1119 return (0); 1120 1121 destroy: 1122 bus_dmamap_destroy(sc->dmat, p->map); 1123 unmap: 1124 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1125 free: 1126 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1127 return (error); 1128 } 1129 1130 int 1131 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1132 { 1133 1134 bus_dmamap_unload(sc->dmat, p->map); 1135 bus_dmamap_destroy(sc->dmat, p->map); 1136 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1137 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1138 return (0); 1139 } 1140 1141 int 1142 auich_alloc_cdata(struct auich_softc *sc) 1143 { 1144 bus_dma_segment_t seg; 1145 int error, rseg; 1146 1147 /* 1148 * Allocate the control data structure, and create and load the 1149 * DMA map for it. 1150 */ 1151 if ((error = bus_dmamem_alloc(sc->dmat, 1152 sizeof(struct auich_cdata), 1153 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1154 printf("%s: unable to allocate control data, error = %d\n", 1155 sc->sc_dev.dv_xname, error); 1156 goto fail_0; 1157 } 1158 1159 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1160 sizeof(struct auich_cdata), 1161 (caddr_t *) &sc->sc_cdata, 1162 BUS_DMA_COHERENT)) != 0) { 1163 printf("%s: unable to map control data, error = %d\n", 1164 sc->sc_dev.dv_xname, error); 1165 goto fail_1; 1166 } 1167 1168 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1169 sizeof(struct auich_cdata), 0, 0, 1170 &sc->sc_cddmamap)) != 0) { 1171 printf("%s: unable to create control data DMA map, " 1172 "error = %d\n", sc->sc_dev.dv_xname, error); 1173 goto fail_2; 1174 } 1175 1176 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1177 sc->sc_cdata, sizeof(struct auich_cdata), 1178 NULL, 0)) != 0) { 1179 printf("%s: unable tp load control data DMA map, " 1180 "error = %d\n", sc->sc_dev.dv_xname, error); 1181 goto fail_3; 1182 } 1183 1184 return (0); 1185 1186 fail_3: 1187 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1188 fail_2: 1189 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1190 sizeof(struct auich_cdata)); 1191 fail_1: 1192 bus_dmamem_free(sc->dmat, &seg, rseg); 1193 fail_0: 1194 return (error); 1195 } 1196 1197 void 1198 auich_powerhook(int why, void *addr) 1199 { 1200 struct auich_softc *sc = (struct auich_softc *)addr; 1201 1202 switch (why) { 1203 case PWR_SUSPEND: 1204 case PWR_STANDBY: 1205 /* Power down */ 1206 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1207 sc->sc_suspend = why; 1208 auich_read_codec(sc, AC97_REG_EXTENDED_STATUS, &sc->ext_status); 1209 break; 1210 1211 case PWR_RESUME: 1212 /* Wake up */ 1213 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1214 if (sc->sc_suspend == PWR_RESUME) { 1215 printf("%s: resume without suspend.\n", 1216 sc->sc_dev.dv_xname); 1217 sc->sc_suspend = why; 1218 return; 1219 } 1220 sc->sc_suspend = why; 1221 auich_reset_codec(sc); 1222 DELAY(1000); 1223 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1224 auich_write_codec(sc, AC97_REG_EXTENDED_STATUS, sc->ext_status); 1225 break; 1226 1227 case PWR_SOFTSUSPEND: 1228 case PWR_SOFTSTANDBY: 1229 case PWR_SOFTRESUME: 1230 break; 1231 } 1232 } 1233
Indexes created Thu Oct 23 22:10:10 GMT 2025