auich.c revision 1.17.2.1
1 /* $NetBSD: auich.c,v 1.17.2.1 2002/08/29 05:22:38 gehenna Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * 107 * TODO: 108 * - Add support for the microphone input. 109 * - 4ch/6ch support. 110 * - auich_calibrate() is called in auich_open(). It causes about 0.1sec 111 * delay in the first open(). auich_calibrate() should be called in 112 * auich_attach(). However microtime() doesn't work in the attach 113 * stage. 114 */ 115 116 #include <sys/cdefs.h> 117 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.17.2.1 2002/08/29 05:22:38 gehenna Exp $"); 118 119 #include <sys/param.h> 120 #include <sys/systm.h> 121 #include <sys/kernel.h> 122 #include <sys/malloc.h> 123 #include <sys/device.h> 124 #include <sys/fcntl.h> 125 #include <sys/proc.h> 126 127 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 128 129 #include <dev/pci/pcidevs.h> 130 #include <dev/pci/pcivar.h> 131 #include <dev/pci/auichreg.h> 132 133 #include <sys/audioio.h> 134 #include <dev/audio_if.h> 135 #include <dev/mulaw.h> 136 #include <dev/auconv.h> 137 138 #include <machine/bus.h> 139 140 #include <dev/ic/ac97reg.h> 141 #include <dev/ic/ac97var.h> 142 143 struct auich_dma { 144 bus_dmamap_t map; 145 caddr_t addr; 146 bus_dma_segment_t segs[1]; 147 int nsegs; 148 size_t size; 149 struct auich_dma *next; 150 }; 151 152 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 153 #define KERNADDR(p) ((void *)((p)->addr)) 154 155 struct auich_cdata { 156 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 157 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 158 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 159 }; 160 161 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 162 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 163 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 164 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 165 166 struct auich_softc { 167 struct device sc_dev; 168 void *sc_ih; 169 170 audio_device_t sc_audev; 171 172 bus_space_tag_t iot; 173 bus_space_handle_t mix_ioh; 174 bus_space_handle_t aud_ioh; 175 bus_dma_tag_t dmat; 176 177 struct ac97_codec_if *codec_if; 178 struct ac97_host_if host_if; 179 180 /* DMA scatter-gather lists. */ 181 bus_dmamap_t sc_cddmamap; 182 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 183 184 struct auich_cdata *sc_cdata; 185 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 186 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 187 #define dmalist_mici sc_cdata->ic_dmalist_mici 188 189 int ptr_pcmo, 190 ptr_pcmi, 191 ptr_mici; 192 193 /* i/o buffer pointers */ 194 u_int32_t pcmo_start, pcmo_p, pcmo_end; 195 int pcmo_blksize, pcmo_fifoe; 196 197 u_int32_t pcmi_start, pcmi_p, pcmi_end; 198 int pcmi_blksize, pcmi_fifoe; 199 200 u_int32_t mici_start, mici_p, mici_end; 201 int mici_blksize, mici_fifoe; 202 203 struct auich_dma *sc_dmas; 204 205 int sc_fixed_rate; 206 int sc_calibrated; /* sc_ac97rate has correct value */ 207 int sc_ac97rate; 208 int sc_ignore_codecready; 209 210 /* SiS 7012 hack */ 211 int sc_sample_size; 212 int sc_sts_reg; 213 214 void (*sc_pintr)(void *); 215 void *sc_parg; 216 217 void (*sc_rintr)(void *); 218 void *sc_rarg; 219 220 /* Power Management */ 221 void *sc_powerhook; 222 int sc_suspend; 223 u_int16_t ext_status; 224 }; 225 226 #define FIXED_RATE 48000 227 228 /* Debug */ 229 #ifdef AUDIO_DEBUG 230 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 231 int auich_debug = 0xfffe; 232 #define ICH_DEBUG_CODECIO 0x0001 233 #define ICH_DEBUG_DMA 0x0002 234 #define ICH_DEBUG_PARAM 0x0004 235 #else 236 #define DPRINTF(x,y) /* nothing */ 237 #endif 238 239 int auich_match(struct device *, struct cfdata *, void *); 240 void auich_attach(struct device *, struct device *, void *); 241 int auich_intr(void *); 242 243 struct cfattach auich_ca = { 244 sizeof(struct auich_softc), auich_match, auich_attach 245 }; 246 247 int auich_open(void *, int); 248 void auich_close(void *); 249 int auich_query_encoding(void *, struct audio_encoding *); 250 int auich_set_params(void *, int, int, struct audio_params *, 251 struct audio_params *); 252 int auich_round_blocksize(void *, int); 253 int auich_halt_output(void *); 254 int auich_halt_input(void *); 255 int auich_getdev(void *, struct audio_device *); 256 int auich_set_port(void *, mixer_ctrl_t *); 257 int auich_get_port(void *, mixer_ctrl_t *); 258 int auich_query_devinfo(void *, mixer_devinfo_t *); 259 void *auich_allocm(void *, int, size_t, int, int); 260 void auich_freem(void *, void *, int); 261 size_t auich_round_buffersize(void *, int, size_t); 262 paddr_t auich_mappage(void *, void *, off_t, int); 263 int auich_get_props(void *); 264 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 265 void *, struct audio_params *); 266 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 267 void *, struct audio_params *); 268 269 int auich_alloc_cdata(struct auich_softc *); 270 271 int auich_allocmem(struct auich_softc *, size_t, size_t, 272 struct auich_dma *); 273 int auich_freemem(struct auich_softc *, struct auich_dma *); 274 275 void auich_powerhook(int, void *); 276 int auich_set_rate(struct auich_softc *sc, int mode, uint srate); 277 unsigned int auich_calibrate(struct auich_softc *sc); 278 279 280 struct audio_hw_if auich_hw_if = { 281 auich_open, 282 auich_close, 283 NULL, /* drain */ 284 auich_query_encoding, 285 auich_set_params, 286 auich_round_blocksize, 287 NULL, /* commit_setting */ 288 NULL, /* init_output */ 289 NULL, /* init_input */ 290 NULL, /* start_output */ 291 NULL, /* start_input */ 292 auich_halt_output, 293 auich_halt_input, 294 NULL, /* speaker_ctl */ 295 auich_getdev, 296 NULL, /* getfd */ 297 auich_set_port, 298 auich_get_port, 299 auich_query_devinfo, 300 auich_allocm, 301 auich_freem, 302 auich_round_buffersize, 303 auich_mappage, 304 auich_get_props, 305 auich_trigger_output, 306 auich_trigger_input, 307 NULL, /* dev_ioctl */ 308 }; 309 310 int auich_attach_codec(void *, struct ac97_codec_if *); 311 int auich_read_codec(void *, u_int8_t, u_int16_t *); 312 int auich_write_codec(void *, u_int8_t, u_int16_t); 313 void auich_reset_codec(void *); 314 315 static const struct auich_devtype { 316 int vendor; 317 int product; 318 const char *name; 319 const char *shortname; 320 } auich_devices[] = { 321 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 322 "i82801AA (ICH) AC-97 Audio", "ICH" }, 323 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 324 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, /* i810-L */ 325 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 326 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 327 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 328 "i82440MX AC-97 Audio", "440MX" }, 329 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 330 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, /* i830Mx i845MP/MZ*/ 331 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 332 "i82801DB (ICH4) AC-97 Audio", "ICH4" }, /* i845E i845Gx */ 333 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 334 "SiS 7012 AC-97 Audio", "SiS7012" }, 335 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 336 "nForce MCP AC-97 Audio", "nForce-MCP" }, 337 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 338 "AMD768 AC-97 Audio", "AMD768" }, 339 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 340 "AMD8111 AC-97 Audio", "AMD8111" }, 341 { 0, 342 NULL, NULL }, 343 }; 344 345 static const struct auich_devtype * 346 auich_lookup(struct pci_attach_args *pa) 347 { 348 const struct auich_devtype *d; 349 350 for (d = auich_devices; d->name != NULL; d++) { 351 if (PCI_VENDOR(pa->pa_id) == d->vendor 352 && PCI_PRODUCT(pa->pa_id) == d->product) 353 return (d); 354 } 355 356 return (NULL); 357 } 358 359 int 360 auich_match(struct device *parent, struct cfdata *match, void *aux) 361 { 362 struct pci_attach_args *pa = aux; 363 364 if (auich_lookup(pa) != NULL) 365 return (1); 366 367 return (0); 368 } 369 370 void 371 auich_attach(struct device *parent, struct device *self, void *aux) 372 { 373 struct auich_softc *sc = (struct auich_softc *)self; 374 struct pci_attach_args *pa = aux; 375 pci_intr_handle_t ih; 376 bus_size_t mix_size, aud_size; 377 pcireg_t csr; 378 const char *intrstr; 379 const struct auich_devtype *d; 380 u_int16_t ext_id, ext_status; 381 u_int32_t status; 382 383 d = auich_lookup(pa); 384 if (d == NULL) 385 panic("auich_attach: impossible"); 386 387 printf(": %s\n", d->name); 388 389 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 390 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 391 printf("%s: can't map codec i/o space\n", 392 sc->sc_dev.dv_xname); 393 return; 394 } 395 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 396 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 397 printf("%s: can't map device i/o space\n", 398 sc->sc_dev.dv_xname); 399 return; 400 } 401 sc->dmat = pa->pa_dmat; 402 403 /* enable bus mastering */ 404 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 405 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 406 csr | PCI_COMMAND_MASTER_ENABLE); 407 408 /* Map and establish the interrupt. */ 409 if (pci_intr_map(pa, &ih)) { 410 printf("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 411 return; 412 } 413 intrstr = pci_intr_string(pa->pa_pc, ih); 414 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 415 auich_intr, sc); 416 if (sc->sc_ih == NULL) { 417 printf("%s: can't establish interrupt", sc->sc_dev.dv_xname); 418 if (intrstr != NULL) 419 printf(" at %s", intrstr); 420 printf("\n"); 421 return; 422 } 423 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 424 425 sprintf(sc->sc_audev.name, "%s AC97", d->shortname); 426 sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class)); 427 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 428 429 /* SiS 7012 needs special handling */ 430 if (d->vendor == PCI_VENDOR_SIS 431 && d->product == PCI_PRODUCT_SIS_7012_AC) { 432 sc->sc_sts_reg = ICH_PICB; 433 sc->sc_sample_size = 1; 434 } else { 435 sc->sc_sts_reg = ICH_STS; 436 sc->sc_sample_size = 2; 437 } 438 439 /* Set up DMA lists. */ 440 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 441 auich_alloc_cdata(sc); 442 443 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 444 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 445 446 sc->sc_ac97rate = FIXED_RATE; 447 /* Reset codec and AC'97 */ 448 auich_reset_codec(sc); 449 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 450 if (!(status & ICH_PCR)) { /* reset failure */ 451 if (d->vendor == PCI_VENDOR_INTEL 452 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) { 453 /* MSI 845G Max never return ICH_PCR */ 454 sc->sc_ignore_codecready = TRUE; 455 } else { 456 return; 457 } 458 } 459 /* Print capabilities though there are no supports for now */ 460 if ((status & ICH_SAMPLE_CAP) == ICH_POM20) 461 printf("%s: 20 bit precision support\n", sc->sc_dev.dv_xname); 462 if ((status & ICH_CHAN_CAP) == ICH_PCM4) 463 printf("%s: 4ch PCM output support\n", sc->sc_dev.dv_xname); 464 if ((status & ICH_CHAN_CAP) == ICH_PCM6) 465 printf("%s: 6ch PCM output support\n", sc->sc_dev.dv_xname); 466 467 sc->host_if.arg = sc; 468 sc->host_if.attach = auich_attach_codec; 469 sc->host_if.read = auich_read_codec; 470 sc->host_if.write = auich_write_codec; 471 sc->host_if.reset = auich_reset_codec; 472 473 if (ac97_attach(&sc->host_if) != 0) 474 return; 475 476 auich_read_codec(sc, AC97_REG_EXTENDED_ID, &ext_id); 477 if ((ext_id & (AC97_CODEC_DOES_VRA | AC97_CODEC_DOES_MICVRA)) != 0) { 478 auich_read_codec(sc, AC97_REG_EXTENDED_STATUS, &ext_status); 479 if ((ext_id & AC97_CODEC_DOES_VRA) !=0) 480 ext_status |= AC97_ENAB_VRA; 481 if ((ext_id & AC97_CODEC_DOES_MICVRA) !=0) 482 ext_status |= AC97_ENAB_MICVRA; 483 auich_write_codec(sc, AC97_REG_EXTENDED_STATUS, ext_status); 484 485 /* so it claims to do variable rate, let's make sure */ 486 if (auich_set_rate(sc, AUMODE_PLAY, 44100) == 44100) 487 sc->sc_fixed_rate = 0; 488 else 489 sc->sc_fixed_rate = FIXED_RATE; 490 } else { 491 sc->sc_fixed_rate = FIXED_RATE; 492 } 493 if (sc->sc_fixed_rate) 494 printf("%s: warning, fixed rate codec\n", sc->sc_dev.dv_xname); 495 496 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 497 498 /* Watch for power change */ 499 sc->sc_suspend = PWR_RESUME; 500 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 501 } 502 503 #define ICH_CODECIO_INTERVAL 10 504 int 505 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 506 { 507 struct auich_softc *sc = v; 508 int i; 509 uint32_t status; 510 511 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 512 if (!sc->sc_ignore_codecready && !(status & ICH_PCR)) { 513 printf("auich_read_codec: codec is not ready (0x%x)\n", status); 514 *val = 0xffff; 515 return -1; 516 } 517 /* wait for an access semaphore */ 518 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 519 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 520 DELAY(ICH_CODECIO_INTERVAL)); 521 522 if (i > 0) { 523 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 524 DPRINTF(ICH_DEBUG_CODECIO, 525 ("auich_read_codec(%x, %x)\n", reg, *val)); 526 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 527 if (status & ICH_RCS) { 528 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 529 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 530 *val = 0xffff; 531 } 532 return 0; 533 } else { 534 DPRINTF(ICH_DEBUG_CODECIO, 535 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 536 return -1; 537 } 538 } 539 540 int 541 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 542 { 543 struct auich_softc *sc = v; 544 int i; 545 546 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 547 if (!sc->sc_ignore_codecready 548 && !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) { 549 printf("auich_write_codec: codec is not ready."); 550 return -1; 551 } 552 /* wait for an access semaphore */ 553 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 554 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 555 DELAY(ICH_CODECIO_INTERVAL)); 556 557 if (i > 0) { 558 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 559 return 0; 560 } else { 561 DPRINTF(ICH_DEBUG_CODECIO, 562 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 563 return -1; 564 } 565 } 566 567 int 568 auich_attach_codec(void *v, struct ac97_codec_if *cif) 569 { 570 struct auich_softc *sc = v; 571 572 sc->codec_if = cif; 573 return 0; 574 } 575 576 void 577 auich_reset_codec(void *v) 578 { 579 struct auich_softc *sc = v; 580 int i; 581 uint32_t control; 582 583 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 584 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 585 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 586 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 587 588 for (i = 500000; i-- && 589 !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR); 590 DELAY(1)); /* or ICH_SCR? */ 591 if (i <= 0) 592 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 593 } 594 595 int 596 auich_open(void *v, int flags) 597 { 598 struct auich_softc *sc = v; 599 600 if (!sc->sc_fixed_rate && !sc->sc_calibrated) { 601 sc->sc_ac97rate = auich_calibrate(sc); 602 sc->sc_calibrated = TRUE; 603 } 604 return 0; 605 } 606 607 void 608 auich_close(void *v) 609 { 610 struct auich_softc *sc = v; 611 612 auich_halt_output(sc); 613 auich_halt_input(sc); 614 615 sc->sc_pintr = NULL; 616 sc->sc_rintr = NULL; 617 } 618 619 int 620 auich_query_encoding(void *v, struct audio_encoding *aep) 621 { 622 623 switch (aep->index) { 624 case 0: 625 strcpy(aep->name, AudioEulinear); 626 aep->encoding = AUDIO_ENCODING_ULINEAR; 627 aep->precision = 8; 628 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 629 return (0); 630 case 1: 631 strcpy(aep->name, AudioEmulaw); 632 aep->encoding = AUDIO_ENCODING_ULAW; 633 aep->precision = 8; 634 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 635 return (0); 636 case 2: 637 strcpy(aep->name, AudioEalaw); 638 aep->encoding = AUDIO_ENCODING_ALAW; 639 aep->precision = 8; 640 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 641 return (0); 642 case 3: 643 strcpy(aep->name, AudioEslinear); 644 aep->encoding = AUDIO_ENCODING_SLINEAR; 645 aep->precision = 8; 646 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 647 return (0); 648 case 4: 649 strcpy(aep->name, AudioEslinear_le); 650 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 651 aep->precision = 16; 652 aep->flags = 0; 653 return (0); 654 case 5: 655 strcpy(aep->name, AudioEulinear_le); 656 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 657 aep->precision = 16; 658 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 659 return (0); 660 case 6: 661 strcpy(aep->name, AudioEslinear_be); 662 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 663 aep->precision = 16; 664 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 665 return (0); 666 case 7: 667 strcpy(aep->name, AudioEulinear_be); 668 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 669 aep->precision = 16; 670 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 671 return (0); 672 default: 673 return (EINVAL); 674 } 675 } 676 677 int 678 auich_set_rate(struct auich_softc *sc, int mode, uint srate) 679 { 680 u_int16_t val, rate, inout; 681 u_int32_t rvalue; 682 683 inout = mode == AUMODE_PLAY ? ICH_PM_PCMO : ICH_PM_PCMI; 684 685 auich_read_codec(sc, AC97_REG_POWER, &val); 686 auich_write_codec(sc, AC97_REG_POWER, val | inout); 687 688 rvalue = srate * FIXED_RATE / sc->sc_ac97rate; 689 if (mode == AUMODE_PLAY) { 690 auich_write_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, rvalue); 691 auich_read_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, &rate); 692 } else { 693 auich_write_codec(sc, AC97_REG_PCM_LR_ADC_RATE, rvalue); 694 auich_read_codec(sc, AC97_REG_PCM_LR_ADC_RATE, &rate); 695 } 696 697 auich_write_codec(sc, AC97_REG_POWER, val); 698 699 /* Cast to avoid integer overflow */ 700 rvalue = (u_int32_t)rate * sc->sc_ac97rate / FIXED_RATE; 701 return rvalue; 702 } 703 704 int 705 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 706 struct audio_params *rec) 707 { 708 struct auich_softc *sc = v; 709 struct audio_params *p; 710 int mode; 711 712 for (mode = AUMODE_RECORD; mode != -1; 713 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 714 if ((setmode & mode) == 0) 715 continue; 716 717 p = mode == AUMODE_PLAY ? play : rec; 718 if (p == NULL) 719 continue; 720 721 if ((p->sample_rate != 8000) && 722 (p->sample_rate != 11025) && 723 (p->sample_rate != 16000) && 724 (p->sample_rate != 22050) && 725 (p->sample_rate != 32000) && 726 (p->sample_rate != 44100) && 727 (p->sample_rate != 48000)) 728 return (EINVAL); 729 730 p->factor = 1; 731 if (p->precision == 8) 732 p->factor *= 2; 733 734 p->sw_code = NULL; 735 /* setup hardware formats */ 736 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 737 p->hw_precision = 16; 738 739 /* If manaural is requested, aurateconv expands a monaural 740 * stream to stereo. */ 741 if (p->channels < 2) 742 p->hw_channels = 2; 743 744 switch (p->encoding) { 745 case AUDIO_ENCODING_SLINEAR_BE: 746 if (p->precision == 16) { 747 p->sw_code = swap_bytes; 748 } else { 749 if (mode == AUMODE_PLAY) 750 p->sw_code = linear8_to_linear16_le; 751 else 752 p->sw_code = linear16_to_linear8_le; 753 } 754 break; 755 756 case AUDIO_ENCODING_SLINEAR_LE: 757 if (p->precision != 16) { 758 if (mode == AUMODE_PLAY) 759 p->sw_code = linear8_to_linear16_le; 760 else 761 p->sw_code = linear16_to_linear8_le; 762 } 763 break; 764 765 case AUDIO_ENCODING_ULINEAR_BE: 766 if (p->precision == 16) { 767 if (mode == AUMODE_PLAY) 768 p->sw_code = 769 swap_bytes_change_sign16_le; 770 else 771 p->sw_code = 772 change_sign16_swap_bytes_le; 773 } else { 774 if (mode == AUMODE_PLAY) 775 p->sw_code = 776 ulinear8_to_slinear16_le; 777 else 778 p->sw_code = 779 slinear16_to_ulinear8_le; 780 } 781 break; 782 783 case AUDIO_ENCODING_ULINEAR_LE: 784 if (p->precision == 16) { 785 p->sw_code = change_sign16_le; 786 } else { 787 if (mode == AUMODE_PLAY) 788 p->sw_code = 789 ulinear8_to_slinear16_le; 790 else 791 p->sw_code = 792 slinear16_to_ulinear8_le; 793 } 794 break; 795 796 case AUDIO_ENCODING_ULAW: 797 if (mode == AUMODE_PLAY) { 798 p->sw_code = mulaw_to_slinear16_le; 799 } else { 800 p->sw_code = slinear16_to_mulaw_le; 801 } 802 break; 803 804 case AUDIO_ENCODING_ALAW: 805 if (mode == AUMODE_PLAY) { 806 p->sw_code = alaw_to_slinear16_le; 807 } else { 808 p->sw_code = slinear16_to_alaw_le; 809 } 810 break; 811 812 default: 813 return (EINVAL); 814 } 815 816 if (sc->sc_fixed_rate) { 817 p->hw_sample_rate = sc->sc_fixed_rate; 818 } else { 819 p->hw_sample_rate = auich_set_rate(sc, mode, 820 p->sample_rate); 821 } 822 /* If hw_sample_rate is different from sample_rate, aurateconv 823 * works. */ 824 } 825 826 return (0); 827 } 828 829 int 830 auich_round_blocksize(void *v, int blk) 831 { 832 833 return (blk & ~0x3f); /* keep good alignment */ 834 } 835 836 int 837 auich_halt_output(void *v) 838 { 839 struct auich_softc *sc = v; 840 841 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 842 843 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 844 845 return (0); 846 } 847 848 int 849 auich_halt_input(void *v) 850 { 851 struct auich_softc *sc = v; 852 853 DPRINTF(ICH_DEBUG_DMA, 854 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 855 856 /* XXX halt both unless known otherwise */ 857 858 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 859 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 860 861 return (0); 862 } 863 864 int 865 auich_getdev(void *v, struct audio_device *adp) 866 { 867 struct auich_softc *sc = v; 868 869 *adp = sc->sc_audev; 870 return (0); 871 } 872 873 int 874 auich_set_port(void *v, mixer_ctrl_t *cp) 875 { 876 struct auich_softc *sc = v; 877 878 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 879 } 880 881 int 882 auich_get_port(void *v, mixer_ctrl_t *cp) 883 { 884 struct auich_softc *sc = v; 885 886 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 887 } 888 889 int 890 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 891 { 892 struct auich_softc *sc = v; 893 894 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 895 } 896 897 void * 898 auich_allocm(void *v, int direction, size_t size, int pool, int flags) 899 { 900 struct auich_softc *sc = v; 901 struct auich_dma *p; 902 int error; 903 904 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 905 return (NULL); 906 907 p = malloc(sizeof(*p), pool, flags|M_ZERO); 908 if (p == NULL) 909 return (NULL); 910 911 error = auich_allocmem(sc, size, 0, p); 912 if (error) { 913 free(p, pool); 914 return (NULL); 915 } 916 917 p->next = sc->sc_dmas; 918 sc->sc_dmas = p; 919 920 return (KERNADDR(p)); 921 } 922 923 void 924 auich_freem(void *v, void *ptr, int pool) 925 { 926 struct auich_softc *sc = v; 927 struct auich_dma *p, **pp; 928 929 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 930 if (KERNADDR(p) == ptr) { 931 auich_freemem(sc, p); 932 *pp = p->next; 933 free(p, pool); 934 return; 935 } 936 } 937 } 938 939 size_t 940 auich_round_buffersize(void *v, int direction, size_t size) 941 { 942 943 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 944 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 945 946 return size; 947 } 948 949 paddr_t 950 auich_mappage(void *v, void *mem, off_t off, int prot) 951 { 952 struct auich_softc *sc = v; 953 struct auich_dma *p; 954 955 if (off < 0) 956 return (-1); 957 958 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 959 ; 960 if (!p) 961 return (-1); 962 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 963 off, prot, BUS_DMA_WAITOK)); 964 } 965 966 int 967 auich_get_props(void *v) 968 { 969 970 return (AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | 971 AUDIO_PROP_FULLDUPLEX); 972 } 973 974 int 975 auich_intr(void *v) 976 { 977 struct auich_softc *sc = v; 978 int ret = 0, sts, gsts, i, qptr; 979 980 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 981 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 982 983 if (gsts & ICH_POINT) { 984 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 985 DPRINTF(ICH_DEBUG_DMA, 986 ("auich_intr: osts=0x%x\n", sts)); 987 988 if (sts & ICH_FIFOE) { 989 printf("%s: fifo underrun # %u\n", 990 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 991 } 992 993 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 994 if (sts & (ICH_LVBCI | ICH_CELV)) { 995 struct auich_dmalist *q; 996 997 qptr = sc->ptr_pcmo; 998 999 while (qptr != i) { 1000 q = &sc->dmalist_pcmo[qptr]; 1001 1002 q->base = sc->pcmo_p; 1003 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1004 DPRINTF(ICH_DEBUG_DMA, 1005 ("auich_intr: %p, %p = %x @ 0x%x\n", 1006 &sc->dmalist_pcmo[i], q, 1007 sc->pcmo_blksize / 2, sc->pcmo_p)); 1008 1009 sc->pcmo_p += sc->pcmo_blksize; 1010 if (sc->pcmo_p >= sc->pcmo_end) 1011 sc->pcmo_p = sc->pcmo_start; 1012 1013 if (++qptr == ICH_DMALIST_MAX) 1014 qptr = 0; 1015 } 1016 1017 sc->ptr_pcmo = qptr; 1018 bus_space_write_1(sc->iot, sc->aud_ioh, 1019 ICH_PCMO + ICH_LVI, 1020 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1021 } 1022 1023 if (sts & ICH_BCIS && sc->sc_pintr) 1024 sc->sc_pintr(sc->sc_parg); 1025 1026 /* int ack */ 1027 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1028 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1029 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1030 ret++; 1031 } 1032 1033 if (gsts & ICH_PIINT) { 1034 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1035 DPRINTF(ICH_DEBUG_DMA, 1036 ("auich_intr: ists=0x%x\n", sts)); 1037 1038 if (sts & ICH_FIFOE) { 1039 printf("%s: fifo overrun # %u\n", 1040 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1041 } 1042 1043 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1044 if (sts & (ICH_LVBCI | ICH_CELV)) { 1045 struct auich_dmalist *q; 1046 1047 qptr = sc->ptr_pcmi; 1048 1049 while (qptr != i) { 1050 q = &sc->dmalist_pcmi[qptr]; 1051 1052 q->base = sc->pcmi_p; 1053 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1054 DPRINTF(ICH_DEBUG_DMA, 1055 ("auich_intr: %p, %p = %x @ 0x%x\n", 1056 &sc->dmalist_pcmi[i], q, 1057 sc->pcmi_blksize / 2, sc->pcmi_p)); 1058 1059 sc->pcmi_p += sc->pcmi_blksize; 1060 if (sc->pcmi_p >= sc->pcmi_end) 1061 sc->pcmi_p = sc->pcmi_start; 1062 1063 if (++qptr == ICH_DMALIST_MAX) 1064 qptr = 0; 1065 } 1066 1067 sc->ptr_pcmi = qptr; 1068 bus_space_write_1(sc->iot, sc->aud_ioh, 1069 ICH_PCMI + ICH_LVI, 1070 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1071 } 1072 1073 if (sts & ICH_BCIS && sc->sc_rintr) 1074 sc->sc_rintr(sc->sc_rarg); 1075 1076 /* int ack */ 1077 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1078 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1079 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1080 ret++; 1081 } 1082 1083 if (gsts & ICH_MIINT) { 1084 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1085 DPRINTF(ICH_DEBUG_DMA, 1086 ("auich_intr: ists=0x%x\n", sts)); 1087 if (sts & ICH_FIFOE) 1088 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1089 1090 /* TODO mic input dma */ 1091 1092 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1093 } 1094 1095 return ret; 1096 } 1097 1098 int 1099 auich_trigger_output(void *v, void *start, void *end, int blksize, 1100 void (*intr)(void *), void *arg, struct audio_params *param) 1101 { 1102 struct auich_softc *sc = v; 1103 struct auich_dmalist *q; 1104 struct auich_dma *p; 1105 size_t size; 1106 1107 DPRINTF(ICH_DEBUG_DMA, 1108 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1109 start, end, blksize, intr, arg, param)); 1110 1111 sc->sc_pintr = intr; 1112 sc->sc_parg = arg; 1113 1114 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1115 ; 1116 if (!p) { 1117 printf("auich_trigger_output: bad addr %p\n", start); 1118 return (EINVAL); 1119 } 1120 1121 size = (size_t)((caddr_t)end - (caddr_t)start); 1122 1123 /* 1124 * The logic behind this is: 1125 * setup one buffer to play, then LVI dump out the rest 1126 * to the scatter-gather chain. 1127 */ 1128 sc->pcmo_start = DMAADDR(p); 1129 sc->pcmo_p = sc->pcmo_start + blksize; 1130 sc->pcmo_end = sc->pcmo_start + size; 1131 sc->pcmo_blksize = blksize; 1132 1133 sc->ptr_pcmo = 0; 1134 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1135 q->base = sc->pcmo_start; 1136 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1137 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1138 sc->ptr_pcmo = 0; 1139 1140 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1141 sc->sc_cddma + ICH_PCMO_OFF(0)); 1142 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1143 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1144 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1145 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1146 1147 return (0); 1148 } 1149 1150 int 1151 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1152 void *v; 1153 void *start, *end; 1154 int blksize; 1155 void (*intr)(void *); 1156 void *arg; 1157 struct audio_params *param; 1158 { 1159 struct auich_softc *sc = v; 1160 struct auich_dmalist *q; 1161 struct auich_dma *p; 1162 size_t size; 1163 1164 DPRINTF(ICH_DEBUG_DMA, 1165 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1166 start, end, blksize, intr, arg, param)); 1167 1168 sc->sc_rintr = intr; 1169 sc->sc_rarg = arg; 1170 1171 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1172 ; 1173 if (!p) { 1174 printf("auich_trigger_input: bad addr %p\n", start); 1175 return (EINVAL); 1176 } 1177 1178 size = (size_t)((caddr_t)end - (caddr_t)start); 1179 1180 /* 1181 * The logic behind this is: 1182 * setup one buffer to play, then LVI dump out the rest 1183 * to the scatter-gather chain. 1184 */ 1185 sc->pcmi_start = DMAADDR(p); 1186 sc->pcmi_p = sc->pcmi_start + blksize; 1187 sc->pcmi_end = sc->pcmi_start + size; 1188 sc->pcmi_blksize = blksize; 1189 1190 sc->ptr_pcmi = 0; 1191 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1192 q->base = sc->pcmi_start; 1193 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1194 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1195 sc->ptr_pcmi = 0; 1196 1197 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1198 sc->sc_cddma + ICH_PCMI_OFF(0)); 1199 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1200 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1201 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1202 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1203 1204 return (0); 1205 } 1206 1207 int 1208 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1209 struct auich_dma *p) 1210 { 1211 int error; 1212 1213 p->size = size; 1214 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1215 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1216 &p->nsegs, BUS_DMA_NOWAIT); 1217 if (error) 1218 return (error); 1219 1220 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1221 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1222 if (error) 1223 goto free; 1224 1225 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1226 0, BUS_DMA_NOWAIT, &p->map); 1227 if (error) 1228 goto unmap; 1229 1230 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1231 BUS_DMA_NOWAIT); 1232 if (error) 1233 goto destroy; 1234 return (0); 1235 1236 destroy: 1237 bus_dmamap_destroy(sc->dmat, p->map); 1238 unmap: 1239 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1240 free: 1241 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1242 return (error); 1243 } 1244 1245 int 1246 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1247 { 1248 1249 bus_dmamap_unload(sc->dmat, p->map); 1250 bus_dmamap_destroy(sc->dmat, p->map); 1251 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1252 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1253 return (0); 1254 } 1255 1256 int 1257 auich_alloc_cdata(struct auich_softc *sc) 1258 { 1259 bus_dma_segment_t seg; 1260 int error, rseg; 1261 1262 /* 1263 * Allocate the control data structure, and create and load the 1264 * DMA map for it. 1265 */ 1266 if ((error = bus_dmamem_alloc(sc->dmat, 1267 sizeof(struct auich_cdata), 1268 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1269 printf("%s: unable to allocate control data, error = %d\n", 1270 sc->sc_dev.dv_xname, error); 1271 goto fail_0; 1272 } 1273 1274 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1275 sizeof(struct auich_cdata), 1276 (caddr_t *) &sc->sc_cdata, 1277 BUS_DMA_COHERENT)) != 0) { 1278 printf("%s: unable to map control data, error = %d\n", 1279 sc->sc_dev.dv_xname, error); 1280 goto fail_1; 1281 } 1282 1283 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1284 sizeof(struct auich_cdata), 0, 0, 1285 &sc->sc_cddmamap)) != 0) { 1286 printf("%s: unable to create control data DMA map, " 1287 "error = %d\n", sc->sc_dev.dv_xname, error); 1288 goto fail_2; 1289 } 1290 1291 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1292 sc->sc_cdata, sizeof(struct auich_cdata), 1293 NULL, 0)) != 0) { 1294 printf("%s: unable tp load control data DMA map, " 1295 "error = %d\n", sc->sc_dev.dv_xname, error); 1296 goto fail_3; 1297 } 1298 1299 return (0); 1300 1301 fail_3: 1302 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1303 fail_2: 1304 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1305 sizeof(struct auich_cdata)); 1306 fail_1: 1307 bus_dmamem_free(sc->dmat, &seg, rseg); 1308 fail_0: 1309 return (error); 1310 } 1311 1312 void 1313 auich_powerhook(int why, void *addr) 1314 { 1315 struct auich_softc *sc = (struct auich_softc *)addr; 1316 1317 switch (why) { 1318 case PWR_SUSPEND: 1319 case PWR_STANDBY: 1320 /* Power down */ 1321 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1322 sc->sc_suspend = why; 1323 auich_read_codec(sc, AC97_REG_EXTENDED_STATUS, &sc->ext_status); 1324 break; 1325 1326 case PWR_RESUME: 1327 /* Wake up */ 1328 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1329 if (sc->sc_suspend == PWR_RESUME) { 1330 printf("%s: resume without suspend.\n", 1331 sc->sc_dev.dv_xname); 1332 sc->sc_suspend = why; 1333 return; 1334 } 1335 sc->sc_suspend = why; 1336 auich_reset_codec(sc); 1337 DELAY(1000); 1338 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1339 auich_write_codec(sc, AC97_REG_EXTENDED_STATUS, sc->ext_status); 1340 break; 1341 1342 case PWR_SOFTSUSPEND: 1343 case PWR_SOFTSTANDBY: 1344 case PWR_SOFTRESUME: 1345 break; 1346 } 1347 } 1348 1349 1350 /* -------------------------------------------------------------------- */ 1351 /* Calibrate card (some boards are overclocked and need scaling) */ 1352 1353 unsigned int 1354 auich_calibrate(struct auich_softc *sc) 1355 { 1356 struct timeval t1, t2; 1357 u_int8_t ociv, nciv; 1358 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1359 void *temp_buffer; 1360 struct auich_dma *p; 1361 1362 ac97rate = 48000; 1363 /* 1364 * Grab audio from input for fixed interval and compare how 1365 * much we actually get with what we expect. Interval needs 1366 * to be sufficiently short that no interrupts are 1367 * generated. 1368 */ 1369 1370 /* Setup a buffer */ 1371 bytes = 16000; 1372 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1373 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1374 ; 1375 if (p == NULL) { 1376 printf("auich_calibrate: bad address %p\n", temp_buffer); 1377 return ac97rate; 1378 } 1379 sc->dmalist_pcmi[0].base = DMAADDR(p); 1380 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size) | ICH_DMAF_IOC; 1381 1382 /* 1383 * our data format is stereo, 16 bit so each sample is 4 bytes. 1384 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1385 * we're going to start recording with interrupts disabled and measure 1386 * the time taken for one block to complete. we know the block size, 1387 * we know the time in microseconds, we calculate the sample rate: 1388 * 1389 * actual_rate [bps] = bytes / (time [s] * 4) 1390 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1391 * actual_rate [Hz] = (bytes * 250000) / time [us] 1392 */ 1393 1394 /* prepare */ 1395 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1396 nciv = ociv; 1397 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1398 sc->sc_cddma + ICH_PCMI_OFF(0)); 1399 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1400 (0 - 1) & ICH_LVI_MASK); 1401 1402 /* start */ 1403 microtime(&t1); 1404 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1405 1406 /* wait */ 1407 while (nciv == ociv) { 1408 microtime(&t2); 1409 if (t2.tv_sec - t1.tv_sec > 1) 1410 break; 1411 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1412 ICH_PCMI + ICH_CIV); 1413 } 1414 microtime(&t2); 1415 1416 /* stop */ 1417 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1418 1419 /* reset */ 1420 DELAY(100); 1421 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1422 1423 /* turn time delta into us */ 1424 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1425 1426 auich_freem(sc, temp_buffer, M_DEVBUF); 1427 1428 if (nciv == ociv) { 1429 printf("%s: ac97 link rate calibration timed out after %d us\n", 1430 sc->sc_dev.dv_xname, wait_us); 1431 return ac97rate; 1432 } 1433 1434 actual_48k_rate = (bytes * 250000) / wait_us; 1435 1436 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 1437 ac97rate = actual_48k_rate; 1438 } 1439 1440 if (ac97rate != 48000) { 1441 printf("%s: measured ac97 link rate at %d Hz", 1442 sc->sc_dev.dv_xname, actual_48k_rate); 1443 if (ac97rate != actual_48k_rate) 1444 printf(", will use %d Hz", ac97rate); 1445 printf("\n"); 1446 } 1447 1448 return ac97rate; 1449 } 1450
Indexes created Thu Oct 23 18:09:57 GMT 2025